From: Peter Maydell <peter.maydell@linaro.org>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "Bin Meng" <bin.meng@windriver.com>,
"QEMU Developers" <qemu-devel@nongnu.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
qemu-arm <qemu-arm@nongnu.org>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Jean-Christophe Dubois" <jcd@tribudubois.net>
Subject: Re: [PATCH v8 06/10] hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled
Date: Thu, 28 Jan 2021 13:34:08 +0000 [thread overview]
Message-ID: <CAFEAcA9cjJo8W6oOF0uASQDGLuXUdgURkammsXkJOsLkaZU3fw@mail.gmail.com> (raw)
In-Reply-To: <1611063546-20278-7-git-send-email-bmeng.cn@gmail.com>
On Tue, 19 Jan 2021 at 13:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> When the block is disabled, only the ECSPI_CONREG register can
> be modified. Setting the EN bit enabled the device, clearing it
> "disables the block and resets the internal logic with the
> exception of the ECSPI_CONREG" register.
>
> Ignore all other registers write except ECSPI_CONREG when the
> block is disabled.
>
> Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM),
> chapter 21.7.3: Control Register (ECSPIx_CONREG)
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Message-Id: <20210115153049.3353008-6-f4bug@amsat.org>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
next prev parent reply other threads:[~2021-01-28 13:36 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-19 13:38 [PATCH v8 00/10] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Bin Meng
2021-01-19 13:38 ` [PATCH v8 01/10] hw/ssi: imx_spi: Use a macro for number of chip selects supported Bin Meng
2021-01-19 13:38 ` [PATCH v8 02/10] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() Bin Meng
2021-01-28 13:34 ` Peter Maydell
2021-01-19 13:38 ` [PATCH v8 03/10] hw/ssi: imx_spi: Remove pointless variable initialization Bin Meng
2021-01-19 13:39 ` [PATCH v8 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value Bin Meng
2021-01-28 13:43 ` Peter Maydell
2021-01-28 13:46 ` Bin Meng
2021-01-28 13:54 ` Peter Maydell
2021-01-28 14:15 ` Bin Meng
2021-01-28 14:17 ` Philippe Mathieu-Daudé
2021-01-28 14:22 ` Peter Maydell
2021-01-28 14:32 ` Philippe Mathieu-Daudé
2021-01-28 14:41 ` Peter Maydell
2021-01-28 14:49 ` Philippe Mathieu-Daudé
2021-01-28 15:00 ` Bin Meng
2021-01-19 13:39 ` [PATCH v8 05/10] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled Bin Meng
2021-01-19 13:39 ` [PATCH v8 06/10] hw/ssi: imx_spi: Rework imx_spi_write() " Bin Meng
2021-01-28 13:34 ` Peter Maydell [this message]
2021-01-19 13:39 ` [PATCH v8 07/10] hw/ssi: imx_spi: Disable chip selects when controller is disabled Bin Meng
2021-01-19 13:39 ` [PATCH v8 08/10] hw/ssi: imx_spi: Round up the burst length to be multiple of 8 Bin Meng
2021-01-28 13:50 ` Peter Maydell
2021-01-19 13:39 ` [PATCH v8 09/10] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Bin Meng
2021-01-19 13:39 ` [PATCH v8 10/10] hw/ssi: imx_spi: Correct tx and rx fifo endianness Bin Meng
2021-01-28 13:32 ` Peter Maydell
2021-01-22 13:36 ` [PATCH v8 00/10] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Bin Meng
2021-01-28 7:15 ` Bin Meng
2021-01-28 13:51 ` Peter Maydell
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