From: Peter Maydell <peter.maydell@linaro.org>
To: Ard Biesheuvel <ardb@kernel.org>
Cc: "Eduardo Habkost" <ehabkost@redhat.com>,
"Sergio Lopez" <slp@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"QEMU Developers" <qemu-devel@nongnu.org>,
"Cameron Esfahani" <dirty@apple.com>,
"Roman Bolshakov" <r.bolshakov@yadro.com>,
"Alexander Graf" <agraf@csgraf.de>,
qemu-arm <qemu-arm@nongnu.org>, "Frank Yang" <lfy@google.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Peter Collingbourne" <pcc@google.com>
Subject: Re: [PATCH v11 06/10] hvf: arm: Implement -cpu host
Date: Thu, 16 Sep 2021 17:16:38 +0100 [thread overview]
Message-ID: <CAFEAcA8yd6m-S90Uq1G=HTYFAerp6cZdJk9B=CFrHMn5tEMZ5w@mail.gmail.com> (raw)
In-Reply-To: <CAMj1kXEEN+J4k_Kib8gRHcy8v1vVRwk7c847yT_Kuv+jnLf9ww@mail.gmail.com>
On Thu, 16 Sept 2021 at 17:05, Ard Biesheuvel <ardb@kernel.org> wrote:
> I'd argue that compliance with the architecture means that the
> software should not clear RES1 bits
Architecturally, RES1 means that "software
* Must not rely on the bit reading as 1.
* Must use an SBOP policy to write to the bit."
(SBOP=="should be 1 or preserved", ie you can preserve the existing value,
as in "read register, change some bits, write back", or you can write a 1.)
> but I don't think we can blame it
> for not touching bits that were in in invalid state upon entry.
SCTLR_EL1.SPAN == 0 is perfectly valid for a CPU that supports the
PAN feature. It's just not the value OVMF wants, so OVMF should
be setting it to what it does want. Also, as the first thing to
run after reset (ie firmware) OVMF absolutely is responsible for
dealing with system registers which have UNKNOWN values out of
reset.
Put another way, if you want to argue that this is an "invalid
state" you need to point to the specification that defines
the valid state that OVMF should see when it is handed control.
-- PMM
next prev parent reply other threads:[~2021-09-16 16:41 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-15 18:10 [PATCH v11 00/10] hvf: Implement Apple Silicon Support Alexander Graf
2021-09-15 18:10 ` [PATCH v11 01/10] arm: Move PMC register definitions to cpu.h Alexander Graf
2021-09-16 10:38 ` Peter Maydell
2021-09-15 18:10 ` [PATCH v11 02/10] hvf: Add execute to dirty log permission bitmap Alexander Graf
2021-09-16 11:59 ` Peter Maydell
2021-09-16 14:04 ` Alexander Graf
2021-09-16 14:05 ` Peter Maydell
2021-09-15 18:10 ` [PATCH v11 03/10] hvf: Introduce hvf_arch_init() callback Alexander Graf
2021-09-16 10:45 ` Peter Maydell
2021-09-15 18:10 ` [PATCH v11 04/10] hvf: Add Apple Silicon support Alexander Graf
2021-09-16 12:16 ` Peter Maydell
2021-09-15 18:10 ` [PATCH v11 05/10] arm/hvf: Add a WFI handler Alexander Graf
2021-09-16 4:49 ` Philippe Mathieu-Daudé
2021-09-16 15:02 ` Alexander Graf
2021-09-16 12:18 ` Peter Maydell
2021-09-15 18:10 ` [PATCH v11 06/10] hvf: arm: Implement -cpu host Alexander Graf
2021-09-16 12:24 ` Peter Maydell
2021-09-16 15:30 ` Alexander Graf
2021-09-16 15:55 ` Peter Maydell
2021-09-16 16:05 ` Ard Biesheuvel
2021-09-16 16:16 ` Peter Maydell [this message]
2021-09-22 11:41 ` Ard Biesheuvel
2021-09-22 12:44 ` Peter Maydell
2021-09-22 16:10 ` Ard Biesheuvel
2021-09-16 17:47 ` Alexander Graf
2021-09-15 18:10 ` [PATCH v11 07/10] hvf: arm: Implement PSCI handling Alexander Graf
2021-09-16 12:27 ` Peter Maydell
2021-09-15 18:10 ` [PATCH v11 08/10] arm: Add Hypervisor.framework build target Alexander Graf
2021-09-15 18:10 ` [PATCH v11 09/10] hvf: arm: Add rudimentary PMC support Alexander Graf
2021-09-16 12:32 ` Peter Maydell
2021-09-15 18:10 ` [PATCH v11 10/10] arm: tcg: Adhere to SMCCC 1.3 section 5.2 Alexander Graf
2021-09-16 12:29 ` Peter Maydell
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