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From: Chen-Yu Tsai <wens@csie.org>
To: "André Przywara" <andre.przywara@arm.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Maxime Ripard <mripard@kernel.org>,
	Jernej Skrabec <jernej.skrabec@siol.net>,
	Icenowy Zheng <icenowy@aosc.io>,
	linux-clk <linux-clk@vger.kernel.org>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	linux-sunxi <linux-sunxi@googlegroups.com>
Subject: Re: [linux-sunxi] [PATCH] clk: sunxi-ng: h6: Fix CEC clock
Date: Thu, 7 Jan 2021 00:06:11 +0800	[thread overview]
Message-ID: <CAGb2v66G+4yUsCZmfuzbC4-8AbpQgtN=Jt=4-7iXUTb+F429AQ@mail.gmail.com> (raw)
In-Reply-To: <20210106143246.11255-1-andre.przywara@arm.com>

On Wed, Jan 6, 2021 at 10:33 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> The CEC clock on the H6 SoC is a bit special, since it uses a fixed
> pre-dividier for one source clock (the PLL), but conveys the other clock
> (32K OSC) directly.
> We are using a fixed predivider array for that, but fail to use the right
> flag to actually activate that.
>
> Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
> Reported-by: Jernej Skrabec <jernej.skrabec@siol.net>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Acked-by: Chen-Yu Tsai <wens@csie.org>

WARNING: multiple messages have this Message-ID (diff)
From: Chen-Yu Tsai <wens@csie.org>
To: "André Przywara" <andre.przywara@arm.com>
Cc: Jernej Skrabec <jernej.skrabec@siol.net>,
	Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Maxime Ripard <mripard@kernel.org>,
	linux-sunxi <linux-sunxi@googlegroups.com>,
	linux-clk <linux-clk@vger.kernel.org>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	Icenowy Zheng <icenowy@aosc.io>
Subject: Re: [linux-sunxi] [PATCH] clk: sunxi-ng: h6: Fix CEC clock
Date: Thu, 7 Jan 2021 00:06:11 +0800	[thread overview]
Message-ID: <CAGb2v66G+4yUsCZmfuzbC4-8AbpQgtN=Jt=4-7iXUTb+F429AQ@mail.gmail.com> (raw)
In-Reply-To: <20210106143246.11255-1-andre.przywara@arm.com>

On Wed, Jan 6, 2021 at 10:33 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> The CEC clock on the H6 SoC is a bit special, since it uses a fixed
> pre-dividier for one source clock (the PLL), but conveys the other clock
> (32K OSC) directly.
> We are using a fixed predivider array for that, but fail to use the right
> flag to actually activate that.
>
> Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
> Reported-by: Jernej Skrabec <jernej.skrabec@siol.net>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Acked-by: Chen-Yu Tsai <wens@csie.org>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-01-06 16:07 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-06 14:32 [PATCH] clk: sunxi-ng: h6: Fix CEC clock Andre Przywara
2021-01-06 14:32 ` Andre Przywara
2021-01-06 16:06 ` Chen-Yu Tsai [this message]
2021-01-06 16:06   ` [linux-sunxi] " Chen-Yu Tsai
2021-01-06 16:51 ` Maxime Ripard
2021-01-06 16:51   ` Maxime Ripard

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