From: Chen-Yu Tsai <wens@csie.org> To: 李扬韬 <frank@allwinnertech.com> Cc: "Maxime Ripard" <maxime@cerno.tech>, robh+dt <robh+dt@kernel.org>, mturquette <mturquette@baylibre.com>, sboyd <sboyd@kernel.org>, "linus.walleij" <linus.walleij@linaro.org>, "p.zabel" <p.zabel@pengutronix.de>, 黄烁生 <huangshuosheng@allwinnertech.com>, "tiny.windzz" <tiny.windzz@gmail.com>, linux-arm-kernel <linux-arm-kernel@lists.infradead.org>, devicetree <devicetree@vger.kernel.org>, linux-kernel <linux-kernel@vger.kernel.org>, linux-clk <linux-clk@vger.kernel.org>, linux-gpio <linux-gpio@vger.kernel.org> Subject: Re: [PATCH 1/4] clk: sunxi-ng: add support for the Allwinner A100 CCU Date: Wed, 3 Jun 2020 17:48:44 +0800 [thread overview] Message-ID: <CAGb2v66rZpX-+DK_MnP7RRp7LL7GrXTd1ExpE6z_AjKDVjVwNg@mail.gmail.com> (raw) In-Reply-To: <d7d6ee84-bfbb-4fef-9ed8-1f7045494594.frank@allwinnertech.com> On Wed, Jun 3, 2020 at 5:42 PM 李扬韬 <frank@allwinnertech.com> wrote: > > >> + /* Enable the lock bits on all PLLs */ > >> + for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { > >> + val = readl(reg + pll_regs[i]); > >> + val |= BIT(29); > > > >Having a define for that would be nice here > > > >> + writel(val, reg + pll_regs[i]); > >> + } > >> + > >> + /* > >> + * In order to pass the EMI certification, the SDM function of > >> + * the peripheral 1 bus is enabled, and the frequency is still > >> + * calculated using the previous division factor. > >> + */ > >> + writel(0xd1303333, reg + SUN50I_A100_PLL_PERIPH1_PATTERN0_REG); > > > >Same here > > Having a define? I don’t quite understand what you mean, > can you give me an example? What Maxime means is that 0xd1303333 is a magic number. It is better to make a properly named macro, or many macros that you then bitwise-OR together. So you should make macros for each bitfield in that register, which would likely include the SDM calculation factors, the enable bit, and any other fields. ChenYu > MBR, > Yangtao
WARNING: multiple messages have this Message-ID (diff)
From: Chen-Yu Tsai <wens@csie.org> To: 李扬韬 <frank@allwinnertech.com> Cc: devicetree <devicetree@vger.kernel.org>, linux-gpio <linux-gpio@vger.kernel.org>, sboyd <sboyd@kernel.org>, mturquette <mturquette@baylibre.com>, linux-kernel <linux-kernel@vger.kernel.org>, linux-clk <linux-clk@vger.kernel.org>, "tiny.windzz" <tiny.windzz@gmail.com>, robh+dt <robh+dt@kernel.org>, 黄烁生 <huangshuosheng@allwinnertech.com>, "Maxime Ripard" <maxime@cerno.tech>, "p.zabel" <p.zabel@pengutronix.de>, "linus.walleij" <linus.walleij@linaro.org>, linux-arm-kernel <linux-arm-kernel@lists.infradead.org> Subject: Re: [PATCH 1/4] clk: sunxi-ng: add support for the Allwinner A100 CCU Date: Wed, 3 Jun 2020 17:48:44 +0800 [thread overview] Message-ID: <CAGb2v66rZpX-+DK_MnP7RRp7LL7GrXTd1ExpE6z_AjKDVjVwNg@mail.gmail.com> (raw) In-Reply-To: <d7d6ee84-bfbb-4fef-9ed8-1f7045494594.frank@allwinnertech.com> On Wed, Jun 3, 2020 at 5:42 PM 李扬韬 <frank@allwinnertech.com> wrote: > > >> + /* Enable the lock bits on all PLLs */ > >> + for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { > >> + val = readl(reg + pll_regs[i]); > >> + val |= BIT(29); > > > >Having a define for that would be nice here > > > >> + writel(val, reg + pll_regs[i]); > >> + } > >> + > >> + /* > >> + * In order to pass the EMI certification, the SDM function of > >> + * the peripheral 1 bus is enabled, and the frequency is still > >> + * calculated using the previous division factor. > >> + */ > >> + writel(0xd1303333, reg + SUN50I_A100_PLL_PERIPH1_PATTERN0_REG); > > > >Same here > > Having a define? I don’t quite understand what you mean, > can you give me an example? What Maxime means is that 0xd1303333 is a magic number. It is better to make a properly named macro, or many macros that you then bitwise-OR together. So you should make macros for each bitfield in that register, which would likely include the SDM calculation factors, the enable bit, and any other fields. ChenYu > MBR, > Yangtao _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-06-03 9:49 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-05-22 3:07 [PATCH 0/4] Allwinner A100 Initial support Frank Lee 2020-05-22 3:07 ` Frank Lee 2020-05-22 3:07 ` [PATCH 1/4] clk: sunxi-ng: add support for the Allwinner A100 CCU Frank Lee 2020-05-22 3:07 ` Frank Lee 2020-05-22 15:14 ` Maxime Ripard 2020-05-22 15:14 ` Maxime Ripard 2020-06-03 9:42 ` 回复:[PATCH " 李扬韬 2020-06-03 9:48 ` Chen-Yu Tsai [this message] 2020-06-03 9:48 ` [PATCH " Chen-Yu Tsai 2020-05-22 3:07 ` [PATCH 2/4] pinctrl: sunxi: add support for the Allwinner A100 pin controller Frank Lee 2020-05-22 3:07 ` Frank Lee 2020-05-22 15:28 ` Maxime Ripard 2020-05-22 15:28 ` Maxime Ripard 2020-06-03 9:44 ` 回复:[PATCH " 李扬韬 2020-06-05 15:13 ` Maxime Ripard 2020-06-05 15:13 ` Maxime Ripard 2020-06-16 9:26 ` Frank Lee 2020-06-20 21:27 ` Linus Walleij 2020-05-22 3:07 ` [PATCH 3/4] arm64: allwinner: A100: add the basical Allwinner A100 DTSI file Frank Lee 2020-05-22 3:07 ` Frank Lee 2020-05-22 3:07 ` [PATCH 4/4] arm64: allwinner: A100: add support for Allwinner Perf1 board Frank Lee 2020-05-22 3:07 ` Frank Lee 2020-05-22 15:31 ` Maxime Ripard 2020-05-22 15:31 ` Maxime Ripard 2020-05-22 15:02 ` [PATCH 0/4] Allwinner A100 Initial support Maxime Ripard 2020-05-22 15:02 ` Maxime Ripard
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