From: Jerome Glisse <j.glisse@gmail.com>
To: "Christian König" <deathsimple@vodafone.de>
Cc: dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 15/16] drm/radeon: implement ring commit tracking
Date: Mon, 9 Jul 2012 11:36:10 -0400 [thread overview]
Message-ID: <CAH3drwZxECAdOPCj5=F_GuXBZA2+w-siJ0Ox4Wu=hWCK8O3-Fw@mail.gmail.com> (raw)
In-Reply-To: <1341830523-30320-16-git-send-email-deathsimple@vodafone.de>
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On Mon, Jul 9, 2012 at 6:42 AM, Christian König <deathsimple@vodafone.de> wrote:
> Signed-off-by: Christian König <deathsimple@vodafone.de>
Bit too complex to my taste, what about attached patch, it's lot
simpler. (Haven't tested
the patch but it should work)
Cheers,
Jerome
> ---
> drivers/gpu/drm/radeon/radeon.h | 3 +++
> drivers/gpu/drm/radeon/radeon_ring.c | 39 ++++++++++++++++++++++++++++++++--
> 2 files changed, 40 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
> index fef4257..9c11be8 100644
> --- a/drivers/gpu/drm/radeon/radeon.h
> +++ b/drivers/gpu/drm/radeon/radeon.h
> @@ -637,6 +637,9 @@ struct radeon_ring {
> u32 ptr_reg_shift;
> u32 ptr_reg_mask;
> u32 nop;
> + unsigned *track_back;
> + unsigned track_ptr;
> + unsigned track_mask;
> };
>
> /*
> diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
> index d9b2e45..994c98c 100644
> --- a/drivers/gpu/drm/radeon/radeon_ring.c
> +++ b/drivers/gpu/drm/radeon/radeon_ring.c
> @@ -276,6 +276,8 @@ void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring)
> DRM_MEMORYBARRIER();
> WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask);
> (void)RREG32(ring->wptr_reg);
> + ring->track_back[ring->track_ptr++] = ring->wptr_old;
> + ring->track_ptr &= ring->track_mask;
> }
>
> void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring)
> @@ -362,6 +364,27 @@ bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *rin
> return false;
> }
>
> +static unsigned radeon_ring_first_valid_commit(struct radeon_ring *ring)
> +{
> + unsigned i, c, result = ring->track_ptr;
> + i = ring->track_ptr - 1;
> + while (i != ring->track_ptr) {
> + i &= ring->track_mask;
> + c = ring->track_back[i];
> +
> + if (ring->wptr >= ring->rptr) {
> + if (c < ring->rptr || c >= ring->wptr)
> + break;
> + } else {
> + if (c < ring->rptr && c >= ring->wptr)
> + break;
> + }
> +
> + result = i--;
> + }
> + return result;
> +}
> +
> int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring,
> unsigned ring_size, unsigned align,
> unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
> @@ -403,6 +426,10 @@ int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring,
> dev_err(rdev->dev, "(%d) ring map failed\n", r);
> return r;
> }
> + ring->track_back = kmalloc(ring_size / align, GFP_KERNEL);
> + memset(ring->track_back, 0, ring_size / align);
> + ring->track_ptr = 0;
> + ring->track_mask = ((ring->ring_size / 4) / align) - 1;
> }
> ring->ptr_mask = (ring->ring_size / 4) - 1;
> ring->ring_free_dw = ring->ring_size / 4;
> @@ -422,6 +449,7 @@ void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring)
> ring->ready = false;
> ring->ring = NULL;
> ring->ring_obj = NULL;
> + kfree(ring->track_back);
> mutex_unlock(&rdev->ring_lock);
>
> if (ring_obj) {
> @@ -447,7 +475,7 @@ static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
> struct radeon_device *rdev = dev->dev_private;
> int ridx = *(int*)node->info_ent->data;
> struct radeon_ring *ring = &rdev->ring[ridx];
> - unsigned count, i, j;
> + unsigned count, i, j, commit;
>
> radeon_ring_free_size(rdev, ring);
> count = (ring->ring_size / 4) - ring->ring_free_dw;
> @@ -457,9 +485,16 @@ static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
> seq_printf(m, "driver's copy of the rptr: 0x%08x\n", ring->rptr);
> seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
> seq_printf(m, "%u dwords in ring\n", count);
> + commit = radeon_ring_first_valid_commit(ring);
> i = ring->rptr;
> for (j = 0; j <= count; j++) {
> - seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
> + seq_printf(m, "r[%04x]=0x%08x", i, ring->ring[i]);
> + if (commit != ring->track_ptr && ring->track_back[commit] == i) {
> + seq_printf(m, " <-");
> + ++commit;
> + commit &= ring->track_mask;
> + }
> + seq_printf(m, "\n");
> i = (i + 1) & ring->ptr_mask;
> }
> return 0;
> --
> 1.7.9.5
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
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From ed90755e625673c98684191ac0bd9436149e416b Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Mon, 9 Jul 2012 11:30:17 -0400
Subject: [PATCH] drm/radeon: record what is next valid wptr for each ring
Before emitting any indirect buffer, emit the offset of the next
valid ring content if any. This allow code that want to resume
ring to resume ring right after ib that caused GPU lockup.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
drivers/gpu/drm/radeon/evergreen.c | 17 ++++++++++++++++-
drivers/gpu/drm/radeon/ni.c | 17 +++++++++++++++++
drivers/gpu/drm/radeon/r600.c | 16 +++++++++++++++-
drivers/gpu/drm/radeon/radeon.h | 14 ++++++++------
drivers/gpu/drm/radeon/radeon_device.c | 3 +++
drivers/gpu/drm/radeon/si.c | 16 ++++++++++++++++
6 files changed, 75 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index eef6048..633efe8 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1376,7 +1376,22 @@ void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
/* set to DX10/11 mode */
radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
radeon_ring_write(ring, 1);
- /* FIXME: implement */
+
+ if (rdev->wb.enabled) {
+ u64 next_rptr_gaddr;
+ /* next rptr is wptr + 5 dw for mem_write and 4 for indirect_buffer */
+ u32 next_rptr = ring->wptr + 5 + 4;
+
+ next_rptr_gaddr = rdev->wb.gpu_addr + RADEON_WB_RING0_NEXT_RPTR;
+ next_rptr_gaddr += ring->id * 4;
+ WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
+ radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
+ radeon_ring_write(ring, next_rptr_gaddr & 0xfffffffc);
+ radeon_ring_write(ring, upper_32_bits(next_rptr_gaddr) & 0xff | (1 << 18));
+ radeon_ring_write(ring, next_rptr);
+ radeon_ring_write(ring, 0);
+ }
+
radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
radeon_ring_write(ring,
#ifdef __BIG_ENDIAN
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 5397fad..ca2f0d0 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -872,6 +872,23 @@ void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
/* set to DX10/11 mode */
radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
radeon_ring_write(ring, 1);
+
+ if (rdev->wb.enabled) {
+ u64 next_rptr_gaddr;
+ /* next rptr is wptr + 5 dw for mem_write and 4 for indirect_buffer
+ * and 8 dword for coherency and flush */
+ u32 next_rptr = ring->wptr + 5 + 4 + 8;
+
+ next_rptr_gaddr = rdev->wb.gpu_addr + RADEON_WB_RING0_NEXT_RPTR;
+ next_rptr_gaddr += ring->id * 4;
+ WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
+ radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
+ radeon_ring_write(ring, next_rptr_gaddr & 0xfffffffc);
+ radeon_ring_write(ring, upper_32_bits(next_rptr_gaddr) & 0xff | (1 << 18));
+ radeon_ring_write(ring, next_rptr);
+ radeon_ring_write(ring, 0);
+ }
+
radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
radeon_ring_write(ring,
#ifdef __BIG_ENDIAN
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index b3c0e0f..7bca9d5 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2617,7 +2617,21 @@ void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
{
struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
- /* FIXME: implement */
+ if (rdev->wb.enabled) {
+ u64 next_rptr_gaddr;
+ /* next rptr is wptr + 5 dw for mem_write and 4 for indirect_buffer */
+ u32 next_rptr = ring->wptr + 5 + 4;
+
+ next_rptr_gaddr = rdev->wb.gpu_addr + RADEON_WB_RING0_NEXT_RPTR;
+ next_rptr_gaddr += ring->id * 4;
+ WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
+ radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
+ radeon_ring_write(ring, next_rptr_gaddr & 0xfffffffc);
+ radeon_ring_write(ring, upper_32_bits(next_rptr_gaddr) & 0xff | (1 << 18));
+ radeon_ring_write(ring, next_rptr);
+ radeon_ring_write(ring, 0);
+ }
+
radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
radeon_ring_write(ring,
#ifdef __BIG_ENDIAN
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index fefcca5..f3dd970 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -639,6 +639,7 @@ struct radeon_ib {
struct radeon_ring {
struct radeon_bo *ring_obj;
volatile uint32_t *ring;
+ unsigned id;
unsigned rptr;
unsigned rptr_offs;
unsigned rptr_reg;
@@ -890,12 +891,13 @@ struct radeon_wb {
bool use_event;
};
-#define RADEON_WB_SCRATCH_OFFSET 0
-#define RADEON_WB_CP_RPTR_OFFSET 1024
-#define RADEON_WB_CP1_RPTR_OFFSET 1280
-#define RADEON_WB_CP2_RPTR_OFFSET 1536
-#define R600_WB_IH_WPTR_OFFSET 2048
-#define R600_WB_EVENT_OFFSET 3072
+#define RADEON_WB_SCRATCH_OFFSET 0
+#define RADEON_WB_RING0_NEXT_RPTR 256
+#define RADEON_WB_CP_RPTR_OFFSET 1024
+#define RADEON_WB_CP1_RPTR_OFFSET 1280
+#define RADEON_WB_CP2_RPTR_OFFSET 1536
+#define R600_WB_IH_WPTR_OFFSET 2048
+#define R600_WB_EVENT_OFFSET 3072
/**
* struct radeon_pm - power management datas
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 653f352..53f4591 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -721,6 +721,9 @@ int radeon_device_init(struct radeon_device *rdev,
rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
rdev->accel_working = false;
+ for (i = 0; i < RADEON_NUM_RINGS; i++) {
+ rdev->ring[i].id = i;
+ }
DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
radeon_family_name[rdev->family], pdev->vendor, pdev->device,
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index a9eb826..e880aed 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1765,6 +1765,22 @@ void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
u32 header;
+ if (rdev->wb.enabled) {
+ u64 next_rptr_gaddr;
+ /* next rptr is wptr + 5 dw for mem_write and 4 for indirect_buffer
+ * and 8 dword for coherency and flush */
+ u32 next_rptr = ring->wptr + 5 + 4 + 8;
+
+ next_rptr_gaddr = rdev->wb.gpu_addr + RADEON_WB_RING0_NEXT_RPTR;
+ next_rptr_gaddr += ring->id * 4;
+ WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
+ radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
+ radeon_ring_write(ring, next_rptr_gaddr & 0xfffffffc);
+ radeon_ring_write(ring, upper_32_bits(next_rptr_gaddr) & 0xff | (1 << 18));
+ radeon_ring_write(ring, next_rptr);
+ radeon_ring_write(ring, 0);
+ }
+
if (ib->is_const_ib)
header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
else
--
1.7.10.4
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next prev parent reply other threads:[~2012-07-09 15:36 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-07-09 10:41 [RFC] drm/radeon: restoring ring commands in case of a lockup Christian König
2012-07-09 10:41 ` [PATCH 01/16] drm/radeon: add error handling to fence_wait_empty_locked Christian König
2012-07-09 10:41 ` [PATCH 02/16] drm/radeon: add error handling to radeon_vm_unbind_locked Christian König
2012-07-09 10:41 ` [PATCH 03/16] drm/radeon: fix fence related segfault in CS Christian König
2012-07-09 10:41 ` [PATCH 04/16] drm/radeon: add an exclusive lock for GPU reset v2 Christian König
2012-07-09 10:41 ` [PATCH 05/16] drm/radeon: fix ring commit padding Christian König
2012-07-09 10:41 ` [PATCH 06/16] drm/radeon: fix fence value access Christian König
2012-07-09 10:41 ` [PATCH 07/16] drm/radeon: fix fence init after resume Christian König
2012-07-09 10:41 ` [PATCH 08/16] drm/radeon: remove FIXME comment from chipset suspend Christian König
2012-07-09 10:41 ` [PATCH 09/16] drm/radeon: make cp init on cayman more robust Christian König
2012-07-09 14:43 ` Jerome Glisse
2012-07-09 15:11 ` Christian König
2012-07-09 10:41 ` [PATCH 10/16] drm/radeon: remove ip_pool start/suspend Christian König
2012-07-09 10:41 ` [PATCH 11/16] drm/radeon: remove r600_blit_suspend Christian König
2012-07-09 10:41 ` [PATCH 12/16] drm/radeon: remove vm_manager start/suspend Christian König
2012-07-09 10:42 ` [PATCH 13/16] drm/radeon: move radeon_ib_ring_tests out of chipset code Christian König
2012-07-09 15:06 ` Michel Dänzer
2012-07-09 15:22 ` Christian König
2012-07-09 15:36 ` Michel Dänzer
2012-07-09 10:42 ` [PATCH 14/16] drm/radeon: make align a ring_init parameter Christian König
2012-07-09 10:42 ` [PATCH 15/16] drm/radeon: implement ring commit tracking Christian König
2012-07-09 15:36 ` Jerome Glisse [this message]
2012-07-09 15:48 ` Christian König
2012-07-09 16:12 ` Jerome Glisse
2012-07-09 10:42 ` [PATCH 16/16] drm/radeon: implement ring saving on reset Christian König
2012-07-09 15:06 ` Michel Dänzer
2012-07-09 15:24 ` Christian König
2012-07-09 15:59 ` [RFC] drm/radeon: restoring ring commands in case of a lockup Michel Dänzer
2012-07-09 16:10 ` Jerome Glisse
2012-07-10 12:54 ` Christian König
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