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From: Greentime Hu <greentime.hu@sifive.com>
To: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	hes@sifive.com, Erik Danie <erik.danie@sifive.com>,
	Zong Li <zong.li@sifive.com>, Bjorn Helgaas <bhelgaas@google.com>,
	robh+dt@kernel.org, Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Michael Turquette <mturquette@baylibre.com>,
	sboyd@kernel.org, lorenzo.pieralisi@arm.com,
	alex.dewar90@gmail.com, khilman@baylibre.com,
	hayashi.kunihiko@socionext.com, vidyas@nvidia.com,
	jh80.chung@samsung.com, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org,
	linux-riscv <linux-riscv@lists.infradead.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	linux-clk@vger.kernel.org
Subject: Re: [RFC PATCH 2/6] clk: sifive: Use reset-simple in prci driver for PCIe driver
Date: Tue, 9 Mar 2021 15:23:14 +0800	[thread overview]
Message-ID: <CAHCEehK3P7jXq-v_xVm-0+BQsugG21VgjU0teyuUgANyR5ErKA@mail.gmail.com> (raw)
In-Reply-To: <81c45bf40b397b57343f159baae896528fa32d89.camel@pengutronix.de>

Philipp Zabel <p.zabel@pengutronix.de> 於 2021年3月4日 週四 下午7:58寫道:
>
> On Tue, 2021-03-02 at 18:59 +0800, Greentime Hu wrote:
> > We use reset-simple in this patch so that pcie driver can use
> > devm_reset_control_get() to get this reset data structure and use
> > reset_control_deassert() to deassert pcie_power_up_rst_n.
> >
> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> > ---
> >  drivers/clk/sifive/Kconfig       |  2 ++
> >  drivers/clk/sifive/sifive-prci.c | 14 ++++++++++++++
> >  drivers/clk/sifive/sifive-prci.h |  4 ++++
> >  drivers/reset/Kconfig            |  3 ++-
> >  4 files changed, 22 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig
> > index 1c14eb20c066..9132c3c4aa86 100644
> > --- a/drivers/clk/sifive/Kconfig
> > +++ b/drivers/clk/sifive/Kconfig
> > @@ -10,6 +10,8 @@ if CLK_SIFIVE
> >
> >  config CLK_SIFIVE_PRCI
> >       bool "PRCI driver for SiFive SoCs"
> > +     select RESET_CONTROLLER
> > +     select RESET_SIMPLE
> >       select CLK_ANALOGBITS_WRPLL_CLN28HPC
> >       help
> >         Supports the Power Reset Clock interface (PRCI) IP block found in
> > diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c
> > index baf7313dac92..925affc6de55 100644
> > --- a/drivers/clk/sifive/sifive-prci.c
> > +++ b/drivers/clk/sifive/sifive-prci.c
> > @@ -583,7 +583,21 @@ static int sifive_prci_probe(struct platform_device *pdev)
> >       if (IS_ERR(pd->va))
> >               return PTR_ERR(pd->va);
> >
> > +     pd->reset.rcdev.owner = THIS_MODULE;
> > +     pd->reset.rcdev.nr_resets = PRCI_RST_NR;
> > +     pd->reset.rcdev.ops = &reset_simple_ops;
> > +     pd->reset.rcdev.of_node = pdev->dev.of_node;
> > +     pd->reset.active_low = true;
> > +     pd->reset.membase = pd->va + PRCI_DEVICESRESETREG_OFFSET;
> > +     spin_lock_init(&pd->reset.lock);
> > +
> > +     r = devm_reset_controller_register(&pdev->dev, &pd->reset.rcdev);
> > +     if (r) {
> > +             dev_err(dev, "could not register reset controller: %d\n", r);
> > +             return r;
> > +     }
> >       r = __prci_register_clocks(dev, pd, desc);
> > +
>
> Accidental whitespace?
>
> Otherwise,
>
> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>

Thank you, Philipp.
Yes, it is an accidental whitespace. I'll remove it in my next version patch.

WARNING: multiple messages have this Message-ID (diff)
From: Greentime Hu <greentime.hu@sifive.com>
To: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	hes@sifive.com,  Erik Danie <erik.danie@sifive.com>,
	Zong Li <zong.li@sifive.com>,
	 Bjorn Helgaas <bhelgaas@google.com>,
	robh+dt@kernel.org,  Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	 Michael Turquette <mturquette@baylibre.com>,
	sboyd@kernel.org, lorenzo.pieralisi@arm.com,
	 alex.dewar90@gmail.com, khilman@baylibre.com,
	hayashi.kunihiko@socionext.com,  vidyas@nvidia.com,
	jh80.chung@samsung.com, linux-pci@vger.kernel.org,
	 devicetree@vger.kernel.org,
	linux-riscv <linux-riscv@lists.infradead.org>,
	 Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	linux-clk@vger.kernel.org
Subject: Re: [RFC PATCH 2/6] clk: sifive: Use reset-simple in prci driver for PCIe driver
Date: Tue, 9 Mar 2021 15:23:14 +0800	[thread overview]
Message-ID: <CAHCEehK3P7jXq-v_xVm-0+BQsugG21VgjU0teyuUgANyR5ErKA@mail.gmail.com> (raw)
In-Reply-To: <81c45bf40b397b57343f159baae896528fa32d89.camel@pengutronix.de>

Philipp Zabel <p.zabel@pengutronix.de> 於 2021年3月4日 週四 下午7:58寫道:
>
> On Tue, 2021-03-02 at 18:59 +0800, Greentime Hu wrote:
> > We use reset-simple in this patch so that pcie driver can use
> > devm_reset_control_get() to get this reset data structure and use
> > reset_control_deassert() to deassert pcie_power_up_rst_n.
> >
> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> > ---
> >  drivers/clk/sifive/Kconfig       |  2 ++
> >  drivers/clk/sifive/sifive-prci.c | 14 ++++++++++++++
> >  drivers/clk/sifive/sifive-prci.h |  4 ++++
> >  drivers/reset/Kconfig            |  3 ++-
> >  4 files changed, 22 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig
> > index 1c14eb20c066..9132c3c4aa86 100644
> > --- a/drivers/clk/sifive/Kconfig
> > +++ b/drivers/clk/sifive/Kconfig
> > @@ -10,6 +10,8 @@ if CLK_SIFIVE
> >
> >  config CLK_SIFIVE_PRCI
> >       bool "PRCI driver for SiFive SoCs"
> > +     select RESET_CONTROLLER
> > +     select RESET_SIMPLE
> >       select CLK_ANALOGBITS_WRPLL_CLN28HPC
> >       help
> >         Supports the Power Reset Clock interface (PRCI) IP block found in
> > diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c
> > index baf7313dac92..925affc6de55 100644
> > --- a/drivers/clk/sifive/sifive-prci.c
> > +++ b/drivers/clk/sifive/sifive-prci.c
> > @@ -583,7 +583,21 @@ static int sifive_prci_probe(struct platform_device *pdev)
> >       if (IS_ERR(pd->va))
> >               return PTR_ERR(pd->va);
> >
> > +     pd->reset.rcdev.owner = THIS_MODULE;
> > +     pd->reset.rcdev.nr_resets = PRCI_RST_NR;
> > +     pd->reset.rcdev.ops = &reset_simple_ops;
> > +     pd->reset.rcdev.of_node = pdev->dev.of_node;
> > +     pd->reset.active_low = true;
> > +     pd->reset.membase = pd->va + PRCI_DEVICESRESETREG_OFFSET;
> > +     spin_lock_init(&pd->reset.lock);
> > +
> > +     r = devm_reset_controller_register(&pdev->dev, &pd->reset.rcdev);
> > +     if (r) {
> > +             dev_err(dev, "could not register reset controller: %d\n", r);
> > +             return r;
> > +     }
> >       r = __prci_register_clocks(dev, pd, desc);
> > +
>
> Accidental whitespace?
>
> Otherwise,
>
> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>

Thank you, Philipp.
Yes, it is an accidental whitespace. I'll remove it in my next version patch.

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  reply	other threads:[~2021-03-09  7:24 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-02 10:59 [RFC PATCH 0/6] Add SiFive FU740 PCIe host controller driver support Greentime Hu
2021-03-02 10:59 ` Greentime Hu
2021-03-02 10:59 ` [RFC PATCH 1/6] clk: sifive: Add pcie_aux clock in prci driver for PCIe driver Greentime Hu
2021-03-02 10:59   ` Greentime Hu
2021-03-02 10:59 ` [RFC PATCH 2/6] clk: sifive: Use reset-simple " Greentime Hu
2021-03-02 10:59   ` Greentime Hu
2021-03-04 11:58   ` Philipp Zabel
2021-03-04 11:58     ` Philipp Zabel
2021-03-09  7:23     ` Greentime Hu [this message]
2021-03-09  7:23       ` Greentime Hu
2021-03-02 10:59 ` [RFC PATCH 3/6] MAINTAINERS: Add maintainers for SiFive FU740 " Greentime Hu
2021-03-02 10:59   ` Greentime Hu
2021-03-02 10:59 ` [RFC PATCH 4/6] dt-bindings: PCI: Add SiFive FU740 PCIe host controller Greentime Hu
2021-03-02 10:59   ` Greentime Hu
2021-03-03 23:14   ` Rob Herring
2021-03-03 23:14     ` Rob Herring
2021-03-02 10:59 ` [RFC PATCH 5/6] PCI: designware: Add SiFive FU740 PCIe host controller driver Greentime Hu
2021-03-02 10:59   ` Greentime Hu
2021-03-03 23:30   ` Rob Herring
2021-03-03 23:30     ` Rob Herring
2021-03-04 12:00   ` Philipp Zabel
2021-03-04 12:00     ` Philipp Zabel
2021-03-04 15:45   ` Bjorn Helgaas
2021-03-04 15:45     ` Bjorn Helgaas
2021-03-02 10:59 ` [RFC PATCH 6/6] riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC Greentime Hu
2021-03-02 10:59   ` Greentime Hu

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