Re: [PATCH v3 0/2] PCI: xilinx-nwl: Add clock handling

From: Michal Simek <monstr@monstr.eu>
To: LKML <linux-kernel@vger.kernel.org>,
	"Michal Simek" <monstr@monstr.eu>, git <git@xilinx.com>,
	"Bharat Kumar Gogada" <bharat.kumar.gogada@xilinx.com>,
	"Krzysztof Wilczyński" <kw@linux.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Marc Zyngier <maz@kernel.org>,
	Ravi Kiran Gummaluri <rgummal@xilinx.com>,
	Rob Herring <robh+dt@kernel.org>, Rob Herring <robh@kernel.org>,
	DTML <devicetree@vger.kernel.org>,
	linux-arm <linux-arm-kernel@lists.infradead.org>,
	linux-pci@vger.kernel.org
Subject: Re: [PATCH v3 0/2] PCI: xilinx-nwl: Add clock handling
Date: Fri, 6 Aug 2021 12:28:16 +0200	[thread overview]
Message-ID: <CAHTX3dL5qTaB+YFPXiDYQAcDD_L9mYu_zAY=zV_2kXMsOR=YAA@mail.gmail.com> (raw)
In-Reply-To: <cover.1624618100.git.michal.simek@xilinx.com>

Hi Bjorn and Krzysztof,

pá 25. 6. 2021 v 12:48 odesílatel Michal Simek <michal.simek@xilinx.com> napsal:
>
> Hi,
>
> this small series add support for enabling PCIe reference clock by driver.
>
> Thanks,
> Michal
>
> Changes in v3:
> - use PCIe instead of pcie
> - add stable cc
> - update commit message - reported by Krzysztof
>
> Changes in v2:
> - new patch in this series because I found that it has never been sent
> - Update commit message - reported by Krzysztof
> - Check return value from clk_prepare_enable() - reported by Krzysztof
>
> Hyun Kwon (1):
>   PCI: xilinx-nwl: Enable the clock through CCF
>
> Michal Simek (1):
>   dt-bindings: pci: xilinx-nwl: Document optional clock property
>
>  .../devicetree/bindings/pci/xilinx-nwl-pcie.txt      |  1 +
>  drivers/pci/controller/pcie-xilinx-nwl.c             | 12 ++++++++++++
>  2 files changed, 13 insertions(+)
>
> --
> 2.32.0
>

Can you please take a look at this series?

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
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