From: Catalin Marinas <catalin.marinas@arm.com>
To: Russell King - ARM Linux <linux@arm.linux.org.uk>
Cc: linux-omap@vger.kernel.org,
Santosh Shilimkar <santosh.shilimkar@ti.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 03/11] ARM: pm: some ARMv7 requires a dsb in resume to ensure correctness
Date: Wed, 7 Sep 2011 16:41:32 +0100 [thread overview]
Message-ID: <CAHkRjk65O3wJLazxZeOOQrDuM-XkZXo4fcOuVZf4Jzq9OP3p3g@mail.gmail.com> (raw)
In-Reply-To: <E1Qz6hr-00078J-2k@rmk-PC.arm.linux.org.uk>
On 1 September 2011 13:49, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> Add a dsb after the isb to ensure that the previous writes to the
> CP15 registers take effect before we enable the MMU.
>
> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> ---
> arch/arm/mm/proc-v7.S | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> index dec72ee..a773f4e 100644
> --- a/arch/arm/mm/proc-v7.S
> +++ b/arch/arm/mm/proc-v7.S
> @@ -255,6 +255,7 @@ ENTRY(cpu_v7_do_resume)
> mcr p15, 0, r4, c10, c2, 0 @ write PRRR
> mcr p15, 0, r5, c10, c2, 1 @ write NMRR
> isb
> + dsb
Isn't an ISB enough here? We usually have the DSB for some background
operations like cache maintenance.
--
Catalin
WARNING: multiple messages have this Message-ID (diff)
From: catalin.marinas@arm.com (Catalin Marinas)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 03/11] ARM: pm: some ARMv7 requires a dsb in resume to ensure correctness
Date: Wed, 7 Sep 2011 16:41:32 +0100 [thread overview]
Message-ID: <CAHkRjk65O3wJLazxZeOOQrDuM-XkZXo4fcOuVZf4Jzq9OP3p3g@mail.gmail.com> (raw)
In-Reply-To: <E1Qz6hr-00078J-2k@rmk-PC.arm.linux.org.uk>
On 1 September 2011 13:49, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> Add a dsb after the isb to ensure that the previous writes to the
> CP15 registers take effect before we enable the MMU.
>
> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> ---
> ?arch/arm/mm/proc-v7.S | ? ?1 +
> ?1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> index dec72ee..a773f4e 100644
> --- a/arch/arm/mm/proc-v7.S
> +++ b/arch/arm/mm/proc-v7.S
> @@ -255,6 +255,7 @@ ENTRY(cpu_v7_do_resume)
> ? ? ? ?mcr ? ? p15, 0, r4, c10, c2, 0 ?@ write PRRR
> ? ? ? ?mcr ? ? p15, 0, r5, c10, c2, 1 ?@ write NMRR
> ? ? ? ?isb
> + ? ? ? dsb
Isn't an ISB enough here? We usually have the DSB for some background
operations like cache maintenance.
--
Catalin
next prev parent reply other threads:[~2011-09-07 15:41 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-09-01 12:47 [PATCH 00/11] Add L2 cache cleaning to generic CPU suspend Russell King - ARM Linux
2011-09-01 12:47 ` Russell King - ARM Linux
2011-09-01 12:48 ` [PATCH 01/11] ARM: pm: CPU specific code should not overwrite r1 (v:p offset) Russell King - ARM Linux
2011-09-01 12:48 ` Russell King - ARM Linux
2011-09-01 12:48 ` [PATCH 02/11] ARM: pm: arm920/926: fix number of registers saved Russell King - ARM Linux
2011-09-01 12:48 ` Russell King - ARM Linux
2011-09-01 12:49 ` [PATCH 03/11] ARM: pm: some ARMv7 requires a dsb in resume to ensure correctness Russell King - ARM Linux
2011-09-01 12:49 ` Russell King - ARM Linux
2011-09-07 15:41 ` Catalin Marinas [this message]
2011-09-07 15:41 ` Catalin Marinas
2011-09-07 16:19 ` Russell King - ARM Linux
2011-09-07 16:19 ` Russell King - ARM Linux
2011-09-07 16:26 ` Catalin Marinas
2011-09-07 16:26 ` Catalin Marinas
2011-09-07 16:54 ` Catalin Marinas
2011-09-07 16:54 ` Catalin Marinas
2011-09-01 12:49 ` [PATCH 04/11] ARM: pm: avoid writing the auxillary control register for ARMv7 Russell King - ARM Linux
2011-09-01 12:49 ` Russell King - ARM Linux
2011-09-01 12:49 ` [PATCH 05/11] ARM: pm: force non-zero return value from __cpu_suspend when aborting Russell King - ARM Linux
2011-09-01 12:49 ` Russell King - ARM Linux
2011-09-01 12:50 ` [PATCH 06/11] ARM: pm: preallocate a page table for suspend/resume Russell King - ARM Linux
2011-09-01 12:50 ` Russell King - ARM Linux
2011-09-01 12:50 ` [PATCH 07/11] ARM: pm: only use preallocated page table during resume Russell King - ARM Linux
2011-09-01 12:50 ` Russell King - ARM Linux
2011-09-01 12:50 ` [PATCH 08/11] ARM: pm: no need to save/restore context ID register Russell King - ARM Linux
2011-09-01 12:50 ` Russell King - ARM Linux
2011-09-03 16:33 ` Santosh
2011-09-03 16:33 ` Santosh
2011-09-04 10:08 ` Russell King - ARM Linux
2011-09-04 10:08 ` Russell King - ARM Linux
2011-09-01 12:51 ` [PATCH 09/11] ARM: pm: get rid of cpu_resume_turn_mmu_on Russell King - ARM Linux
2011-09-01 12:51 ` Russell King - ARM Linux
2011-09-01 12:51 ` [PATCH 10/11] ARM: pm: convert some assembly to C Russell King - ARM Linux
2011-09-01 12:51 ` Russell King - ARM Linux
2011-09-07 15:48 ` Lorenzo Pieralisi
2011-09-07 15:48 ` Lorenzo Pieralisi
2011-09-19 16:32 ` Russell King - ARM Linux
2011-09-19 16:32 ` Russell King - ARM Linux
2011-09-01 12:51 ` [PATCH 11/11] ARM: pm: add L2 cache cleaning for suspend Russell King - ARM Linux
2011-09-01 12:51 ` Russell King - ARM Linux
2011-09-01 15:33 ` [PATCH 00/11] Add L2 cache cleaning to generic CPU suspend Shawn Guo
2011-09-01 15:33 ` Shawn Guo
2011-09-01 15:34 ` Russell King - ARM Linux
2011-09-01 15:34 ` Russell King - ARM Linux
2011-09-01 15:57 ` Shawn Guo
2011-09-01 15:57 ` Shawn Guo
2011-09-10 16:10 ` Shawn Guo
2011-09-10 16:10 ` Shawn Guo
2011-09-19 16:22 ` Russell King - ARM Linux
2011-09-19 16:22 ` Russell King - ARM Linux
2011-09-20 3:24 ` Shawn Guo
2011-09-20 3:24 ` Shawn Guo
2011-09-03 16:36 ` Santosh
2011-09-03 16:36 ` Santosh
2011-09-04 10:12 ` Russell King - ARM Linux
2011-09-04 10:12 ` Russell King - ARM Linux
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