From: Guo Ren <guoren@kernel.org> To: Samuel Holland <samuel@sholland.org> Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, Prabhakar <prabhakar.csengg@gmail.com>, Marc Zyngier <maz@kernel.org>, Sagar Kadam <sagar.kadam@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven <geert+renesas@glider.be>, Thomas Gleixner <tglx@linutronix.de>, Biju Das <biju.das.jz@bp.renesas.com>, Albert Ou <aou@eecs.berkeley.edu>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Rob Herring <robh+dt@kernel.org>, devicetree <devicetree@vger.kernel.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, linux-riscv <linux-riscv@lists.infradead.org> Subject: Re: [PATCH v1 1/3] dt-bindings: interrupt-controller: Require trigger type for T-HEAD PLIC Date: Mon, 27 Jun 2022 15:40:25 +0800 [thread overview] Message-ID: <CAJF2gTSq1NsBWRCg+kpTbJRwSeE30P9NVB5di6vzi7m2CFRzHw@mail.gmail.com> (raw) In-Reply-To: <20220627051257.38543-2-samuel@sholland.org> On Mon, Jun 27, 2022 at 1:13 PM Samuel Holland <samuel@sholland.org> wrote: > > The RISC-V PLIC specification unfortunately allows PLIC implementations > to ignore edges seen while an edge-triggered interrupt is being handled: > > Depending on the design of the device and the interrupt handler, > in between sending an interrupt request and receiving notice of its > handler’s completion, the gateway might either ignore additional > matching edges or increment a counter of pending interrupts. > > For PLICs with that misfeature, software needs to know the trigger type > of each interrupt. This allows it to work around the issue by completing > edge-triggered interrupts before handling them. Such a workaround is > required to avoid missing any edges. > > The T-HEAD C9xx PLIC is an example of a PLIC with this behavior. Actually, C9xx support pulse signals which configed by pad_plic_int_cfg_x for SoC vendor: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/plic/rtl/plic_int_kid.v 104: assign int_new_pending = pad_plic_int_cfg_x ? int_pulse 105: : level_int_pending; They could put pad_plic_int_cfg_x into the SoC software config registers region or bind them to constant values. > > Signed-off-by: Samuel Holland <samuel@sholland.org> > --- > > .../sifive,plic-1.0.0.yaml | 31 ++++++++++++++++--- > 1 file changed, 27 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > index 27092c6a86c4..3c589cbca851 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > @@ -26,9 +26,13 @@ description: > with priority below this threshold will not cause the PLIC to raise its > interrupt line leading to the context. > > - While the PLIC supports both edge-triggered and level-triggered interrupts, > - interrupt handlers are oblivious to this distinction and therefore it is not > - specified in the PLIC device-tree binding. > + The PLIC supports both edge-triggered and level-triggered interrupts. For > + edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges > + seen while an interrupt handler is active; the PLIC may either queue them or > + ignore them. In the first case, handlers are oblivious to the trigger type, so > + it is not included in the interrupt specifier. In the second case, software > + needs to know the trigger type, so it can reorder the interrupt flow to avoid > + missing interrupts. > > While the RISC-V ISA doesn't specify a memory layout for the PLIC, the > "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that > @@ -65,7 +69,8 @@ properties: > const: 0 > > '#interrupt-cells': > - const: 1 > + minimum: 1 > + maximum: 2 > > interrupt-controller: true > > @@ -91,6 +96,24 @@ required: > - interrupts-extended > - riscv,ndev > > +allOf: > + - if: > + properties: > + compatible: > + contains: > + enum: > + - thead,c900-plic > + > + then: > + properties: > + '#interrupt-cells': > + const: 2 > + > + else: > + properties: > + '#interrupt-cells': > + const: 1 > + > additionalProperties: false > > examples: > -- > 2.35.1 > -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/
WARNING: multiple messages have this Message-ID (diff)
From: Guo Ren <guoren@kernel.org> To: Samuel Holland <samuel@sholland.org> Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, Prabhakar <prabhakar.csengg@gmail.com>, Marc Zyngier <maz@kernel.org>, Sagar Kadam <sagar.kadam@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven <geert+renesas@glider.be>, Thomas Gleixner <tglx@linutronix.de>, Biju Das <biju.das.jz@bp.renesas.com>, Albert Ou <aou@eecs.berkeley.edu>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Rob Herring <robh+dt@kernel.org>, devicetree <devicetree@vger.kernel.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, linux-riscv <linux-riscv@lists.infradead.org> Subject: Re: [PATCH v1 1/3] dt-bindings: interrupt-controller: Require trigger type for T-HEAD PLIC Date: Mon, 27 Jun 2022 15:40:25 +0800 [thread overview] Message-ID: <CAJF2gTSq1NsBWRCg+kpTbJRwSeE30P9NVB5di6vzi7m2CFRzHw@mail.gmail.com> (raw) In-Reply-To: <20220627051257.38543-2-samuel@sholland.org> On Mon, Jun 27, 2022 at 1:13 PM Samuel Holland <samuel@sholland.org> wrote: > > The RISC-V PLIC specification unfortunately allows PLIC implementations > to ignore edges seen while an edge-triggered interrupt is being handled: > > Depending on the design of the device and the interrupt handler, > in between sending an interrupt request and receiving notice of its > handler’s completion, the gateway might either ignore additional > matching edges or increment a counter of pending interrupts. > > For PLICs with that misfeature, software needs to know the trigger type > of each interrupt. This allows it to work around the issue by completing > edge-triggered interrupts before handling them. Such a workaround is > required to avoid missing any edges. > > The T-HEAD C9xx PLIC is an example of a PLIC with this behavior. Actually, C9xx support pulse signals which configed by pad_plic_int_cfg_x for SoC vendor: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/plic/rtl/plic_int_kid.v 104: assign int_new_pending = pad_plic_int_cfg_x ? int_pulse 105: : level_int_pending; They could put pad_plic_int_cfg_x into the SoC software config registers region or bind them to constant values. > > Signed-off-by: Samuel Holland <samuel@sholland.org> > --- > > .../sifive,plic-1.0.0.yaml | 31 ++++++++++++++++--- > 1 file changed, 27 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > index 27092c6a86c4..3c589cbca851 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > @@ -26,9 +26,13 @@ description: > with priority below this threshold will not cause the PLIC to raise its > interrupt line leading to the context. > > - While the PLIC supports both edge-triggered and level-triggered interrupts, > - interrupt handlers are oblivious to this distinction and therefore it is not > - specified in the PLIC device-tree binding. > + The PLIC supports both edge-triggered and level-triggered interrupts. For > + edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges > + seen while an interrupt handler is active; the PLIC may either queue them or > + ignore them. In the first case, handlers are oblivious to the trigger type, so > + it is not included in the interrupt specifier. In the second case, software > + needs to know the trigger type, so it can reorder the interrupt flow to avoid > + missing interrupts. > > While the RISC-V ISA doesn't specify a memory layout for the PLIC, the > "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that > @@ -65,7 +69,8 @@ properties: > const: 0 > > '#interrupt-cells': > - const: 1 > + minimum: 1 > + maximum: 2 > > interrupt-controller: true > > @@ -91,6 +96,24 @@ required: > - interrupts-extended > - riscv,ndev > > +allOf: > + - if: > + properties: > + compatible: > + contains: > + enum: > + - thead,c900-plic > + > + then: > + properties: > + '#interrupt-cells': > + const: 2 > + > + else: > + properties: > + '#interrupt-cells': > + const: 1 > + > additionalProperties: false > > examples: > -- > 2.35.1 > -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-06-27 7:40 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-06-27 5:12 [PATCH v1 0/3] irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling Samuel Holland 2022-06-27 5:12 ` Samuel Holland 2022-06-27 5:12 ` [PATCH v1 1/3] dt-bindings: interrupt-controller: Require trigger type for T-HEAD PLIC Samuel Holland 2022-06-27 5:12 ` Samuel Holland 2022-06-27 7:40 ` Guo Ren [this message] 2022-06-27 7:40 ` Guo Ren 2022-06-27 14:14 ` Samuel Holland 2022-06-27 14:14 ` Samuel Holland 2022-06-28 3:04 ` Guo Ren 2022-06-28 3:04 ` Guo Ren 2022-06-28 7:55 ` Guo Ren 2022-06-28 7:55 ` Guo Ren 2022-06-27 5:12 ` [PATCH v1 2/3] irqchip/sifive-plic: Name the chip more generically Samuel Holland 2022-06-27 5:12 ` Samuel Holland 2022-06-27 6:50 ` Guo Ren 2022-06-27 6:50 ` Guo Ren 2022-06-27 7:11 ` Marc Zyngier 2022-06-27 7:11 ` Marc Zyngier 2022-06-27 13:40 ` Samuel Holland 2022-06-27 13:40 ` Samuel Holland 2022-06-27 5:12 ` [PATCH v1 3/3] irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling Samuel Holland 2022-06-27 5:12 ` Samuel Holland 2022-06-27 7:27 ` Marc Zyngier 2022-06-27 7:27 ` Marc Zyngier 2022-06-27 13:58 ` Samuel Holland 2022-06-27 13:58 ` Samuel Holland
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