From: Arnd Bergmann <arnd@kernel.org>
To: Zhen Lei <thunder.leizhen@huawei.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Will Deacon <will.deacon@arm.com>,
Haojian Zhuang <haojian.zhuang@gmail.com>,
Arnd Bergmann <arnd@arndb.de>, Rob Herring <robh+dt@kernel.org>,
Wei Xu <xuwei5@hisilicon.com>,
devicetree <devicetree@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 2/3] dt-bindings: arm: hisilicon: Add binding for L3 cache controller
Date: Tue, 12 Jan 2021 09:46:03 +0100 [thread overview]
Message-ID: <CAK8P3a0VcLtOrvXKEd2dDuP8HhKzU+uB0U6OiJXtefQQYjTheg@mail.gmail.com> (raw)
In-Reply-To: <20210112015602.497-3-thunder.leizhen@huawei.com>
On Tue, Jan 12, 2021 at 2:56 AM Zhen Lei <thunder.leizhen@huawei.com> wrote:
> +---
> +$id: http://devicetree.org/schemas/arm/hisilicon/l3cache.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Hisilicon L3 cache controller
> +
> +maintainers:
> + - Wei Xu <xuwei5@hisilicon.com>
> +
> +description: |
> + The Hisilicon L3 outer cache controller supports a maximum of 36-bit physical
> + addresses. The data cached in the L3 outer cache can be operated based on the
> + physical address range or the entire cache.
> +
> +properties:
> + compatible:
> + items:
> + - const: hisilicon,l3cache
> +
The compatible string needs to be a little more specific, I'm sure
you cannot guarantee that this is the only L3 cache controller ever
designed in the past or future by HiSilicon.
Normally when you have an IP block that is itself unnamed but that is specific
to one or a few SoCs but that has no na, the convention is to include the name
of the first SoC that contained it.
Can you share which products actually use this L3 cache controller?
On a related note, what does the memory map look like on this chip?
Do you support more than 4GB of total installed memory? If you
do, this becomes a problem in the future as highmem support
winds down. In fact anything more than 1GB on a 32-bit system
requires more work on the kernel to be completed before we remove
highmem, and will incur a slowdown. If the total is under 4GB but the
memory is not in a contiguous physical address range. See my
Linaro connect presentation[1] for further information on the topic.
Arnd
[1] https://connect.linaro.org/resources/lvc20/lvc20-106/
WARNING: multiple messages have this Message-ID (diff)
From: Arnd Bergmann <arnd@kernel.org>
To: Zhen Lei <thunder.leizhen@huawei.com>
Cc: devicetree <devicetree@vger.kernel.org>,
Arnd Bergmann <arnd@arndb.de>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Will Deacon <will.deacon@arm.com>,
linux-kernel <linux-kernel@vger.kernel.org>,
Haojian Zhuang <haojian.zhuang@gmail.com>,
Rob Herring <robh+dt@kernel.org>, Wei Xu <xuwei5@hisilicon.com>,
Russell King <rmk+kernel@arm.linux.org.uk>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v3 2/3] dt-bindings: arm: hisilicon: Add binding for L3 cache controller
Date: Tue, 12 Jan 2021 09:46:03 +0100 [thread overview]
Message-ID: <CAK8P3a0VcLtOrvXKEd2dDuP8HhKzU+uB0U6OiJXtefQQYjTheg@mail.gmail.com> (raw)
In-Reply-To: <20210112015602.497-3-thunder.leizhen@huawei.com>
On Tue, Jan 12, 2021 at 2:56 AM Zhen Lei <thunder.leizhen@huawei.com> wrote:
> +---
> +$id: http://devicetree.org/schemas/arm/hisilicon/l3cache.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Hisilicon L3 cache controller
> +
> +maintainers:
> + - Wei Xu <xuwei5@hisilicon.com>
> +
> +description: |
> + The Hisilicon L3 outer cache controller supports a maximum of 36-bit physical
> + addresses. The data cached in the L3 outer cache can be operated based on the
> + physical address range or the entire cache.
> +
> +properties:
> + compatible:
> + items:
> + - const: hisilicon,l3cache
> +
The compatible string needs to be a little more specific, I'm sure
you cannot guarantee that this is the only L3 cache controller ever
designed in the past or future by HiSilicon.
Normally when you have an IP block that is itself unnamed but that is specific
to one or a few SoCs but that has no na, the convention is to include the name
of the first SoC that contained it.
Can you share which products actually use this L3 cache controller?
On a related note, what does the memory map look like on this chip?
Do you support more than 4GB of total installed memory? If you
do, this becomes a problem in the future as highmem support
winds down. In fact anything more than 1GB on a 32-bit system
requires more work on the kernel to be completed before we remove
highmem, and will incur a slowdown. If the total is under 4GB but the
memory is not in a contiguous physical address range. See my
Linaro connect presentation[1] for further information on the topic.
Arnd
[1] https://connect.linaro.org/resources/lvc20/lvc20-106/
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next prev parent reply other threads:[~2021-01-12 8:47 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-12 1:55 [PATCH v3 0/3] Add Hisilicon L3 cache controller support Zhen Lei
2021-01-12 1:55 ` Zhen Lei
2021-01-12 1:56 ` [PATCH v3 1/3] ARM: LPAE: Use phys_addr_t instead of unsigned long in outercache hooks Zhen Lei
2021-01-12 1:56 ` Zhen Lei
2021-01-12 1:56 ` [PATCH v3 2/3] dt-bindings: arm: hisilicon: Add binding for L3 cache controller Zhen Lei
2021-01-12 1:56 ` Zhen Lei
2021-01-12 8:46 ` Arnd Bergmann [this message]
2021-01-12 8:46 ` Arnd Bergmann
2021-01-12 12:35 ` Leizhen (ThunderTown)
2021-01-12 12:35 ` Leizhen (ThunderTown)
2021-01-12 13:55 ` Arnd Bergmann
2021-01-12 13:55 ` Arnd Bergmann
2021-01-13 7:44 ` Leizhen (ThunderTown)
2021-01-13 7:44 ` Leizhen (ThunderTown)
2021-01-13 8:13 ` Leizhen (ThunderTown)
2021-01-13 8:13 ` Leizhen (ThunderTown)
2021-01-13 11:15 ` Arnd Bergmann
2021-01-13 11:15 ` Arnd Bergmann
2021-01-13 12:33 ` Leizhen (ThunderTown)
2021-01-13 12:33 ` Leizhen (ThunderTown)
2021-01-12 1:56 ` [PATCH v3 3/3] ARM: Add Hisilicon L3 cache controller support Zhen Lei
2021-01-12 1:56 ` Zhen Lei
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