Re: [PATCH v5 03/17] target/riscv: rvb: count bits set

From: Alistair Francis <alistair23@gmail.com>
To: Frank Chang <frank.chang@sifive.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Richard Henderson <richard.henderson@linaro.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Kito Cheng <kito.cheng@sifive.com>
Subject: Re: [PATCH v5 03/17] target/riscv: rvb: count bits set
Date: Tue, 27 Apr 2021 16:03:04 +1000	[thread overview]
Message-ID: <CAKmqyKNeQnxpyb-1gNWa41dmGkOSm8DeUGNwdHyZebLsicP1Xg@mail.gmail.com> (raw)
In-Reply-To: <20210421041400.22243-4-frank.chang@sifive.com>

On Wed, Apr 21, 2021 at 2:18 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn32-64.decode           |  1 +
>  target/riscv/insn32.decode              |  1 +
>  target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++
>  target/riscv/translate.c                |  6 ++++++
>  4 files changed, 20 insertions(+)
>
> diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
> index f4c42720fc7..89498a9a28a 100644
> --- a/target/riscv/insn32-64.decode
> +++ b/target/riscv/insn32-64.decode
> @@ -90,3 +90,4 @@ hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
>  # *** RV64B Standard Extension (in addition to RV32B) ***
>  clzw       0110000 00000 ..... 001 ..... 0011011 @r2
>  ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
> +cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 8fe838cf0d0..0e321da37f4 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -597,3 +597,4 @@ vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
>  # *** RV32B Standard Extension ***
>  clz        011000 000000 ..... 001 ..... 0010011 @r2
>  ctz        011000 000001 ..... 001 ..... 0010011 @r2
> +cpop       011000 000010 ..... 001 ..... 0010011 @r2
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> index 76788c2f353..dbbd94e1015 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -29,6 +29,12 @@ static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
>      return gen_unary(ctx, a, gen_ctz);
>  }
>
> +static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_unary(ctx, a, tcg_gen_ctpop_tl);
> +}
> +
>  /* RV64-only instructions */
>  #ifdef TARGET_RISCV64
>
> @@ -44,4 +50,10 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
>      return gen_unary(ctx, a, gen_ctzw);
>  }
>
> +static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_unary(ctx, a, gen_cpopw);
> +}
> +
>  #endif
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 4648c422f42..b20a58c63b4 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -551,6 +551,12 @@ static void gen_clzw(TCGv ret, TCGv arg1)
>      tcg_gen_subi_i64(ret, ret, 32);
>  }
>
> +static void gen_cpopw(TCGv ret, TCGv arg1)
> +{
> +    tcg_gen_ext32u_tl(arg1, arg1);
> +    tcg_gen_ctpop_tl(ret, arg1);
> +}
> +
>  #endif
>
>  static bool gen_arith(DisasContext *ctx, arg_r *a,
> --
> 2.17.1
>
>