From: Alistair Francis <alistair23@gmail.com>
To: Yifei Jiang <jiangyifei@huawei.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Zhanghailiang <zhang.zhanghailiang@huawei.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
"Zhangxiaofeng \(F\)" <victor.zhangxiaofeng@huawei.com>,
Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
yinyipeng <yinyipeng1@huawei.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
"Wubin \(H\)" <wu.wubin@huawei.com>,
"dengkai \(A\)" <dengkai1@huawei.com>
Subject: Re: [PATCH V3 6/6] target/riscv: Add sifive_plic vmstate
Date: Fri, 23 Oct 2020 17:02:06 -0700 [thread overview]
Message-ID: <CAKmqyKNg5__hB+tMm3z0S9EH7FG9fMLpvFmwz5BoBKZ0Ag_Ruw@mail.gmail.com> (raw)
In-Reply-To: <20201023091225.224-7-jiangyifei@huawei.com>
On Fri, Oct 23, 2020 at 2:13 AM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> Add sifive_plic vmstate for supporting sifive_plic migration.
> Current vmstate framework only supports one structure parameter
> as num field to describe variable length arrays, so introduce
> num_enables.
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/intc/sifive_plic.c | 26 +++++++++++++++++++++++++-
> hw/intc/sifive_plic.h | 1 +
> 2 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index f42fd695d8..97a1a27a9a 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -30,6 +30,7 @@
> #include "hw/intc/sifive_plic.h"
> #include "target/riscv/cpu.h"
> #include "sysemu/sysemu.h"
> +#include "migration/vmstate.h"
>
> #define RISCV_DEBUG_PLIC 0
>
> @@ -448,11 +449,12 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
> TYPE_SIFIVE_PLIC, plic->aperture_size);
> parse_hart_config(plic);
> plic->bitfield_words = (plic->num_sources + 31) >> 5;
> + plic->num_enables = plic->bitfield_words * plic->num_addrs;
> plic->source_priority = g_new0(uint32_t, plic->num_sources);
> plic->target_priority = g_new(uint32_t, plic->num_addrs);
> plic->pending = g_new0(uint32_t, plic->bitfield_words);
> plic->claimed = g_new0(uint32_t, plic->bitfield_words);
> - plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
> + plic->enable = g_new0(uint32_t, plic->num_enables);
> sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
> qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
>
> @@ -472,12 +474,34 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
> msi_nonbroken = true;
> }
>
> +static const VMStateDescription vmstate_sifive_plic = {
> + .name = "riscv_sifive_plic",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_VARRAY_UINT32(source_priority, SiFivePLICState,
> + num_sources, 0,
> + vmstate_info_uint32, uint32_t),
> + VMSTATE_VARRAY_UINT32(target_priority, SiFivePLICState,
> + num_addrs, 0,
> + vmstate_info_uint32, uint32_t),
> + VMSTATE_VARRAY_UINT32(pending, SiFivePLICState, bitfield_words, 0,
> + vmstate_info_uint32, uint32_t),
> + VMSTATE_VARRAY_UINT32(claimed, SiFivePLICState, bitfield_words, 0,
> + vmstate_info_uint32, uint32_t),
> + VMSTATE_VARRAY_UINT32(enable, SiFivePLICState, num_enables, 0,
> + vmstate_info_uint32, uint32_t),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> static void sifive_plic_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
>
> device_class_set_props(dc, sifive_plic_properties);
> dc->realize = sifive_plic_realize;
> + dc->vmsd = &vmstate_sifive_plic;
> }
>
> static const TypeInfo sifive_plic_info = {
> diff --git a/hw/intc/sifive_plic.h b/hw/intc/sifive_plic.h
> index b75b1f145d..1e451a270c 100644
> --- a/hw/intc/sifive_plic.h
> +++ b/hw/intc/sifive_plic.h
> @@ -52,6 +52,7 @@ struct SiFivePLICState {
> uint32_t num_addrs;
> uint32_t num_harts;
> uint32_t bitfield_words;
> + uint32_t num_enables;
> PLICAddr *addr_config;
> uint32_t *source_priority;
> uint32_t *target_priority;
> --
> 2.19.1
>
>
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com>
To: Yifei Jiang <jiangyifei@huawei.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Zhanghailiang <zhang.zhanghailiang@huawei.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
"Zhangxiaofeng (F)" <victor.zhangxiaofeng@huawei.com>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
yinyipeng <yinyipeng1@huawei.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
"Wubin (H)" <wu.wubin@huawei.com>,
"dengkai (A)" <dengkai1@huawei.com>
Subject: Re: [PATCH V3 6/6] target/riscv: Add sifive_plic vmstate
Date: Fri, 23 Oct 2020 17:02:06 -0700 [thread overview]
Message-ID: <CAKmqyKNg5__hB+tMm3z0S9EH7FG9fMLpvFmwz5BoBKZ0Ag_Ruw@mail.gmail.com> (raw)
In-Reply-To: <20201023091225.224-7-jiangyifei@huawei.com>
On Fri, Oct 23, 2020 at 2:13 AM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> Add sifive_plic vmstate for supporting sifive_plic migration.
> Current vmstate framework only supports one structure parameter
> as num field to describe variable length arrays, so introduce
> num_enables.
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/intc/sifive_plic.c | 26 +++++++++++++++++++++++++-
> hw/intc/sifive_plic.h | 1 +
> 2 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index f42fd695d8..97a1a27a9a 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -30,6 +30,7 @@
> #include "hw/intc/sifive_plic.h"
> #include "target/riscv/cpu.h"
> #include "sysemu/sysemu.h"
> +#include "migration/vmstate.h"
>
> #define RISCV_DEBUG_PLIC 0
>
> @@ -448,11 +449,12 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
> TYPE_SIFIVE_PLIC, plic->aperture_size);
> parse_hart_config(plic);
> plic->bitfield_words = (plic->num_sources + 31) >> 5;
> + plic->num_enables = plic->bitfield_words * plic->num_addrs;
> plic->source_priority = g_new0(uint32_t, plic->num_sources);
> plic->target_priority = g_new(uint32_t, plic->num_addrs);
> plic->pending = g_new0(uint32_t, plic->bitfield_words);
> plic->claimed = g_new0(uint32_t, plic->bitfield_words);
> - plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
> + plic->enable = g_new0(uint32_t, plic->num_enables);
> sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
> qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
>
> @@ -472,12 +474,34 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
> msi_nonbroken = true;
> }
>
> +static const VMStateDescription vmstate_sifive_plic = {
> + .name = "riscv_sifive_plic",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_VARRAY_UINT32(source_priority, SiFivePLICState,
> + num_sources, 0,
> + vmstate_info_uint32, uint32_t),
> + VMSTATE_VARRAY_UINT32(target_priority, SiFivePLICState,
> + num_addrs, 0,
> + vmstate_info_uint32, uint32_t),
> + VMSTATE_VARRAY_UINT32(pending, SiFivePLICState, bitfield_words, 0,
> + vmstate_info_uint32, uint32_t),
> + VMSTATE_VARRAY_UINT32(claimed, SiFivePLICState, bitfield_words, 0,
> + vmstate_info_uint32, uint32_t),
> + VMSTATE_VARRAY_UINT32(enable, SiFivePLICState, num_enables, 0,
> + vmstate_info_uint32, uint32_t),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> static void sifive_plic_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
>
> device_class_set_props(dc, sifive_plic_properties);
> dc->realize = sifive_plic_realize;
> + dc->vmsd = &vmstate_sifive_plic;
> }
>
> static const TypeInfo sifive_plic_info = {
> diff --git a/hw/intc/sifive_plic.h b/hw/intc/sifive_plic.h
> index b75b1f145d..1e451a270c 100644
> --- a/hw/intc/sifive_plic.h
> +++ b/hw/intc/sifive_plic.h
> @@ -52,6 +52,7 @@ struct SiFivePLICState {
> uint32_t num_addrs;
> uint32_t num_harts;
> uint32_t bitfield_words;
> + uint32_t num_enables;
> PLICAddr *addr_config;
> uint32_t *source_priority;
> uint32_t *target_priority;
> --
> 2.19.1
>
>
next prev parent reply other threads:[~2020-10-24 0:15 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-23 9:12 [PATCH V3 0/6] Support RISC-V migration Yifei Jiang
2020-10-23 9:12 ` Yifei Jiang
2020-10-23 9:12 ` [PATCH V3 1/6] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit Yifei Jiang
2020-10-23 9:12 ` Yifei Jiang
2020-10-23 9:41 ` Jiangyifei
2020-10-23 9:41 ` Jiangyifei
2020-10-23 23:50 ` Alistair Francis
2020-10-23 23:50 ` Alistair Francis
2020-10-23 9:12 ` [PATCH V3 2/6] target/riscv: Add basic vmstate description of CPU Yifei Jiang
2020-10-23 9:12 ` Yifei Jiang
2020-10-23 23:52 ` Alistair Francis
2020-10-23 23:52 ` Alistair Francis
2020-10-23 9:12 ` [PATCH V3 3/6] target/riscv: Add PMP state description Yifei Jiang
2020-10-23 9:12 ` Yifei Jiang
2020-10-23 23:59 ` Alistair Francis
2020-10-23 23:59 ` Alistair Francis
2020-10-23 9:12 ` [PATCH V3 4/6] target/riscv: Add H extension " Yifei Jiang
2020-10-23 9:12 ` Yifei Jiang
2020-10-24 0:00 ` Alistair Francis
2020-10-24 0:00 ` Alistair Francis
2020-10-23 9:12 ` [PATCH V3 5/6] target/riscv: Add V " Yifei Jiang
2020-10-23 9:12 ` Yifei Jiang
2020-10-24 0:01 ` Alistair Francis
2020-10-24 0:01 ` Alistair Francis
2020-10-23 9:12 ` [PATCH V3 6/6] target/riscv: Add sifive_plic vmstate Yifei Jiang
2020-10-23 9:12 ` Yifei Jiang
2020-10-24 0:02 ` Alistair Francis [this message]
2020-10-24 0:02 ` Alistair Francis
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