From: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> To: Jordan Crouse <jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> Cc: Nishanth Menon <nm-l0cyMroinI0@public.gmane.org>, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rajendra Nayak <rnayak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-msm <linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>, Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>, Doug Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>, dri-devel <dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>, Viresh Kumar <vireshk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>, freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org> Subject: Re: [PATCH 1/2] dt-bindings: Document qcom,adreno-gmu Date: Mon, 5 Mar 2018 13:38:59 -0600 [thread overview] Message-ID: <CAL_Jsq+OJ0jon2uFb6oMKjZuw4iPQxkxfBrbDyMN-BrNZfTRzA@mail.gmail.com> (raw) In-Reply-To: <20180302215638.6145-2-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> On Fri, Mar 2, 2018 at 3:56 PM, Jordan Crouse <jcrouse@codeaurora.org> wrote: > Document the device tree bindings for the Adreno GMU device > available on Adreno a6xx targets. > > Change-Id: I3cfd5fb35ab0045e39905ff12393006e60f1a124 Gerrit! > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > --- > .../devicetree/bindings/display/msm/gmu.txt | 54 ++++++++++++++++++++++ > .../devicetree/bindings/display/msm/gpu.txt | 10 +++- > 2 files changed, 62 insertions(+), 2 deletions(-) > create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt > > diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt b/Documentation/devicetree/bindings/display/msm/gmu.txt > new file mode 100644 > index 000000000000..f65bb49fff36 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/gmu.txt > @@ -0,0 +1,54 @@ > +Qualcomm adreno/snapdragon GMU (Graphics management unit) > + > +The GMU is a programmable power controller for the GPU. the CPU controls the > +GMU which in turn handles power controls for the GPU. > + > +Required properties: > +- compatible: > + * "qcom,adreno-gmu" Kind of generic. All the features are discoverable? > +- reg: Physical base address and length of the GMU registers. > +- reg-names: Matching names for the register regions > + * "gmu" > + * "gmu_pdc" > +- interrupts: The interrupt signals from the GMU. > +- interrupt-names: Matching names for the interrupts > + * "hfi" > + * "gmu" > +- clocks: phandles to the device clocks > +- clock-names: Matching names for the clocks > + * "gmu" > + * "cxo" > + * "axi" > + * "mnoc" > +- power-domains: should be <&clock_gpucc GPU_CX_GDSC> > +- iommus: phandle to the adreno iommu > +- operating-points-v2: phandle to the OPP operating points > + > +Example: > + > +/ { > + ... > + > + gmu: gmu@506a000 { > + compatible="qcom,adreno-gmu"; > + > + reg = <0x506a000 0x30000>, > + <0xb200000 0x300000>; > + reg-names = "gmu", "gmu_pdc"; > + > + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hfi", "gmu"; > + > + clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>, > + <&clock_gpucc GPU_CC_CXO_CLK>, > + <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, > + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>; > + clock-names = "gmu", "cxo", "axi", "memnoc"; > + > + power-domains = <&clock_gpucc GPU_CX_GDSC>; > + iommus = <&adreno_smmu 5>; > + > + i operating-points-v2 = <&gmu_opp_table>; > + }; > +}; > diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt > index 43fac0fe09bb..0e207498edd3 100644 > --- a/Documentation/devicetree/bindings/display/msm/gpu.txt > +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt > @@ -8,12 +8,18 @@ Required properties: > with the chip-id. > - reg: Physical base address and length of the controller's registers. > - interrupts: The interrupt signal from the gpu. > -- clocks: device clocks > + > +Optional properties. > +- clocks: device clocks. Required for a3xx, a4xx and a5xx targets. a6xx and > + newer with a GMU attached do not have direct clock control from the CPU and > + do not need to provide clock properties. > See ../clocks/clock-bindings.txt for details. > -- clock-names: the following clocks are required: > +- clock-names: the following clocks can be provided: > * "core" > * "iface" > * "mem_iface" > +- gmu: For a6xx and newer targets a phandle to the GMU device that will qcom,gmu > + control the power for the GPU > > Example: > > -- > 2.16.1 > > -- > To unsubscribe from this list: send the line "unsubscribe devicetree" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html _______________________________________________ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
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From: robh@kernel.org (Rob Herring) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/2] dt-bindings: Document qcom,adreno-gmu Date: Mon, 5 Mar 2018 13:38:59 -0600 [thread overview] Message-ID: <CAL_Jsq+OJ0jon2uFb6oMKjZuw4iPQxkxfBrbDyMN-BrNZfTRzA@mail.gmail.com> (raw) In-Reply-To: <20180302215638.6145-2-jcrouse@codeaurora.org> On Fri, Mar 2, 2018 at 3:56 PM, Jordan Crouse <jcrouse@codeaurora.org> wrote: > Document the device tree bindings for the Adreno GMU device > available on Adreno a6xx targets. > > Change-Id: I3cfd5fb35ab0045e39905ff12393006e60f1a124 Gerrit! > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > --- > .../devicetree/bindings/display/msm/gmu.txt | 54 ++++++++++++++++++++++ > .../devicetree/bindings/display/msm/gpu.txt | 10 +++- > 2 files changed, 62 insertions(+), 2 deletions(-) > create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt > > diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt b/Documentation/devicetree/bindings/display/msm/gmu.txt > new file mode 100644 > index 000000000000..f65bb49fff36 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/gmu.txt > @@ -0,0 +1,54 @@ > +Qualcomm adreno/snapdragon GMU (Graphics management unit) > + > +The GMU is a programmable power controller for the GPU. the CPU controls the > +GMU which in turn handles power controls for the GPU. > + > +Required properties: > +- compatible: > + * "qcom,adreno-gmu" Kind of generic. All the features are discoverable? > +- reg: Physical base address and length of the GMU registers. > +- reg-names: Matching names for the register regions > + * "gmu" > + * "gmu_pdc" > +- interrupts: The interrupt signals from the GMU. > +- interrupt-names: Matching names for the interrupts > + * "hfi" > + * "gmu" > +- clocks: phandles to the device clocks > +- clock-names: Matching names for the clocks > + * "gmu" > + * "cxo" > + * "axi" > + * "mnoc" > +- power-domains: should be <&clock_gpucc GPU_CX_GDSC> > +- iommus: phandle to the adreno iommu > +- operating-points-v2: phandle to the OPP operating points > + > +Example: > + > +/ { > + ... > + > + gmu: gmu at 506a000 { > + compatible="qcom,adreno-gmu"; > + > + reg = <0x506a000 0x30000>, > + <0xb200000 0x300000>; > + reg-names = "gmu", "gmu_pdc"; > + > + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hfi", "gmu"; > + > + clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>, > + <&clock_gpucc GPU_CC_CXO_CLK>, > + <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, > + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>; > + clock-names = "gmu", "cxo", "axi", "memnoc"; > + > + power-domains = <&clock_gpucc GPU_CX_GDSC>; > + iommus = <&adreno_smmu 5>; > + > + i operating-points-v2 = <&gmu_opp_table>; > + }; > +}; > diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt > index 43fac0fe09bb..0e207498edd3 100644 > --- a/Documentation/devicetree/bindings/display/msm/gpu.txt > +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt > @@ -8,12 +8,18 @@ Required properties: > with the chip-id. > - reg: Physical base address and length of the controller's registers. > - interrupts: The interrupt signal from the gpu. > -- clocks: device clocks > + > +Optional properties. > +- clocks: device clocks. Required for a3xx, a4xx and a5xx targets. a6xx and > + newer with a GMU attached do not have direct clock control from the CPU and > + do not need to provide clock properties. > See ../clocks/clock-bindings.txt for details. > -- clock-names: the following clocks are required: > +- clock-names: the following clocks can be provided: > * "core" > * "iface" > * "mem_iface" > +- gmu: For a6xx and newer targets a phandle to the GMU device that will qcom,gmu > + control the power for the GPU > > Example: > > -- > 2.16.1 > > -- > To unsubscribe from this list: send the line "unsubscribe devicetree" in > the body of a message to majordomo at vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html
next prev parent reply other threads:[~2018-03-05 19:38 UTC|newest] Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-03-02 21:56 [PATCH 0/2] arm64: dts: Add sdm845 GPU/GMU and SMMU Jordan Crouse 2018-03-02 21:56 ` Jordan Crouse [not found] ` <20180302215638.6145-1-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2018-03-02 21:56 ` [PATCH 1/2] dt-bindings: Document qcom,adreno-gmu Jordan Crouse 2018-03-02 21:56 ` Jordan Crouse [not found] ` <20180302215638.6145-2-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2018-03-05 19:38 ` Rob Herring [this message] 2018-03-05 19:38 ` Rob Herring 2018-03-16 18:27 ` Jordan Crouse 2018-03-16 18:27 ` Jordan Crouse 2018-03-02 21:56 ` [PATCH 2/2] arm64: dts: sdm845: Support GPU/GMU Jordan Crouse 2018-03-02 21:56 ` Jordan Crouse [not found] ` <20180302215638.6145-3-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2018-03-05 4:42 ` Viresh Kumar 2018-03-05 4:42 ` Viresh Kumar 2018-03-05 15:28 ` Jordan Crouse 2018-03-05 15:28 ` Jordan Crouse [not found] ` <20180305152818.GC15200-9PYrDHPZ2Orvke4nUoYGnHL1okKdlPRT@public.gmane.org> 2018-03-06 4:26 ` Viresh Kumar 2018-03-06 4:26 ` Viresh Kumar 2018-03-06 15:37 ` [Freedreno] " Jordan Crouse 2018-03-06 15:37 ` Jordan Crouse [not found] ` <20180306153757.GD15200-9PYrDHPZ2Orvke4nUoYGnHL1okKdlPRT@public.gmane.org> 2018-03-07 5:06 ` Viresh Kumar 2018-03-07 5:06 ` [Freedreno] " Viresh Kumar 2018-03-08 20:14 ` Jordan Crouse 2018-03-08 20:14 ` [Freedreno] " Jordan Crouse [not found] ` <20180308201438.GA10589-9PYrDHPZ2Orvke4nUoYGnHL1okKdlPRT@public.gmane.org> 2018-03-09 3:43 ` Viresh Kumar 2018-03-09 3:43 ` [Freedreno] " Viresh Kumar 2018-03-09 10:19 ` Rajendra Nayak 2018-03-09 10:19 ` Rajendra Nayak [not found] ` <4fd61bd2-757b-ef30-a07f-ed74af031ff5-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2018-03-09 15:47 ` Jordan Crouse 2018-03-09 15:47 ` [Freedreno] " Jordan Crouse 2018-03-09 16:03 ` Jordan Crouse 2018-03-09 16:03 ` [Freedreno] " Jordan Crouse 2018-03-09 17:18 ` Stephen Boyd 2018-03-09 17:18 ` Stephen Boyd [not found] ` <152061592175.13890.6455929815877326231-n1Xw8LXHxjTHt/MElyovVYaSKrA+ACpX0E9HWUfgJXw@public.gmane.org> 2018-03-09 17:42 ` Jordan Crouse 2018-03-09 17:42 ` [Freedreno] " Jordan Crouse [not found] ` <20180309174246.GD10589-9PYrDHPZ2Orvke4nUoYGnHL1okKdlPRT@public.gmane.org> 2018-03-12 5:54 ` Viresh Kumar 2018-03-12 5:54 ` [Freedreno] " Viresh Kumar [not found] ` <20180309160355.GC10589-9PYrDHPZ2Orvke4nUoYGnHL1okKdlPRT@public.gmane.org> 2018-03-12 5:52 ` Viresh Kumar 2018-03-12 5:52 ` [Freedreno] " Viresh Kumar 2018-03-13 18:23 ` Stephen Boyd 2018-03-13 18:23 ` Stephen Boyd 2018-03-16 18:44 [v2 PATCH 0/2] arm64: dts: Add sdm845 GPU/GMU and SMMU Jordan Crouse 2018-03-16 18:44 ` [PATCH 1/2] dt-bindings: Document qcom,adreno-gmu Jordan Crouse 2018-03-16 18:51 [v2 PATCH 0/2] arm64: dts: Add sdm845 GPU/GMU and SMMU Jordan Crouse [not found] ` <20180316185152.32020-1-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2018-03-16 18:51 ` [PATCH 1/2] dt-bindings: Document qcom,adreno-gmu Jordan Crouse 2018-03-16 18:51 ` Jordan Crouse [not found] ` <20180316185152.32020-2-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2018-03-26 22:23 ` Rob Herring 2018-03-26 22:23 ` Rob Herring 2018-08-08 22:46 [v3 PATCH 0/2] arm64: dts: Add sdm845 GPU/GMU and SMMU Jordan Crouse [not found] ` <20180808224701.7527-1-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2018-08-08 22:47 ` [PATCH 1/2] dt-bindings: Document qcom,adreno-gmu Jordan Crouse 2018-08-08 22:47 ` Jordan Crouse
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