From: Rob Herring <robh@kernel.org>
To: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
Marc Zyngier <maz@kernel.org>,
kvmarm@lists.cs.columbia.edu
Subject: Re: [PATCH v3 3/3] arm64: Add workaround for Arm Cortex-A77 erratum 1508412
Date: Fri, 31 Jul 2020 16:55:26 -0600 [thread overview]
Message-ID: <CAL_JsqKhytox6+rbZBbkgs2=Zgh3ZtXeYyzjqSWF6Picn-c27A@mail.gmail.com> (raw)
In-Reply-To: <20200730082227.GA24095@willie-the-truck>
On Thu, Jul 30, 2020 at 2:22 AM Will Deacon <will@kernel.org> wrote:
>
> On Wed, Jul 29, 2020 at 05:38:00PM +0100, Catalin Marinas wrote:
> > On Fri, Jul 17, 2020 at 02:52:33PM -0600, Rob Herring wrote:
> > > diff --git a/arch/arm64/include/asm/kvm_hyp.h b/arch/arm64/include/asm/kvm_hyp.h
> > > index ce3080834bfa..ce5b0d9b12bf 100644
> > > --- a/arch/arm64/include/asm/kvm_hyp.h
> > > +++ b/arch/arm64/include/asm/kvm_hyp.h
> > > @@ -46,6 +46,17 @@
> > > #define read_sysreg_el2(r) read_sysreg_elx(r, _EL2, _EL1)
> > > #define write_sysreg_el2(v,r) write_sysreg_elx(v, r, _EL2, _EL1)
> > >
> > > +static inline u64 __hyp_text read_sysreg_par(void)
> > > +{
> > > + u64 par;
> > > + if (cpus_have_const_cap(ARM64_WORKAROUND_1508412))
> > > + dmb(sy);
> > > + par = read_sysreg(par_el1);
> > > + if (cpus_have_const_cap(ARM64_WORKAROUND_1508412))
> > > + dmb(sy);
> > > + return par;
> > > +}
> >
> > Even if that's not always called on a critical path, I agree with Andrew
> > that we could use alternatives here for dmb(sy).
>
> Even then, I'm not sure how this helps if the CPU can speculatively branch
> to the PAR access without executing the DMB. Is that not possible on A77?
I'm told by the h/w folks speculation is not possible in this case.
Rob
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Will Deacon <will@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
James Morse <james.morse@arm.com>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
Marc Zyngier <maz@kernel.org>,
kvmarm@lists.cs.columbia.edu,
Julien Thierry <julien.thierry.kdev@gmail.com>
Subject: Re: [PATCH v3 3/3] arm64: Add workaround for Arm Cortex-A77 erratum 1508412
Date: Fri, 31 Jul 2020 16:55:26 -0600 [thread overview]
Message-ID: <CAL_JsqKhytox6+rbZBbkgs2=Zgh3ZtXeYyzjqSWF6Picn-c27A@mail.gmail.com> (raw)
In-Reply-To: <20200730082227.GA24095@willie-the-truck>
On Thu, Jul 30, 2020 at 2:22 AM Will Deacon <will@kernel.org> wrote:
>
> On Wed, Jul 29, 2020 at 05:38:00PM +0100, Catalin Marinas wrote:
> > On Fri, Jul 17, 2020 at 02:52:33PM -0600, Rob Herring wrote:
> > > diff --git a/arch/arm64/include/asm/kvm_hyp.h b/arch/arm64/include/asm/kvm_hyp.h
> > > index ce3080834bfa..ce5b0d9b12bf 100644
> > > --- a/arch/arm64/include/asm/kvm_hyp.h
> > > +++ b/arch/arm64/include/asm/kvm_hyp.h
> > > @@ -46,6 +46,17 @@
> > > #define read_sysreg_el2(r) read_sysreg_elx(r, _EL2, _EL1)
> > > #define write_sysreg_el2(v,r) write_sysreg_elx(v, r, _EL2, _EL1)
> > >
> > > +static inline u64 __hyp_text read_sysreg_par(void)
> > > +{
> > > + u64 par;
> > > + if (cpus_have_const_cap(ARM64_WORKAROUND_1508412))
> > > + dmb(sy);
> > > + par = read_sysreg(par_el1);
> > > + if (cpus_have_const_cap(ARM64_WORKAROUND_1508412))
> > > + dmb(sy);
> > > + return par;
> > > +}
> >
> > Even if that's not always called on a critical path, I agree with Andrew
> > that we could use alternatives here for dmb(sy).
>
> Even then, I'm not sure how this helps if the CPU can speculatively branch
> to the PAR access without executing the DMB. Is that not possible on A77?
I'm told by the h/w folks speculation is not possible in this case.
Rob
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-07-31 22:55 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-17 20:52 [PATCH v3 0/3] Cortex-A77 erratum 1508412 workaround Rob Herring
2020-07-17 20:52 ` Rob Herring
2020-07-17 20:52 ` [PATCH v3 1/3] KVM: arm64: Print warning when cpu erratum can cause guests to deadlock Rob Herring
2020-07-17 20:52 ` Rob Herring
2020-07-17 20:52 ` [PATCH v3 2/3] arm64: Add part number for Arm Cortex-A77 Rob Herring
2020-07-17 20:52 ` Rob Herring
2020-07-17 20:52 ` [PATCH v3 3/3] arm64: Add workaround for Arm Cortex-A77 erratum 1508412 Rob Herring
2020-07-17 20:52 ` Rob Herring
2020-07-27 15:52 ` Andrew Scull
2020-07-27 15:52 ` Andrew Scull
2020-07-29 16:38 ` Catalin Marinas
2020-07-29 16:38 ` Catalin Marinas
2020-07-30 8:22 ` Will Deacon
2020-07-30 8:22 ` Will Deacon
2020-07-31 22:55 ` Rob Herring [this message]
2020-07-31 22:55 ` Rob Herring
2020-08-03 15:03 ` Will Deacon
2020-08-03 15:03 ` Will Deacon
2020-07-31 23:21 ` Rob Herring
2020-07-31 23:21 ` Rob Herring
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