Re: [PATCH v2 1/3] RISC-V: Add Zba, Zbs extension probing

From: Evan Green <evan@rivosinc.com>
To: Conor Dooley <conor@kernel.org>
Cc: Palmer Dabbelt <palmer@rivosinc.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Anup Patel <apatel@ventanamicro.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Heiko Stuebner <heiko.stuebner@vrull.eu>,
	Jisheng Zhang <jszhang@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Sunil V L <sunilvl@ventanamicro.com>,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 1/3] RISC-V: Add Zba, Zbs extension probing
Date: Tue, 9 May 2023 11:34:57 -0700	[thread overview]
Message-ID: <CALs-HstaQweGaz71GZXeu1gtVQ7Efb=i=Zgt4ETtmf1vJncxEQ@mail.gmail.com> (raw)
In-Reply-To: <20230509-exclusion-crested-67dad91b7055@spud>

On Tue, May 9, 2023 at 11:29 AM Conor Dooley <conor@kernel.org> wrote:
>
> On Tue, May 09, 2023 at 11:25:01AM -0700, Evan Green wrote:
> > Add the Zba address bit manipulation extension and Zbs single bit
> > instructions extension into those the kernel is aware of and maintains
> > in its riscv_isa bitmap.
> >
> > Signed-off-by: Evan Green <evan@rivosinc.com>
> > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> > Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
>
> Given you added the lads, rather than ignoring them due to the Zbs
> change, I think you forgot my R-b from v1?
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Whoops, yes I did. Sorry about that, and thanks for the review!

>
> Cheers,
> Conor.
>
> >
> > ---
> >
> > Changes in v2:
> >  - Add Zbs as well
> >
> >  arch/riscv/include/asm/hwcap.h | 2 ++
> >  arch/riscv/kernel/cpu.c        | 2 ++
> >  arch/riscv/kernel/cpufeature.c | 2 ++
> >  3 files changed, 6 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index e0c40a4c63d5..6b2e8ff4638c 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -46,6 +46,8 @@
> >  #define RISCV_ISA_EXT_ZICBOZ         34
> >  #define RISCV_ISA_EXT_SMAIA          35
> >  #define RISCV_ISA_EXT_SSAIA          36
> > +#define RISCV_ISA_EXT_ZBA            37
> > +#define RISCV_ISA_EXT_ZBS            38
> >
> >  #define RISCV_ISA_EXT_MAX            64
>
> Heh, gonna start getting tight on bits here soonish :)

Yeah they're flying in, I had to update mine since SMAIA swooshed in.
-Evan