From: Abhilash Kesavan <kesavan.abhilash@gmail.com>
To: Jaehoon Chung <jh80.chung@samsung.com>, prabu.t@synopsys.com
Cc: Yuvaraj Kumar C D <yuvaraj.cd@gmail.com>,
linux-samsung-soc <linux-samsung-soc@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
Doug Anderson <dianders@google.com>,
Douglas Anderson <dianders@chromium.org>,
cjb@laptop.org, tgih.jun@samsung.com, linux-mmc@vger.kernel.org,
ulf.hansson@linaro.org, Sonny Rao <sonnyrao@chromium.org>,
Tomasz Figa <t.figa@samsung.com>,
Kukjin Kim <kgene.kim@samsung.com>,
sunil joshi <joshi@samsung.com>,
Prashanth G <prashanth.g@samsung.com>,
ALIM AKHTAR <alim.akhtar@samsung.com>,
Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>,
CPGS <cpgs@samsung.com>
Subject: Re: [PATCH] mmc: dw_mmc: exynos: Add support for exynos7
Date: Mon, 1 Sep 2014 11:14:05 +0530 [thread overview]
Message-ID: <CAM4voan4ih-dD1qm85CQP9Yd0fo8xDbf7WyMdPFyHse9qO9=JA@mail.gmail.com> (raw)
In-Reply-To: <54005990.8070306@samsung.com>
Hi Jaehoon,
+Prabu Thangamuthu
On Fri, Aug 29, 2014 at 4:14 PM, Jaehoon Chung <jh80.chung@samsung.com> wrote:
> Hi, Abhilash.
>
> On 08/28/2014 10:18 PM, Yuvaraj Kumar C D wrote:
>> From: Abhilash Kesavan <a.kesavan@samsung.com>
>>
>> The Exynos7 has a DWMMC controller (v2.70a) which is different from
>> prior versions. This patch adds new compatible strings for exynos7.
>> This patch also fixes the CLKSEL register offset on exynos7.
>
> If support the 64bit, dw-mmc.c need to modify.(according to v2.70, some offset is changed for 64-bit address)
> But i didn't see any patches at mailing.
> Do you have the plan which send patch of dw-mmc.c?
We are using a rebased version of
http://www.spinics.net/lists/linux-mmc/msg21742.html to handle the
dwmmc side changes. We should have mentioned this dependency as the
patch is required for proper functioning of dwmmc on Exynos7.
Stress tests are on-going with that patch and once it looks good, we
will post our results so that the original patch may be taken forward.
Regards,
Abhilash
>
> Best Regards,
> Jaehoon Chung
>>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
>> ---
>> .../devicetree/bindings/mmc/exynos-dw-mshc.txt | 4 +
>> drivers/mmc/host/dw_mmc-exynos.c | 91 +++++++++++++++++---
>> 2 files changed, 82 insertions(+), 13 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> index 6cd3525..ee4fc05 100644
>> --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> @@ -18,6 +18,10 @@ Required Properties:
>> specific extensions.
>> - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
>> specific extensions.
>> + - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
>> + specific extensions.
>> + - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
>> + specific extensions having an SMU.
>>
>> * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
>> unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
>> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
>> index 0fbc53a..509365c 100644
>> --- a/drivers/mmc/host/dw_mmc-exynos.c
>> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>> @@ -25,6 +25,7 @@
>> #define NUM_PINS(x) (x + 2)
>>
>> #define SDMMC_CLKSEL 0x09C
>> +#define SDMMC_CLKSEL64 0x0A8
>> #define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0)
>> #define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16)
>> #define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24)
>> @@ -65,6 +66,8 @@ enum dw_mci_exynos_type {
>> DW_MCI_TYPE_EXYNOS5250,
>> DW_MCI_TYPE_EXYNOS5420,
>> DW_MCI_TYPE_EXYNOS5420_SMU,
>> + DW_MCI_TYPE_EXYNOS7,
>> + DW_MCI_TYPE_EXYNOS7_SMU,
>> };
>>
>> /* Exynos implementation specific driver private data */
>> @@ -95,6 +98,12 @@ static struct dw_mci_exynos_compatible {
>> }, {
>> .compatible = "samsung,exynos5420-dw-mshc-smu",
>> .ctrl_type = DW_MCI_TYPE_EXYNOS5420_SMU,
>> + }, {
>> + .compatible = "samsung,exynos7-dw-mshc",
>> + .ctrl_type = DW_MCI_TYPE_EXYNOS7,
>> + }, {
>> + .compatible = "samsung,exynos7-dw-mshc-smu",
>> + .ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU,
>> },
>> };
>>
>> @@ -102,7 +111,8 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
>> {
>> struct dw_mci_exynos_priv_data *priv = host->priv;
>>
>> - if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU) {
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU ||
>> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
>> mci_writel(host, MPSBEGIN0, 0);
>> mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
>> mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
>> @@ -153,11 +163,22 @@ static int dw_mci_exynos_resume(struct device *dev)
>> static int dw_mci_exynos_resume_noirq(struct device *dev)
>> {
>> struct dw_mci *host = dev_get_drvdata(dev);
>> + struct dw_mci_exynos_priv_data *priv = host->priv;
>> u32 clksel;
>>
>> - clksel = mci_readl(host, CLKSEL);
>> - if (clksel & SDMMC_CLKSEL_WAKEUP_INT)
>> - mci_writel(host, CLKSEL, clksel);
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
>> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
>> + clksel = mci_readl(host, CLKSEL64);
>> + else
>> + clksel = mci_readl(host, CLKSEL);
>> +
>> + if (clksel & SDMMC_CLKSEL_WAKEUP_INT) {
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
>> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
>> + mci_writel(host, CLKSEL64, clksel);
>> + else
>> + mci_writel(host, CLKSEL, clksel);
>> + }
>>
>> return 0;
>> }
>> @@ -169,6 +190,7 @@ static int dw_mci_exynos_resume_noirq(struct device *dev)
>>
>> static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
>> {
>> + struct dw_mci_exynos_priv_data *priv = host->priv;
>> /*
>> * Exynos4412 and Exynos5250 extends the use of CMD register with the
>> * use of bit 29 (which is reserved on standard MSHC controllers) for
>> @@ -176,8 +198,14 @@ static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
>> * HOLD register should be bypassed in case there is no phase shift
>> * applied on CMD/DATA that is sent to the card.
>> */
>> - if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
>> - *cmdr |= SDMMC_CMD_USE_HOLD_REG;
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
>> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
>> + if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL64)))
>> + *cmdr |= SDMMC_CMD_USE_HOLD_REG;
>> + } else {
>> + if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
>> + *cmdr |= SDMMC_CMD_USE_HOLD_REG;
>> + }
>> }
>>
>> static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
>> @@ -188,12 +216,20 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
>> u8 div = priv->ciu_div + 1;
>>
>> if (ios->timing == MMC_TIMING_MMC_DDR52) {
>> - mci_writel(host, CLKSEL, priv->ddr_timing);
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
>> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
>> + mci_writel(host, CLKSEL64, priv->ddr_timing);
>> + else
>> + mci_writel(host, CLKSEL, priv->ddr_timing);
>> /* Should be double rate for DDR mode */
>> if (ios->bus_width == MMC_BUS_WIDTH_8)
>> wanted <<= 1;
>> } else {
>> - mci_writel(host, CLKSEL, priv->sdr_timing);
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
>> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
>> + mci_writel(host, CLKSEL64, priv->sdr_timing);
>> + else
>> + mci_writel(host, CLKSEL, priv->sdr_timing);
>> }
>>
>> /* Don't care if wanted clock is zero */
>> @@ -265,26 +301,51 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
>>
>> static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host)
>> {
>> - return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
>> + struct dw_mci_exynos_priv_data *priv = host->priv;
>> +
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
>> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
>> + return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64));
>> + else
>> + return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
>> }
>>
>> static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample)
>> {
>> u32 clksel;
>> - clksel = mci_readl(host, CLKSEL);
>> + struct dw_mci_exynos_priv_data *priv = host->priv;
>> +
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
>> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
>> + clksel = mci_readl(host, CLKSEL64);
>> + else
>> + clksel = mci_readl(host, CLKSEL);
>> clksel = (clksel & ~0x7) | SDMMC_CLKSEL_CCLK_SAMPLE(sample);
>> - mci_writel(host, CLKSEL, clksel);
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
>> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
>> + mci_writel(host, CLKSEL64, clksel);
>> + else
>> + mci_writel(host, CLKSEL, clksel);
>> }
>>
>> static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
>> {
>> + struct dw_mci_exynos_priv_data *priv = host->priv;
>> u32 clksel;
>> u8 sample;
>>
>> - clksel = mci_readl(host, CLKSEL);
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
>> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
>> + clksel = mci_readl(host, CLKSEL64);
>> + else
>> + clksel = mci_readl(host, CLKSEL);
>> sample = (clksel + 1) & 0x7;
>> clksel = (clksel & ~0x7) | sample;
>> - mci_writel(host, CLKSEL, clksel);
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
>> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
>> + mci_writel(host, CLKSEL64, clksel);
>> + else
>> + mci_writel(host, CLKSEL, clksel);
>> return sample;
>> }
>>
>> @@ -411,6 +472,10 @@ static const struct of_device_id dw_mci_exynos_match[] = {
>> .data = &exynos_drv_data, },
>> { .compatible = "samsung,exynos5420-dw-mshc-smu",
>> .data = &exynos_drv_data, },
>> + { .compatible = "samsung,exynos7-dw-mshc",
>> + .data = &exynos_drv_data, },
>> + { .compatible = "samsung,exynos7-dw-mshc-smu",
>> + .data = &exynos_drv_data, },
>> {},
>> };
>> MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
>>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
WARNING: multiple messages have this Message-ID (diff)
From: kesavan.abhilash@gmail.com (Abhilash Kesavan)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] mmc: dw_mmc: exynos: Add support for exynos7
Date: Mon, 1 Sep 2014 11:14:05 +0530 [thread overview]
Message-ID: <CAM4voan4ih-dD1qm85CQP9Yd0fo8xDbf7WyMdPFyHse9qO9=JA@mail.gmail.com> (raw)
In-Reply-To: <54005990.8070306@samsung.com>
Hi Jaehoon,
+Prabu Thangamuthu
On Fri, Aug 29, 2014 at 4:14 PM, Jaehoon Chung <jh80.chung@samsung.com> wrote:
> Hi, Abhilash.
>
> On 08/28/2014 10:18 PM, Yuvaraj Kumar C D wrote:
>> From: Abhilash Kesavan <a.kesavan@samsung.com>
>>
>> The Exynos7 has a DWMMC controller (v2.70a) which is different from
>> prior versions. This patch adds new compatible strings for exynos7.
>> This patch also fixes the CLKSEL register offset on exynos7.
>
> If support the 64bit, dw-mmc.c need to modify.(according to v2.70, some offset is changed for 64-bit address)
> But i didn't see any patches at mailing.
> Do you have the plan which send patch of dw-mmc.c?
We are using a rebased version of
http://www.spinics.net/lists/linux-mmc/msg21742.html to handle the
dwmmc side changes. We should have mentioned this dependency as the
patch is required for proper functioning of dwmmc on Exynos7.
Stress tests are on-going with that patch and once it looks good, we
will post our results so that the original patch may be taken forward.
Regards,
Abhilash
>
> Best Regards,
> Jaehoon Chung
>>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
>> ---
>> .../devicetree/bindings/mmc/exynos-dw-mshc.txt | 4 +
>> drivers/mmc/host/dw_mmc-exynos.c | 91 +++++++++++++++++---
>> 2 files changed, 82 insertions(+), 13 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> index 6cd3525..ee4fc05 100644
>> --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> @@ -18,6 +18,10 @@ Required Properties:
>> specific extensions.
>> - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
>> specific extensions.
>> + - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
>> + specific extensions.
>> + - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
>> + specific extensions having an SMU.
>>
>> * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
>> unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
>> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
>> index 0fbc53a..509365c 100644
>> --- a/drivers/mmc/host/dw_mmc-exynos.c
>> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>> @@ -25,6 +25,7 @@
>> #define NUM_PINS(x) (x + 2)
>>
>> #define SDMMC_CLKSEL 0x09C
>> +#define SDMMC_CLKSEL64 0x0A8
>> #define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0)
>> #define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16)
>> #define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24)
>> @@ -65,6 +66,8 @@ enum dw_mci_exynos_type {
>> DW_MCI_TYPE_EXYNOS5250,
>> DW_MCI_TYPE_EXYNOS5420,
>> DW_MCI_TYPE_EXYNOS5420_SMU,
>> + DW_MCI_TYPE_EXYNOS7,
>> + DW_MCI_TYPE_EXYNOS7_SMU,
>> };
>>
>> /* Exynos implementation specific driver private data */
>> @@ -95,6 +98,12 @@ static struct dw_mci_exynos_compatible {
>> }, {
>> .compatible = "samsung,exynos5420-dw-mshc-smu",
>> .ctrl_type = DW_MCI_TYPE_EXYNOS5420_SMU,
>> + }, {
>> + .compatible = "samsung,exynos7-dw-mshc",
>> + .ctrl_type = DW_MCI_TYPE_EXYNOS7,
>> + }, {
>> + .compatible = "samsung,exynos7-dw-mshc-smu",
>> + .ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU,
>> },
>> };
>>
>> @@ -102,7 +111,8 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
>> {
>> struct dw_mci_exynos_priv_data *priv = host->priv;
>>
>> - if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU) {
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU ||
>> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
>> mci_writel(host, MPSBEGIN0, 0);
>> mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
>> mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
>> @@ -153,11 +163,22 @@ static int dw_mci_exynos_resume(struct device *dev)
>> static int dw_mci_exynos_resume_noirq(struct device *dev)
>> {
>> struct dw_mci *host = dev_get_drvdata(dev);
>> + struct dw_mci_exynos_priv_data *priv = host->priv;
>> u32 clksel;
>>
>> - clksel = mci_readl(host, CLKSEL);
>> - if (clksel & SDMMC_CLKSEL_WAKEUP_INT)
>> - mci_writel(host, CLKSEL, clksel);
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
>> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
>> + clksel = mci_readl(host, CLKSEL64);
>> + else
>> + clksel = mci_readl(host, CLKSEL);
>> +
>> + if (clksel & SDMMC_CLKSEL_WAKEUP_INT) {
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
>> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
>> + mci_writel(host, CLKSEL64, clksel);
>> + else
>> + mci_writel(host, CLKSEL, clksel);
>> + }
>>
>> return 0;
>> }
>> @@ -169,6 +190,7 @@ static int dw_mci_exynos_resume_noirq(struct device *dev)
>>
>> static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
>> {
>> + struct dw_mci_exynos_priv_data *priv = host->priv;
>> /*
>> * Exynos4412 and Exynos5250 extends the use of CMD register with the
>> * use of bit 29 (which is reserved on standard MSHC controllers) for
>> @@ -176,8 +198,14 @@ static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
>> * HOLD register should be bypassed in case there is no phase shift
>> * applied on CMD/DATA that is sent to the card.
>> */
>> - if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
>> - *cmdr |= SDMMC_CMD_USE_HOLD_REG;
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
>> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
>> + if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL64)))
>> + *cmdr |= SDMMC_CMD_USE_HOLD_REG;
>> + } else {
>> + if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
>> + *cmdr |= SDMMC_CMD_USE_HOLD_REG;
>> + }
>> }
>>
>> static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
>> @@ -188,12 +216,20 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
>> u8 div = priv->ciu_div + 1;
>>
>> if (ios->timing == MMC_TIMING_MMC_DDR52) {
>> - mci_writel(host, CLKSEL, priv->ddr_timing);
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
>> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
>> + mci_writel(host, CLKSEL64, priv->ddr_timing);
>> + else
>> + mci_writel(host, CLKSEL, priv->ddr_timing);
>> /* Should be double rate for DDR mode */
>> if (ios->bus_width == MMC_BUS_WIDTH_8)
>> wanted <<= 1;
>> } else {
>> - mci_writel(host, CLKSEL, priv->sdr_timing);
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
>> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
>> + mci_writel(host, CLKSEL64, priv->sdr_timing);
>> + else
>> + mci_writel(host, CLKSEL, priv->sdr_timing);
>> }
>>
>> /* Don't care if wanted clock is zero */
>> @@ -265,26 +301,51 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
>>
>> static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host)
>> {
>> - return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
>> + struct dw_mci_exynos_priv_data *priv = host->priv;
>> +
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
>> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
>> + return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64));
>> + else
>> + return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
>> }
>>
>> static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample)
>> {
>> u32 clksel;
>> - clksel = mci_readl(host, CLKSEL);
>> + struct dw_mci_exynos_priv_data *priv = host->priv;
>> +
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
>> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
>> + clksel = mci_readl(host, CLKSEL64);
>> + else
>> + clksel = mci_readl(host, CLKSEL);
>> clksel = (clksel & ~0x7) | SDMMC_CLKSEL_CCLK_SAMPLE(sample);
>> - mci_writel(host, CLKSEL, clksel);
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
>> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
>> + mci_writel(host, CLKSEL64, clksel);
>> + else
>> + mci_writel(host, CLKSEL, clksel);
>> }
>>
>> static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
>> {
>> + struct dw_mci_exynos_priv_data *priv = host->priv;
>> u32 clksel;
>> u8 sample;
>>
>> - clksel = mci_readl(host, CLKSEL);
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
>> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
>> + clksel = mci_readl(host, CLKSEL64);
>> + else
>> + clksel = mci_readl(host, CLKSEL);
>> sample = (clksel + 1) & 0x7;
>> clksel = (clksel & ~0x7) | sample;
>> - mci_writel(host, CLKSEL, clksel);
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
>> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
>> + mci_writel(host, CLKSEL64, clksel);
>> + else
>> + mci_writel(host, CLKSEL, clksel);
>> return sample;
>> }
>>
>> @@ -411,6 +472,10 @@ static const struct of_device_id dw_mci_exynos_match[] = {
>> .data = &exynos_drv_data, },
>> { .compatible = "samsung,exynos5420-dw-mshc-smu",
>> .data = &exynos_drv_data, },
>> + { .compatible = "samsung,exynos7-dw-mshc",
>> + .data = &exynos_drv_data, },
>> + { .compatible = "samsung,exynos7-dw-mshc-smu",
>> + .data = &exynos_drv_data, },
>> {},
>> };
>> MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
>>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
next prev parent reply other threads:[~2014-09-01 5:44 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-28 13:18 [PATCH] mmc: dw_mmc: exynos: Add support for exynos7 Yuvaraj Kumar C D
2014-08-28 13:18 ` Yuvaraj Kumar C D
2014-08-29 10:44 ` Jaehoon Chung
2014-08-29 10:44 ` Jaehoon Chung
2014-09-01 5:44 ` Abhilash Kesavan [this message]
2014-09-01 5:44 ` Abhilash Kesavan
2014-10-21 8:17 ` Vivek Gautam
2014-10-21 8:17 ` Vivek Gautam
2014-10-21 8:20 ` Vivek Gautam
2014-10-21 8:20 ` Vivek Gautam
2014-11-11 14:14 ` Alim Akhtar
2014-11-11 14:14 ` Alim Akhtar
2014-11-12 1:41 ` Jaehoon Chung
2014-11-12 1:41 ` Jaehoon Chung
2014-11-12 8:16 ` Ulf Hansson
2014-11-12 8:16 ` Ulf Hansson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAM4voan4ih-dD1qm85CQP9Yd0fo8xDbf7WyMdPFyHse9qO9=JA@mail.gmail.com' \
--to=kesavan.abhilash@gmail.com \
--cc=alim.akhtar@samsung.com \
--cc=cjb@laptop.org \
--cc=cpgs@samsung.com \
--cc=dianders@chromium.org \
--cc=dianders@google.com \
--cc=jh80.chung@samsung.com \
--cc=joshi@samsung.com \
--cc=kgene.kim@samsung.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-mmc@vger.kernel.org \
--cc=linux-samsung-soc@vger.kernel.org \
--cc=prabu.t@synopsys.com \
--cc=prashanth.g@samsung.com \
--cc=sonnyrao@chromium.org \
--cc=t.figa@samsung.com \
--cc=tgih.jun@samsung.com \
--cc=ulf.hansson@linaro.org \
--cc=yuvaraj.cd@gmail.com \
--cc=yuvaraj.cd@samsung.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.