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From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Claudiu <claudiu.beznea@tuxon.dev>
Cc: magnus.damm@gmail.com, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
	mturquette@baylibre.com, sboyd@kernel.org,
	linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: Re: [PATCH 4/6] arm64: dts: renesas: rzg3s-smarc-som: Enable SDHI2
Date: Thu, 12 Oct 2023 16:36:34 +0200	[thread overview]
Message-ID: <CAMuHMdW-m+ikzOiCqGaiofd0QG5BVuoMK+z6G7u2JboGTw3xhQ@mail.gmail.com> (raw)
In-Reply-To: <20231010132701.1658737-5-claudiu.beznea.uj@bp.renesas.com>

Hi Claudiu,

Thanks for your patch!

On Tue, Oct 10, 2023 at 3:27 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Add SDHI2 to RZ/G3S Smarc SoM. SDHI2 pins are multiplexed with SCIF1, SSI3,

SSI0

> IRQ0. The selection b/w SDHI2 and SCIF1, SSI3, IRQ0 is done with a switch

and IRQ1 (twice). Or just say "The selection is done ...".

> button. To be able to select b/w these a compilation flag has been added
> (SW_SD2_EN) at the moment being instantiated to select SDHI2.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

> --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> @@ -13,14 +13,21 @@
>   * @SW_SD0_DEV_SEL:
>   *     0 - SD0 is connected to eMMC
>   *     1 - SD0 is connected to uSD0 card
> + * @SW_SD2_EN:
> + *     0 - SCIF1, SSI3, IRQ0, IRQ1 connected to SoC

SSI0

> + *     1 - SD2 is connected to SoC
>   */
>  #define SW_SD0_DEV_SEL 1
> +#define SW_SD2_EN      1

> @@ -100,6 +125,19 @@ &sdhi0 {
>  };
>  #endif
>
> +#if SW_SD2_EN
> +&sdhi2 {
> +       pinctrl-0 = <&sdhi2_pins>;
> +       pinctrl-1 = <&sdhi2_pins>;
> +       pinctrl-names = "default", "state_uhs";

Do you need two states if there is only a single voltage?
AFAIK, UHS needs 1.8V.

> +       vmmc-supply = <&vcc_sdhi2>;
> +       vqmmc-supply = <&reg_3p3v>;
> +       bus-width = <4>;
> +       max-frequency = <50000000>;
> +       status = "okay";
> +};
> +#endif
> +
>  &pinctrl {
>         sdhi0_pins: sd0 {
>                 data {

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

  reply	other threads:[~2023-10-12 14:36 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-10 13:26 [PATCH 0/6] arm64: dts: renesas: Add SDHI1 and SDHI2 for RZ/G3S Claudiu
2023-10-10 13:26 ` [PATCH 1/6] clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R() Claudiu
2023-10-10 14:52   ` Sergei Shtylyov
2023-10-11  7:36     ` claudiu beznea
2023-10-11  7:43       ` Geert Uytterhoeven
2023-10-11 15:55         ` claudiu beznea
2023-10-12 12:37   ` Geert Uytterhoeven
2023-10-10 13:26 ` [PATCH 2/6] clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2 Claudiu
2023-10-12 13:22   ` Geert Uytterhoeven
2023-10-10 13:26 ` [PATCH 3/6] arm64: dts: renesas: r9a08g045: Add nodes " Claudiu
2023-10-12 13:35   ` Geert Uytterhoeven
2023-10-10 13:26 ` [PATCH 4/6] arm64: dts: renesas: rzg3s-smarc-som: Enable SDHI2 Claudiu
2023-10-12 14:36   ` Geert Uytterhoeven [this message]
2023-10-13  5:45     ` claudiu beznea
2023-10-10 13:27 ` [PATCH 5/6] arm64: dts: renesas: rzg3s-smarc: Enable SDHI1 Claudiu
2023-10-12 14:44   ` Geert Uytterhoeven
2023-10-13  5:51     ` claudiu beznea
2023-10-10 13:27 ` [PATCH 6/6] arm64: dts: renesas: rzg3s: Fix dtbs_check Claudiu
2023-10-12 14:49   ` Geert Uytterhoeven
2023-10-13  5:55     ` claudiu beznea

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