From: Nicolas Boichat <drinkcat@chromium.org> To: Qii Wang <qii.wang@mediatek.com> Cc: wsa@the-dreams.de, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-arm Mailing List <linux-arm-kernel@lists.infradead.org>, lkml <linux-kernel@vger.kernel.org>, "moderated list:ARM/Mediatek SoC support" <linux-mediatek@lists.infradead.org>, srv_heupstream <srv_heupstream@mediatek.com>, Leilk Liu <leilk.liu@mediatek.com>, xinping.qian@mediatek.com, liguo.zhang@mediatek.com, Rob Herring <robh@kernel.org> Subject: Re: [PATCH v6 6/6] dts: arm64: mt8183: Add I2C nodes Date: Mon, 11 Mar 2019 16:36:22 +0800 [thread overview] Message-ID: <CANMq1KDqKy=F0+Ld+k1-E9Y9qxfYMDORJPHvqEpCBGi5G7+zgw@mail.gmail.com> (raw) In-Reply-To: <1552282840-12778-7-git-send-email-qii.wang@mediatek.com> On Mon, Mar 11, 2019 at 1:41 PM Qii Wang <qii.wang@mediatek.com> wrote: > > This patch adds nodes for I2C controller. > > Signed-off-by: Qii Wang <qii.wang@mediatek.com> > --- This applies on top of some other uncommitted series, right? This is fine, but please say which one. > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 190 ++++++++++++++++++++++++++++++ > 1 file changed, 190 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > index 165b859..f20f1af 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -16,6 +16,21 @@ > #address-cells = <2>; > #size-cells = <2>; > > + aliases { > + i2c0 = &i2c0; > + i2c1 = &i2c1; > + i2c2 = &i2c2; > + i2c3 = &i2c3; > + i2c4 = &i2c4; > + i2c5 = &i2c5; > + i2c6 = &i2c6; > + i2c7 = &i2c7; > + i2c8 = &i2c8; > + i2c9 = &i2c9; > + i2c10 = &i2c10; > + i2c11 = &i2c11; > + }; > + > cpus { > #address-cells = <1>; > #size-cells = <0>; > @@ -268,6 +283,79 @@ > status = "disabled"; > }; > > + i2c6: i2c@11005000 { > + compatible = "mediatek,mt8183-i2c"; > + reg = <0 0x11005000 0 0x1000>, > + <0 0x11000600 0 0x80>; > + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C6>, > + <&infracfg CLK_INFRA_AP_DMA>; > + clock-names = "main", "dma"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c0: i2c@11007000 { > + compatible = "mediatek,mt8183-i2c"; > + reg = <0 0x11007000 0 0x1000>, > + <0 0x11000080 0 0x80>; > + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C0>, > + <&infracfg CLK_INFRA_AP_DMA>; > + clock-names = "main", "dma"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c4: i2c@11008000 { > + compatible = "mediatek,mt8183-i2c"; > + id = <4>; > + reg = <0 0x11008000 0 0x1000>, > + <0 0x11000100 0 0x80>; > + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C1>, > + <&infracfg CLK_INFRA_AP_DMA>, > + <&infracfg CLK_INFRA_I2C1_ARBITER>; > + clock-names = "main", "dma","arb"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c2: i2c@11009000 { > + compatible = "mediatek,mt8183-i2c"; > + reg = <0 0x11009000 0 0x1000>, > + <0 0x11000280 0 0x80>; > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C2>, > + <&infracfg CLK_INFRA_AP_DMA>, > + <&infracfg CLK_INFRA_I2C2_ARBITER>; > + clock-names = "main", "dma", "arb"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c3: i2c@1100f000 { > + compatible = "mediatek,mt8183-i2c"; > + reg = <0 0x1100f000 0 0x1000>, > + <0 0x11000400 0 0x80>; > + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C3>, > + <&infracfg CLK_INFRA_AP_DMA>; > + clock-names = "main", "dma"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > spi0: spi@1100a000 { > compatible = "mediatek,mt8183-spi"; > #address-cells = <1>; > @@ -294,6 +382,20 @@ > status = "disabled"; > }; > > + i2c1: i2c@11011000 { > + compatible = "mediatek,mt8183-i2c"; > + reg = <0 0x11011000 0 0x1000>, > + <0 0x11000480 0 0x80>; > + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C4>, > + <&infracfg CLK_INFRA_AP_DMA>; > + clock-names = "main", "dma"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > spi2: spi@11012000 { > compatible = "mediatek,mt8183-spi"; > #address-cells = <1>; > @@ -320,6 +422,66 @@ > status = "disabled"; > }; > > + i2c9: i2c@11014000 { > + compatible = "mediatek,mt8183-i2c"; > + reg = <0 0x11014000 0 0x1000>, > + <0 0x11000180 0 0x80>; > + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C1_IMM>, > + <&infracfg CLK_INFRA_AP_DMA>, > + <&infracfg CLK_INFRA_I2C1_ARBITER>; > + clock-names = "main", "dma", "arb"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c10: i2c@11015000 { > + compatible = "mediatek,mt8183-i2c"; > + reg = <0 0x11015000 0 0x1000>, > + <0 0x11000300 0 0x80>; > + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C2_IMM>, > + <&infracfg CLK_INFRA_AP_DMA>, > + <&infracfg CLK_INFRA_I2C2_ARBITER>; > + clock-names = "main", "dma", "arb"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c5: i2c@11016000 { > + compatible = "mediatek,mt8183-i2c"; > + reg = <0 0x11016000 0 0x1000>, > + <0 0x11000500 0 0x80>; > + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C5>, > + <&infracfg CLK_INFRA_AP_DMA>, > + <&infracfg CLK_INFRA_I2C5_ARBITER>; > + clock-names = "main", "dma", "arb"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c11: i2c@11017000 { > + compatible = "mediatek,mt8183-i2c"; > + reg = <0 0x11017000 0 0x1000>, > + <0 0x11000580 0 0x80>; > + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C5_IMM>, > + <&infracfg CLK_INFRA_AP_DMA>, > + <&infracfg CLK_INFRA_I2C5_ARBITER>; > + clock-names = "main", "dma", "arb"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > spi4: spi@11018000 { > compatible = "mediatek,mt8183-spi"; > #address-cells = <1>; > @@ -346,6 +508,34 @@ > status = "disabled"; > }; > > + i2c7: i2c@1101a000 { > + compatible = "mediatek,mt8183-i2c"; > + reg = <0 0x1101a000 0 0x1000>, > + <0 0x11000680 0 0x80>; > + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C7>, > + <&infracfg CLK_INFRA_AP_DMA>; > + clock-names = "main", "dma"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c8: i2c@1101b000 { > + compatible = "mediatek,mt8183-i2c"; > + reg = <0 0x1101b000 0 0x1000>, > + <0 0x11000700 0 0x80>; > + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C8>, > + <&infracfg CLK_INFRA_AP_DMA>; > + clock-names = "main", "dma"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > audiosys: syscon@11220000 { > compatible = "mediatek,mt8183-audiosys", "syscon"; > reg = <0 0x11220000 0 0x1000>; > -- > 1.7.9.5 >
WARNING: multiple messages have this Message-ID (diff)
From: Nicolas Boichat <drinkcat@chromium.org> To: Qii Wang <qii.wang@mediatek.com> Cc: devicetree@vger.kernel.org, srv_heupstream <srv_heupstream@mediatek.com>, wsa@the-dreams.de, Leilk Liu <leilk.liu@mediatek.com>, xinping.qian@mediatek.com, lkml <linux-kernel@vger.kernel.org>, liguo.zhang@mediatek.com, "moderated list:ARM/Mediatek SoC support" <linux-mediatek@lists.infradead.org>, linux-i2c@vger.kernel.org, Rob Herring <robh@kernel.org>, linux-arm Mailing List <linux-arm-kernel@lists.infradead.org> Subject: Re: [PATCH v6 6/6] dts: arm64: mt8183: Add I2C nodes Date: Mon, 11 Mar 2019 16:36:22 +0800 [thread overview] Message-ID: <CANMq1KDqKy=F0+Ld+k1-E9Y9qxfYMDORJPHvqEpCBGi5G7+zgw@mail.gmail.com> (raw) In-Reply-To: <1552282840-12778-7-git-send-email-qii.wang@mediatek.com> On Mon, Mar 11, 2019 at 1:41 PM Qii Wang <qii.wang@mediatek.com> wrote: > > This patch adds nodes for I2C controller. > > Signed-off-by: Qii Wang <qii.wang@mediatek.com> > --- This applies on top of some other uncommitted series, right? This is fine, but please say which one. > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 190 ++++++++++++++++++++++++++++++ > 1 file changed, 190 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > index 165b859..f20f1af 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -16,6 +16,21 @@ > #address-cells = <2>; > #size-cells = <2>; > > + aliases { > + i2c0 = &i2c0; > + i2c1 = &i2c1; > + i2c2 = &i2c2; > + i2c3 = &i2c3; > + i2c4 = &i2c4; > + i2c5 = &i2c5; > + i2c6 = &i2c6; > + i2c7 = &i2c7; > + i2c8 = &i2c8; > + i2c9 = &i2c9; > + i2c10 = &i2c10; > + i2c11 = &i2c11; > + }; > + > cpus { > #address-cells = <1>; > #size-cells = <0>; > @@ -268,6 +283,79 @@ > status = "disabled"; > }; > > + i2c6: i2c@11005000 { > + compatible = "mediatek,mt8183-i2c"; > + reg = <0 0x11005000 0 0x1000>, > + <0 0x11000600 0 0x80>; > + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C6>, > + <&infracfg CLK_INFRA_AP_DMA>; > + clock-names = "main", "dma"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c0: i2c@11007000 { > + compatible = "mediatek,mt8183-i2c"; > + reg = <0 0x11007000 0 0x1000>, > + <0 0x11000080 0 0x80>; > + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C0>, > + <&infracfg CLK_INFRA_AP_DMA>; > + clock-names = "main", "dma"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c4: i2c@11008000 { > + compatible = "mediatek,mt8183-i2c"; > + id = <4>; > + reg = <0 0x11008000 0 0x1000>, > + <0 0x11000100 0 0x80>; > + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C1>, > + <&infracfg CLK_INFRA_AP_DMA>, > + <&infracfg CLK_INFRA_I2C1_ARBITER>; > + clock-names = "main", "dma","arb"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c2: i2c@11009000 { > + compatible = "mediatek,mt8183-i2c"; > + reg = <0 0x11009000 0 0x1000>, > + <0 0x11000280 0 0x80>; > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C2>, > + <&infracfg CLK_INFRA_AP_DMA>, > + <&infracfg CLK_INFRA_I2C2_ARBITER>; > + clock-names = "main", "dma", "arb"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c3: i2c@1100f000 { > + compatible = "mediatek,mt8183-i2c"; > + reg = <0 0x1100f000 0 0x1000>, > + <0 0x11000400 0 0x80>; > + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C3>, > + <&infracfg CLK_INFRA_AP_DMA>; > + clock-names = "main", "dma"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > spi0: spi@1100a000 { > compatible = "mediatek,mt8183-spi"; > #address-cells = <1>; > @@ -294,6 +382,20 @@ > status = "disabled"; > }; > > + i2c1: i2c@11011000 { > + compatible = "mediatek,mt8183-i2c"; > + reg = <0 0x11011000 0 0x1000>, > + <0 0x11000480 0 0x80>; > + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C4>, > + <&infracfg CLK_INFRA_AP_DMA>; > + clock-names = "main", "dma"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > spi2: spi@11012000 { > compatible = "mediatek,mt8183-spi"; > #address-cells = <1>; > @@ -320,6 +422,66 @@ > status = "disabled"; > }; > > + i2c9: i2c@11014000 { > + compatible = "mediatek,mt8183-i2c"; > + reg = <0 0x11014000 0 0x1000>, > + <0 0x11000180 0 0x80>; > + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C1_IMM>, > + <&infracfg CLK_INFRA_AP_DMA>, > + <&infracfg CLK_INFRA_I2C1_ARBITER>; > + clock-names = "main", "dma", "arb"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c10: i2c@11015000 { > + compatible = "mediatek,mt8183-i2c"; > + reg = <0 0x11015000 0 0x1000>, > + <0 0x11000300 0 0x80>; > + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C2_IMM>, > + <&infracfg CLK_INFRA_AP_DMA>, > + <&infracfg CLK_INFRA_I2C2_ARBITER>; > + clock-names = "main", "dma", "arb"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c5: i2c@11016000 { > + compatible = "mediatek,mt8183-i2c"; > + reg = <0 0x11016000 0 0x1000>, > + <0 0x11000500 0 0x80>; > + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C5>, > + <&infracfg CLK_INFRA_AP_DMA>, > + <&infracfg CLK_INFRA_I2C5_ARBITER>; > + clock-names = "main", "dma", "arb"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c11: i2c@11017000 { > + compatible = "mediatek,mt8183-i2c"; > + reg = <0 0x11017000 0 0x1000>, > + <0 0x11000580 0 0x80>; > + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C5_IMM>, > + <&infracfg CLK_INFRA_AP_DMA>, > + <&infracfg CLK_INFRA_I2C5_ARBITER>; > + clock-names = "main", "dma", "arb"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > spi4: spi@11018000 { > compatible = "mediatek,mt8183-spi"; > #address-cells = <1>; > @@ -346,6 +508,34 @@ > status = "disabled"; > }; > > + i2c7: i2c@1101a000 { > + compatible = "mediatek,mt8183-i2c"; > + reg = <0 0x1101a000 0 0x1000>, > + <0 0x11000680 0 0x80>; > + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C7>, > + <&infracfg CLK_INFRA_AP_DMA>; > + clock-names = "main", "dma"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c8: i2c@1101b000 { > + compatible = "mediatek,mt8183-i2c"; > + reg = <0 0x1101b000 0 0x1000>, > + <0 0x11000700 0 0x80>; > + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_INFRA_I2C8>, > + <&infracfg CLK_INFRA_AP_DMA>; > + clock-names = "main", "dma"; > + clock-div = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > audiosys: syscon@11220000 { > compatible = "mediatek,mt8183-audiosys", "syscon"; > reg = <0 0x11220000 0 0x1000>; > -- > 1.7.9.5 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-03-11 8:36 UTC|newest] Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-03-11 5:40 [PATCH v6 0/6] add i2c support for mt8183 Qii Wang 2019-03-11 5:40 ` Qii Wang 2019-03-11 5:40 ` Qii Wang 2019-03-11 5:40 ` [PATCH v6 1/6] i2c: mediatek: Add offsets array for new i2c registers Qii Wang 2019-03-11 5:40 ` Qii Wang 2019-03-11 5:40 ` Qii Wang 2019-03-11 5:40 ` [PATCH v6 2/6] dt-bindings: i2c: Add Mediatek MT8183 i2c binding Qii Wang 2019-03-11 5:40 ` Qii Wang 2019-03-11 5:40 ` Qii Wang 2019-03-11 5:40 ` [PATCH v6 3/6] i2c: mediatek: Add arb clock in i2c driver Qii Wang 2019-03-11 5:40 ` Qii Wang 2019-03-11 5:40 ` Qii Wang 2019-03-11 8:28 ` Nicolas Boichat 2019-03-11 8:28 ` Nicolas Boichat 2019-03-11 8:28 ` Nicolas Boichat 2019-03-11 5:40 ` [PATCH v6 4/6] i2c: mediatek: Add i2c and apdma sync " Qii Wang 2019-03-11 5:40 ` Qii Wang 2019-03-11 5:40 ` Qii Wang 2019-03-11 5:40 ` [PATCH v6 5/6] i2c: mediatek: Add i2c support for MediaTek MT8183 Qii Wang 2019-03-11 5:40 ` Qii Wang 2019-03-11 5:40 ` Qii Wang 2019-03-11 8:34 ` Nicolas Boichat 2019-03-11 8:34 ` Nicolas Boichat 2019-03-11 8:34 ` Nicolas Boichat 2019-03-11 5:40 ` [PATCH v6 6/6] dts: arm64: mt8183: Add I2C nodes Qii Wang 2019-03-11 5:40 ` Qii Wang 2019-03-11 5:40 ` Qii Wang 2019-03-11 8:36 ` Nicolas Boichat [this message] 2019-03-11 8:36 ` Nicolas Boichat 2019-03-11 8:36 ` Nicolas Boichat 2019-03-11 9:43 ` Qii Wang 2019-03-11 9:43 ` Qii Wang 2019-03-11 9:43 ` Qii Wang
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