Re: [PATCH v3 04/10] drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit setting

From: Sean Paul <seanpaul@chromium.org>
To: Yakir Yang <ykk@rock-chips.com>
Cc: "Mark Yao" <yzq@rock-chips.com>,
	"Inki Dae" <inki.dae@samsung.com>,
	"Jingoo Han" <jingoohan1@gmail.com>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"Krzysztof Kozlowski" <k.kozlowski@samsung.com>,
	linux-samsung-soc <linux-samsung-soc@vger.kernel.org>,
	linux-rockchip@lists.infradead.org,
	"Daniel Vetter" <daniel.vetter@ffwll.ch>,
	"Emil Velikov" <emil.l.velikov@gmail.com>,
	"Douglas Anderson" <dianders@chromium.org>,
	dri-devel <dri-devel@lists.freedesktop.org>,
	"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
	"Javier Martinez Canillas" <javier@osg.samsung.com>,
	"Tomasz Figa" <tomasz.figa@chromium.com>,
	"Stéphane Marchesin" <marcheu@chromium.org>,
	"Thierry Reding" <treding@nvidia.com>,
	"Dan Carpenter" <dan.carpenter@oracle.com>
Subject: Re: [PATCH v3 04/10] drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit setting
Date: Thu, 23 Jun 2016 09:27:32 -0400	[thread overview]
Message-ID: <CAOw6vbKr68PMMNyptZas18Z0JPLyqnX+t+EvQSCy=i5tsbQKRA@mail.gmail.com> (raw)
In-Reply-To: <1465904776-891-1-git-send-email-ykk@rock-chips.com>

On Tue, Jun 14, 2016 at 7:46 AM, Yakir Yang <ykk@rock-chips.com> wrote:
> As vendor document indicate, when REF_CLK bit set 0, then DP
> phy's REF_CLK should switch to 24M source clock.
>
> But due to IC PHY layout mistaken, some chips need to flip this
> bit(like RK3288), and unfortunately they didn't indicate in the
> DP version register. That's why we have to make this little hack.
>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
> ---
> Changes in v3:
> - Make this hack code more clear (Tomasz, reviewed at Google Gerrit)
>   reg = ~reg & REF_CLK_MASK;  --->  reg ^= REF_CLK_MASK;
>     [https://chromium-review.googlesource.com/#/c/346852/7/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c@80]
> - Add tested flag from Javier
>
> Changes in v2:
> - new patch in v2
>
>  drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 6 +++++-
>  drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 1 +
>  drivers/gpu/drm/rockchip/analogix_dp-rockchip.c   | 3 +++
>  include/drm/bridge/analogix_dp.h                  | 5 +++++
>  4 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> index 931a76c..97ced6b 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> @@ -75,7 +75,11 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
>         writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
>
>         if (dp->plat_data && (dp->plat_data->dev_type == ROCKCHIP_DP)) {
> -               writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
> +               reg = REF_CLK_24M;
> +               if (dp->plat_data->subdev_type == RK3288_DP)
> +                       reg ^= REF_CLK_MASK;
> +
> +               writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
>                 writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
>                 writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
>                 writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
> index 88d56ad..cdcc6c5 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
> @@ -165,6 +165,7 @@
>  /* ANALOGIX_DP_PLL_REG_1 */
>  #define REF_CLK_24M                            (0x1 << 0)
>  #define REF_CLK_27M                            (0x0 << 0)
> +#define REF_CLK_MASK                           (0x1 << 0)
>
>  /* ANALOGIX_DP_LANE_MAP */
>  #define LANE3_MAP_LOGIC_LANE_0                 (0x0 << 6)
> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> index 3855f46..315ebba 100644
> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> @@ -46,6 +46,7 @@ struct rockchip_dp_chip_data {
>         u32     lcdsel_grf_reg;
>         u32     lcdsel_big;
>         u32     lcdsel_lit;
> +       u32     chip_type;
>  };
>
>  struct rockchip_dp_device {
> @@ -286,6 +287,7 @@ static int rockchip_dp_bind(struct device *dev, struct device *master,
>         dp->plat_data.encoder = &dp->encoder;
>
>         dp->plat_data.dev_type = ROCKCHIP_DP;
> +       dp->plat_data.subdev_type = dp_data->chip_type;
>         dp->plat_data.power_on = rockchip_dp_poweron;
>         dp->plat_data.power_off = rockchip_dp_powerdown;
>
> @@ -384,6 +386,7 @@ static const struct rockchip_dp_chip_data rk3288_dp = {
>         .lcdsel_grf_reg = 0x025c,
>         .lcdsel_big = 0 | BIT(21),
>         .lcdsel_lit = BIT(5) | BIT(21),
> +       .chip_type = RK3288_DP,
>  };
>
>  static const struct of_device_id rockchip_dp_dt_ids[] = {
> diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
> index 9e5d013..06c0250 100644
> --- a/include/drm/bridge/analogix_dp.h
> +++ b/include/drm/bridge/analogix_dp.h
> @@ -18,8 +18,13 @@ enum analogix_dp_devtype {
>         ROCKCHIP_DP,
>  };
>
> +enum analogix_dp_sub_devtype {
> +       RK3288_DP,
> +};
> +
>  struct analogix_dp_plat_data {
>         enum analogix_dp_devtype dev_type;
> +       enum analogix_dp_sub_devtype subdev_type;

So this is what I was talking about in my review of the first patch of
the series.

I don't personally think the dev and subdev types add any clarity
here, just more state. I'd prefer that you put the product number in
the top level devtype, and add a helper function like:

static bool is_rockchip(enum analogix_dp_devtype type) {
  return type == ... || type == ...
}

Sean

>         struct drm_panel *panel;
>         struct drm_encoder *encoder;
>         struct drm_connector *connector;
> --
> 1.9.1
>
>
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