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From: Alexandre Courbot <acourbot@chromium.org>
To: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Tiffany Lin <tiffany.lin@mediatek.com>,
	Andrew-CT Chen <andrew-ct.chen@mediatek.com>,
	Hans Verkuil <hverkuil-cisco@xs4all.nl>,
	Yunfei Dong <yunfei.dong@mediatek.com>,
	Maoguang Meng <maoguang.meng@mediatek.com>,
	Linux Media Mailing List <linux-media@vger.kernel.org>,
	"moderated list:ARM/Mediatek SoC support" 
	<linux-mediatek@lists.infradead.org>,
	devicetree <devicetree@vger.kernel.org>,
	LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v4 09/17] arm64: dts: mt8183: add encoder node
Date: Thu, 27 Aug 2020 19:29:35 +0900	[thread overview]
Message-ID: <CAPBb6MXrUNqWr=3KBPbJkXGmz=gL0aq_QuUQ5u_crR3yyDBvpw@mail.gmail.com> (raw)
In-Reply-To: <184d895c-239e-3f23-970e-6a9563235cd9@gmail.com>

Hi Matthias,

On Thu, Aug 27, 2020 at 7:23 PM Matthias Brugger <matthias.bgg@gmail.com> wrote:
>
> Hi Alexandre,
>
> On 27/08/2020 12:10, Alexandre Courbot wrote:
> > On Thu, Aug 27, 2020 at 7:03 PM Matthias Brugger <matthias.bgg@gmail.com> wrote:
> >>
> >>
> >>
> >> On 21/08/2020 12:36, Alexandre Courbot wrote:
> >>> Now that the MT8183 encoder driver is ready, add its DT node. Also pull
> >>> the iommu and scp ones, which the encoder depends upon.
> >>
> >> Please don't do that. Instead of pulling in other DT nodes, it would be handy to
> >> get a reference of the series this is based on.
> >>
> >> Let me try to hunt them down now :)
> >
> > Sorry, I'm not sure to understand - do you mean each node should come
> > with its own patch? Or that all the code should be merged before
> > sending these nodes? The rest of this series should land into the
> > media tree soon, if you prefer I can resend this patch separately once
> > that happens.
> >
>
> What I'm talking about is the case when you send a series that's based on
> another one and the latter is not yet accepted in Torvalds tree. In that case it
> helps to point to the series you expect to be included as well.
>
> In this case the SCP series was merged long time ago, but I missed the DTS
> change. It would have been good if you would have added that information in your
> series, instead of directly pulling in the SCP node.

Sorry about that, actually I was not even aware of this patch (or
maybe I just forgot about it due to its date).

>
> For the iommu node: I understand that there was never a patch adding the node
> (at least I wasn't able to find one). So I'd prefer to have it send as a
> separate patch of this series.
>
> Regarding this series now. If you want just resend the two DTS patches (iommu
> and vcodec_enc) once the rest of this series got accpeted. If for any other
> reason you have to send a v5, then feel free to include both in v5.

Absolutely. I will wait until the patches land into the media tree and
send you two DT-only patches.

Thanks for the explanation!

>
> Hope I explained myself now :)
>
> Regards,
> Matthias
>
> >>
> >> Regards,
> >> Matthias
> >>
> >>>
> >>> Signed-off-by: Alexandre Courbot <acourbot@chromium.org>
> >>> ---
> >>>    arch/arm64/boot/dts/mediatek/mt8183-evb.dts   | 10 ++++++
> >>>    .../arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 12 +++++++
> >>>    arch/arm64/boot/dts/mediatek/mt8183.dtsi      | 36 +++++++++++++++++++
> >>>    3 files changed, 58 insertions(+)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> >>> index ae405bd8f06b..9e77b420eee8 100644
> >>> --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> >>> +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> >>> @@ -25,6 +25,16 @@ memory@40000000 {
> >>>        chosen {
> >>>                stdout-path = "serial0:921600n8";
> >>>        };
> >>> +     reserved-memory {
> >>> +             #address-cells = <2>;
> >>> +             #size-cells = <2>;
> >>> +             ranges;
> >>> +             scp_mem_reserved: scp_mem_region {
> >>> +                     compatible = "shared-dma-pool";
> >>> +                     reg = <0 0x50000000 0 0x2900000>;
> >>> +                     no-map;
> >>> +             };
> >>> +     };
> >>>    };
> >>>
> >>>    &auxadc {
> >>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> >>> index f0a070535b34..3c763be658da 100644
> >>> --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> >>> +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> >>> @@ -90,6 +90,18 @@ pp3300_alw: regulator6 {
> >>>                regulator-max-microvolt = <3300000>;
> >>>        };
> >>>
> >>> +     reserved_memory: reserved-memory {
> >>> +             #address-cells = <2>;
> >>> +             #size-cells = <2>;
> >>> +             ranges;
> >>> +
> >>> +             scp_mem_reserved: scp_mem_region {
> >>> +                     compatible = "shared-dma-pool";
> >>> +                     reg = <0 0x50000000 0 0x2900000>;
> >>> +                     no-map;
> >>> +             };
> >>> +     };
> >>> +
> >>>        max98357a: codec0 {
> >>>                compatible = "maxim,max98357a";
> >>>                sdmode-gpios = <&pio 175 0>;
> >>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >>> index 102105871db2..8f77eea6df27 100644
> >>> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >>> @@ -8,6 +8,7 @@
> >>>    #include <dt-bindings/clock/mt8183-clk.h>
> >>>    #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>>    #include <dt-bindings/interrupt-controller/irq.h>
> >>> +#include <dt-bindings/memory/mt8183-larb-port.h>
> >>>    #include <dt-bindings/reset-controller/mt8183-resets.h>
> >>>    #include <dt-bindings/phy/phy.h>
> >>>    #include "mt8183-pinfunc.h"
> >>> @@ -339,6 +340,25 @@ pwrap: pwrap@1000d000 {
> >>>                        clock-names = "spi", "wrap";
> >>>                };
> >>>
> >>> +             iommu: iommu@10205000 {
> >>> +                     compatible = "mediatek,mt8183-m4u";
> >>> +                     reg = <0 0x10205000 0 0x1000>;
> >>> +                     interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
> >>> +                     #iommu-cells = <1>;
> >>> +             };
> >>> +
> >>> +             scp: scp@10500000 {
> >>> +                     compatible = "mediatek,mt8183-scp";
> >>> +                     reg = <0 0x10500000 0 0x80000>,
> >>> +                           <0 0x105c0000 0 0x19080>;
> >>> +                     reg-names = "sram", "cfg";
> >>> +                     interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
> >>> +                     clocks = <&infracfg CLK_INFRA_SCPSYS>;
> >>> +                     clock-names = "main";
> >>> +                     memory-region = <&scp_mem_reserved>;
> >>> +                     status = "disabled";
> >>> +             };
> >>> +
> >>>                systimer: timer@10017000 {
> >>>                        compatible = "mediatek,mt8183-timer",
> >>>                                     "mediatek,mt6765-timer";
> >>> @@ -772,6 +792,22 @@ vencsys: syscon@17000000 {
> >>>                        #clock-cells = <1>;
> >>>                };
> >>>
> >>> +             vcodec_enc: vcodec@17020000 {
> >>> +                     compatible = "mediatek,mt8183-vcodec-enc";
> >>> +                     reg = <0 0x17020000 0 0x1000>;
> >>> +                     interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_LOW>;
> >>> +                     iommus = <&iommu M4U_PORT_VENC_REC>,
> >>> +                              <&iommu M4U_PORT_VENC_BSDMA>,
> >>> +                              <&iommu M4U_PORT_VENC_RD_COMV>,
> >>> +                              <&iommu M4U_PORT_VENC_CUR_LUMA>,
> >>> +                              <&iommu M4U_PORT_VENC_CUR_CHROMA>,
> >>> +                              <&iommu M4U_PORT_VENC_REF_LUMA>,
> >>> +                              <&iommu M4U_PORT_VENC_REF_CHROMA>;
> >>> +                     mediatek,scp = <&scp>;
> >>> +                     clocks = <&vencsys CLK_VENC_VENC>;
> >>> +                     clock-names = "MT_CG_VENC";
> >>> +             };
> >>> +
> >>>                ipu_conn: syscon@19000000 {
> >>>                        compatible = "mediatek,mt8183-ipu_conn", "syscon";
> >>>                        reg = <0 0x19000000 0 0x1000>;
> >>>

WARNING: multiple messages have this Message-ID (diff)
From: Alexandre Courbot <acourbot@chromium.org>
To: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Andrew-CT Chen <andrew-ct.chen@mediatek.com>,
	Maoguang Meng <maoguang.meng@mediatek.com>,
	devicetree <devicetree@vger.kernel.org>,
	Yunfei Dong <yunfei.dong@mediatek.com>,
	LKML <linux-kernel@vger.kernel.org>,
	"moderated list:ARM/Mediatek SoC support"
	<linux-mediatek@lists.infradead.org>,
	Hans Verkuil <hverkuil-cisco@xs4all.nl>,
	Tiffany Lin <tiffany.lin@mediatek.com>,
	Linux Media Mailing List <linux-media@vger.kernel.org>
Subject: Re: [PATCH v4 09/17] arm64: dts: mt8183: add encoder node
Date: Thu, 27 Aug 2020 19:29:35 +0900	[thread overview]
Message-ID: <CAPBb6MXrUNqWr=3KBPbJkXGmz=gL0aq_QuUQ5u_crR3yyDBvpw@mail.gmail.com> (raw)
In-Reply-To: <184d895c-239e-3f23-970e-6a9563235cd9@gmail.com>

Hi Matthias,

On Thu, Aug 27, 2020 at 7:23 PM Matthias Brugger <matthias.bgg@gmail.com> wrote:
>
> Hi Alexandre,
>
> On 27/08/2020 12:10, Alexandre Courbot wrote:
> > On Thu, Aug 27, 2020 at 7:03 PM Matthias Brugger <matthias.bgg@gmail.com> wrote:
> >>
> >>
> >>
> >> On 21/08/2020 12:36, Alexandre Courbot wrote:
> >>> Now that the MT8183 encoder driver is ready, add its DT node. Also pull
> >>> the iommu and scp ones, which the encoder depends upon.
> >>
> >> Please don't do that. Instead of pulling in other DT nodes, it would be handy to
> >> get a reference of the series this is based on.
> >>
> >> Let me try to hunt them down now :)
> >
> > Sorry, I'm not sure to understand - do you mean each node should come
> > with its own patch? Or that all the code should be merged before
> > sending these nodes? The rest of this series should land into the
> > media tree soon, if you prefer I can resend this patch separately once
> > that happens.
> >
>
> What I'm talking about is the case when you send a series that's based on
> another one and the latter is not yet accepted in Torvalds tree. In that case it
> helps to point to the series you expect to be included as well.
>
> In this case the SCP series was merged long time ago, but I missed the DTS
> change. It would have been good if you would have added that information in your
> series, instead of directly pulling in the SCP node.

Sorry about that, actually I was not even aware of this patch (or
maybe I just forgot about it due to its date).

>
> For the iommu node: I understand that there was never a patch adding the node
> (at least I wasn't able to find one). So I'd prefer to have it send as a
> separate patch of this series.
>
> Regarding this series now. If you want just resend the two DTS patches (iommu
> and vcodec_enc) once the rest of this series got accpeted. If for any other
> reason you have to send a v5, then feel free to include both in v5.

Absolutely. I will wait until the patches land into the media tree and
send you two DT-only patches.

Thanks for the explanation!

>
> Hope I explained myself now :)
>
> Regards,
> Matthias
>
> >>
> >> Regards,
> >> Matthias
> >>
> >>>
> >>> Signed-off-by: Alexandre Courbot <acourbot@chromium.org>
> >>> ---
> >>>    arch/arm64/boot/dts/mediatek/mt8183-evb.dts   | 10 ++++++
> >>>    .../arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 12 +++++++
> >>>    arch/arm64/boot/dts/mediatek/mt8183.dtsi      | 36 +++++++++++++++++++
> >>>    3 files changed, 58 insertions(+)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> >>> index ae405bd8f06b..9e77b420eee8 100644
> >>> --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> >>> +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> >>> @@ -25,6 +25,16 @@ memory@40000000 {
> >>>        chosen {
> >>>                stdout-path = "serial0:921600n8";
> >>>        };
> >>> +     reserved-memory {
> >>> +             #address-cells = <2>;
> >>> +             #size-cells = <2>;
> >>> +             ranges;
> >>> +             scp_mem_reserved: scp_mem_region {
> >>> +                     compatible = "shared-dma-pool";
> >>> +                     reg = <0 0x50000000 0 0x2900000>;
> >>> +                     no-map;
> >>> +             };
> >>> +     };
> >>>    };
> >>>
> >>>    &auxadc {
> >>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> >>> index f0a070535b34..3c763be658da 100644
> >>> --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> >>> +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> >>> @@ -90,6 +90,18 @@ pp3300_alw: regulator6 {
> >>>                regulator-max-microvolt = <3300000>;
> >>>        };
> >>>
> >>> +     reserved_memory: reserved-memory {
> >>> +             #address-cells = <2>;
> >>> +             #size-cells = <2>;
> >>> +             ranges;
> >>> +
> >>> +             scp_mem_reserved: scp_mem_region {
> >>> +                     compatible = "shared-dma-pool";
> >>> +                     reg = <0 0x50000000 0 0x2900000>;
> >>> +                     no-map;
> >>> +             };
> >>> +     };
> >>> +
> >>>        max98357a: codec0 {
> >>>                compatible = "maxim,max98357a";
> >>>                sdmode-gpios = <&pio 175 0>;
> >>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >>> index 102105871db2..8f77eea6df27 100644
> >>> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >>> @@ -8,6 +8,7 @@
> >>>    #include <dt-bindings/clock/mt8183-clk.h>
> >>>    #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>>    #include <dt-bindings/interrupt-controller/irq.h>
> >>> +#include <dt-bindings/memory/mt8183-larb-port.h>
> >>>    #include <dt-bindings/reset-controller/mt8183-resets.h>
> >>>    #include <dt-bindings/phy/phy.h>
> >>>    #include "mt8183-pinfunc.h"
> >>> @@ -339,6 +340,25 @@ pwrap: pwrap@1000d000 {
> >>>                        clock-names = "spi", "wrap";
> >>>                };
> >>>
> >>> +             iommu: iommu@10205000 {
> >>> +                     compatible = "mediatek,mt8183-m4u";
> >>> +                     reg = <0 0x10205000 0 0x1000>;
> >>> +                     interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
> >>> +                     #iommu-cells = <1>;
> >>> +             };
> >>> +
> >>> +             scp: scp@10500000 {
> >>> +                     compatible = "mediatek,mt8183-scp";
> >>> +                     reg = <0 0x10500000 0 0x80000>,
> >>> +                           <0 0x105c0000 0 0x19080>;
> >>> +                     reg-names = "sram", "cfg";
> >>> +                     interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
> >>> +                     clocks = <&infracfg CLK_INFRA_SCPSYS>;
> >>> +                     clock-names = "main";
> >>> +                     memory-region = <&scp_mem_reserved>;
> >>> +                     status = "disabled";
> >>> +             };
> >>> +
> >>>                systimer: timer@10017000 {
> >>>                        compatible = "mediatek,mt8183-timer",
> >>>                                     "mediatek,mt6765-timer";
> >>> @@ -772,6 +792,22 @@ vencsys: syscon@17000000 {
> >>>                        #clock-cells = <1>;
> >>>                };
> >>>
> >>> +             vcodec_enc: vcodec@17020000 {
> >>> +                     compatible = "mediatek,mt8183-vcodec-enc";
> >>> +                     reg = <0 0x17020000 0 0x1000>;
> >>> +                     interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_LOW>;
> >>> +                     iommus = <&iommu M4U_PORT_VENC_REC>,
> >>> +                              <&iommu M4U_PORT_VENC_BSDMA>,
> >>> +                              <&iommu M4U_PORT_VENC_RD_COMV>,
> >>> +                              <&iommu M4U_PORT_VENC_CUR_LUMA>,
> >>> +                              <&iommu M4U_PORT_VENC_CUR_CHROMA>,
> >>> +                              <&iommu M4U_PORT_VENC_REF_LUMA>,
> >>> +                              <&iommu M4U_PORT_VENC_REF_CHROMA>;
> >>> +                     mediatek,scp = <&scp>;
> >>> +                     clocks = <&vencsys CLK_VENC_VENC>;
> >>> +                     clock-names = "MT_CG_VENC";
> >>> +             };
> >>> +
> >>>                ipu_conn: syscon@19000000 {
> >>>                        compatible = "mediatek,mt8183-ipu_conn", "syscon";
> >>>                        reg = <0 0x19000000 0 0x1000>;
> >>>

_______________________________________________
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  reply	other threads:[~2020-08-27 10:29 UTC|newest]

Thread overview: 60+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-21 10:35 [PATCH v4 00/17] media: mtk-vcodec: venc: support for MT8183 Alexandre Courbot
2020-08-21 10:35 ` Alexandre Courbot
2020-08-21 10:35 ` [PATCH v4 01/17] media: mtk-vcodec: abstract firmware interface Alexandre Courbot
2020-08-21 10:35   ` Alexandre Courbot
2020-08-21 10:35 ` [PATCH v4 02/17] dt-bindings: media: mtk-vcodec: document SCP node Alexandre Courbot
2020-08-21 10:35   ` Alexandre Courbot
2020-08-28 22:00   ` Rob Herring
2020-08-28 22:00     ` Rob Herring
2020-08-21 10:35 ` [PATCH v4 03/17] media: mtk-vcodec: add SCP firmware ops Alexandre Courbot
2020-08-21 10:35   ` Alexandre Courbot
2020-08-21 15:13   ` kernel test robot
2020-08-21 15:13     ` kernel test robot
2020-08-21 15:13     ` kernel test robot
2020-08-26  9:19     ` Alexandre Courbot
2020-08-26  9:19       ` Alexandre Courbot
2020-08-26  9:19       ` Alexandre Courbot
2020-08-21 10:35 ` [PATCH v4 04/17] media: mtk-vcodec: venc: support SCP firmware Alexandre Courbot
2020-08-21 10:35   ` Alexandre Courbot
2020-08-21 10:35 ` [PATCH v4 05/17] media: mtk-vcodec: venc: handle firmware version field Alexandre Courbot
2020-08-21 10:35   ` Alexandre Courbot
2020-08-21 10:35 ` [PATCH v4 06/17] media: mtk-vcodec: venc: specify bitrate range per-chip Alexandre Courbot
2020-08-21 10:35   ` Alexandre Courbot
2020-08-21 10:35 ` [PATCH v4 07/17] media: mtk-vcodec: venc: specify supported formats per-chip Alexandre Courbot
2020-08-21 10:35   ` Alexandre Courbot
2020-08-21 10:35 ` [PATCH v4 08/17] dt-bindings: media: document mediatek,mt8183-vcodec-enc Alexandre Courbot
2020-08-21 10:35   ` [PATCH v4 08/17] dt-bindings: media: document mediatek, mt8183-vcodec-enc Alexandre Courbot
2020-08-21 10:36 ` [PATCH v4 09/17] arm64: dts: mt8183: add encoder node Alexandre Courbot
2020-08-21 10:36   ` Alexandre Courbot
2020-08-27 10:03   ` Matthias Brugger
2020-08-27 10:03     ` Matthias Brugger
2020-08-27 10:10     ` Alexandre Courbot
2020-08-27 10:10       ` Alexandre Courbot
2020-08-27 10:23       ` Matthias Brugger
2020-08-27 10:23         ` Matthias Brugger
2020-08-27 10:29         ` Alexandre Courbot [this message]
2020-08-27 10:29           ` Alexandre Courbot
2020-08-21 10:36 ` [PATCH v4 10/17] media: mtk-vcodec: add support for MT8183 encoder Alexandre Courbot
2020-08-21 10:36   ` Alexandre Courbot
2020-08-21 10:36 ` [PATCH v4 11/17] Revert "media: mtk-vcodec: Remove extra area allocation in an input buffer on encoding" Alexandre Courbot
2020-08-21 10:36   ` Alexandre Courbot
2020-08-21 10:36 ` [PATCH v4 12/17] media: mtk-vcodec: venc support MIN_OUTPUT_BUFFERS control Alexandre Courbot
2020-08-21 10:36   ` Alexandre Courbot
2020-08-21 10:36 ` [PATCH v4 13/17] media: mtk-vcodec: venc: set OUTPUT buffers field to V4L2_FIELD_NONE Alexandre Courbot
2020-08-21 10:36   ` Alexandre Courbot
2020-08-21 10:36 ` [PATCH v4 14/17] media: mtk-vcodec: venc: use platform data for ENUM_FRAMESIZES Alexandre Courbot
2020-08-21 10:36   ` Alexandre Courbot
2020-08-25  5:39   ` Tiffany Lin
2020-08-25  5:39     ` Tiffany Lin
2020-08-21 10:36 ` [PATCH v4 15/17] media: mtk-vcodec: venc: support ENUM_FRAMESIZES on OUTPUT formats Alexandre Courbot
2020-08-21 10:36   ` Alexandre Courbot
2020-08-25  5:46   ` Tiffany Lin
2020-08-25  5:46     ` Tiffany Lin
2020-08-21 10:36 ` [PATCH v4 16/17] media: mtk-vcodec: venc: set default time per frame Alexandre Courbot
2020-08-21 10:36   ` Alexandre Courbot
2020-08-25  5:48   ` Tiffany Lin
2020-08-25  5:48     ` Tiffany Lin
2020-08-21 10:36 ` [PATCH v4 17/17] media: mtk-vcodec: venc: fix invalid time per frame in S_PARM Alexandre Courbot
2020-08-21 10:36   ` Alexandre Courbot
2020-08-25  5:49   ` Tiffany Lin
2020-08-25  5:49     ` Tiffany Lin

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