From: Ulf Hansson <ulf.hansson@linaro.org>
To: Shawn Guo <shawnguo@kernel.org>
Cc: Adrian Hunter <adrian.hunter@intel.com>,
Haibo Chen <haibo.chen@nxp.com>,
Dong Aisheng <aisheng.dong@nxp.com>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
NXP Linux Team <linux-imx@nxp.com>,
linux-mmc <linux-mmc@vger.kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
Shawn Guo <shawn.guo@linaro.org>
Subject: Re: [PATCH] mmc: sdhci-esdhc-imx: separate 100/200 MHz pinctrl states check
Date: Tue, 30 Mar 2021 12:44:41 +0200 [thread overview]
Message-ID: <CAPDyKFq2dQ3zpwgxeekHoBQyeKOOAr8aAM_7dRxasWt2fVgC5A@mail.gmail.com> (raw)
In-Reply-To: <20210326110214.28416-1-shawnguo@kernel.org>
On Fri, 26 Mar 2021 at 12:02, Shawn Guo <shawnguo@kernel.org> wrote:
>
> From: Shawn Guo <shawn.guo@linaro.org>
>
> As indicated by function esdhc_change_pinstate(), SDR50 and DDR50
> require pins_100mhz, while SDR104 and HS400 require pins_200mhz. Some
> system design may support SDR50 and DDR50 with 100mhz pin state only
> (without 200mhz one). Currently the combined 100/200 MHz pinctrl state
> check prevents such system from running SDR50 and DDR50. Separate the
> check to support such system design.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Applied for next, thanks!
Kind regards
Uffe
> ---
> drivers/mmc/host/sdhci-esdhc-imx.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
> index a20459744d21..aa45901325b9 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -434,10 +434,10 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
> * Do not advertise faster UHS modes if there are no
> * pinctrl states for 100MHz/200MHz.
> */
> - if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
> - IS_ERR_OR_NULL(imx_data->pins_200mhz))
> - val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
> - | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
> + if (IS_ERR_OR_NULL(imx_data->pins_100mhz))
> + val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
> + if (IS_ERR_OR_NULL(imx_data->pins_200mhz))
> + val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
> }
> }
>
> --
> 2.17.1
>
WARNING: multiple messages have this Message-ID (diff)
From: Ulf Hansson <ulf.hansson@linaro.org>
To: Shawn Guo <shawnguo@kernel.org>
Cc: Adrian Hunter <adrian.hunter@intel.com>,
Haibo Chen <haibo.chen@nxp.com>,
Dong Aisheng <aisheng.dong@nxp.com>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
NXP Linux Team <linux-imx@nxp.com>,
linux-mmc <linux-mmc@vger.kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
Shawn Guo <shawn.guo@linaro.org>
Subject: Re: [PATCH] mmc: sdhci-esdhc-imx: separate 100/200 MHz pinctrl states check
Date: Tue, 30 Mar 2021 12:44:41 +0200 [thread overview]
Message-ID: <CAPDyKFq2dQ3zpwgxeekHoBQyeKOOAr8aAM_7dRxasWt2fVgC5A@mail.gmail.com> (raw)
In-Reply-To: <20210326110214.28416-1-shawnguo@kernel.org>
On Fri, 26 Mar 2021 at 12:02, Shawn Guo <shawnguo@kernel.org> wrote:
>
> From: Shawn Guo <shawn.guo@linaro.org>
>
> As indicated by function esdhc_change_pinstate(), SDR50 and DDR50
> require pins_100mhz, while SDR104 and HS400 require pins_200mhz. Some
> system design may support SDR50 and DDR50 with 100mhz pin state only
> (without 200mhz one). Currently the combined 100/200 MHz pinctrl state
> check prevents such system from running SDR50 and DDR50. Separate the
> check to support such system design.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Applied for next, thanks!
Kind regards
Uffe
> ---
> drivers/mmc/host/sdhci-esdhc-imx.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
> index a20459744d21..aa45901325b9 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -434,10 +434,10 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
> * Do not advertise faster UHS modes if there are no
> * pinctrl states for 100MHz/200MHz.
> */
> - if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
> - IS_ERR_OR_NULL(imx_data->pins_200mhz))
> - val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
> - | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
> + if (IS_ERR_OR_NULL(imx_data->pins_100mhz))
> + val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
> + if (IS_ERR_OR_NULL(imx_data->pins_200mhz))
> + val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
> }
> }
>
> --
> 2.17.1
>
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-03-30 10:46 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-26 11:02 [PATCH] mmc: sdhci-esdhc-imx: separate 100/200 MHz pinctrl states check Shawn Guo
2021-03-26 11:02 ` Shawn Guo
2021-03-29 1:50 ` Bough Chen
2021-03-29 1:50 ` Bough Chen
2021-03-30 10:44 ` Ulf Hansson [this message]
2021-03-30 10:44 ` Ulf Hansson
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