From: "Paladugu, Siva Durga Prasad" <siva.durga.prasad.paladugu@amd.com>
To: "Simek, Michal" <michal.simek@amd.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"monstr@monstr.eu" <monstr@monstr.eu>,
"michal.simek@xilinx.com" <michal.simek@xilinx.com>,
"git@xilinx.com" <git@xilinx.com>
Cc: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>,
Andrew Davis <afd@ti.com>, Conor Dooley <conor+dt@kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
"Katakam, Harini" <harini.katakam@amd.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
Michael Grzeschik <m.grzeschik@pengutronix.de>,
Michael Tretter <m.tretter@pengutronix.de>,
"Gajjar, Parth" <parth.gajjar@amd.com>,
Piyush Mehta <piyush.mehta@xilinx.com>,
Rob Herring <robh+dt@kernel.org>,
Robert Hancock <robert.hancock@calian.com>,
Srinivas Neeli <srinivas.neeli@xilinx.com>,
"Shah, Tanmay" <tanmay.shah@amd.com>,
"Sagar, Vishal" <vishal.sagar@amd.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: RE: [PATCH] arm64: zynqmp: Switch to amd.com emails
Date: Wed, 17 May 2023 11:57:45 +0000 [thread overview]
Message-ID: <MW4PR12MB56676DB6C82A14A6A2451ED1917E9@MW4PR12MB5667.namprd12.prod.outlook.com> (raw)
In-Reply-To: <4c3426077075683b866f144b633cf5218a688c7c.1684244480.git.michal.simek@amd.com>
> -----Original Message-----
> From: Simek, Michal <michal.simek@amd.com>
> Sent: Tuesday, May 16, 2023 7:12 PM
> To: linux-kernel@vger.kernel.org; monstr@monstr.eu; michal.simek@xilinx.com;
> git@xilinx.com
> Cc: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>; Andrew Davis
> <afd@ti.com>; Conor Dooley <conor+dt@kernel.org>; Geert Uytterhoeven
> <geert+renesas@glider.be>; Katakam, Harini <harini.katakam@amd.com>;
> Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Laurent Pinchart
> <laurent.pinchart@ideasonboard.com>; Michael Grzeschik
> <m.grzeschik@pengutronix.de>; Michael Tretter <m.tretter@pengutronix.de>;
> Gajjar, Parth <parth.gajjar@amd.com>; Piyush Mehta
> <piyush.mehta@xilinx.com>; Rob Herring <robh+dt@kernel.org>; Robert
> Hancock <robert.hancock@calian.com>; Srinivas Neeli
> <srinivas.neeli@xilinx.com>; Shah, Tanmay <tanmay.shah@amd.com>; Sagar,
> Vishal <vishal.sagar@amd.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Subject: [PATCH] arm64: zynqmp: Switch to amd.com emails
>
> Update my and DPs email address to match current setup.
>
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
>
> arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 7 ++++---
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 7 ++++---
> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts | 7 ++++---
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 5 +++--
> 24 files changed, 51 insertions(+), 39 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
> b/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
> index 88aa06fa78a8..1495272e5668 100644
> --- a/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
> +++ b/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
> @@ -2,9 +2,10 @@
> /*
> * dts file for Avnet Ultra96 rev1
> *
> - * (C) Copyright 2018, Xilinx, Inc.
> + * (C) Copyright 2018 - 2022, Xilinx, Inc.
> + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> */
>
> /dts-v1/;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> index 719ea5d5ae88..f04716841a0c 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> @@ -5,7 +5,7 @@
> * (C) Copyright 2017 - 2022, Xilinx, Inc.
> * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> */
>
> #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> index bebbe955eec1..669fe6084f3f 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> @@ -9,7 +9,7 @@
> * "Y" - A01 board modified with legacy interposer (Nexperia)
> * "Z" - A01 board modified with Diode interposer
> *
> - * Michal Simek <michal.simek@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> */
>
> #include <dt-bindings/gpio/gpio.h>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> index 8e66448f35a9..7886a19139ee 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> @@ -4,7 +4,7 @@
> *
> * (C) Copyright 2020 - 2021, Xilinx, Inc.
> *
> - * Michal Simek <michal.simek@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> */
>
> #include <dt-bindings/gpio/gpio.h>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
> b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
> index 464e28bf078a..8d1c54e00556 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
> @@ -2,9 +2,10 @@
> /*
> * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
> *
> - * (C) Copyright 2020 - 2021, Xilinx, Inc.
> + * (C) Copyright 2020 - 2022, Xilinx, Inc.
> + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> */
>
> /dts-v1/;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts
> b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts
> index c70966c1f344..664ea7d99049 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts
> @@ -2,9 +2,10 @@
> /*
> * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A
> *
> - * (C) Copyright 2020 - 2021, Xilinx, Inc.
> + * (C) Copyright 2020 - 2022, Xilinx, Inc.
> + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> */
>
> #include "zynqmp-sm-k26-revA.dts"
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
> b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
> index f1598527e5ec..774fb773886e 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
> @@ -2,9 +2,10 @@
> /*
> * dts file for Xilinx ZynqMP ZC1232
> *
> - * (C) Copyright 2017 - 2021, Xilinx, Inc.
> + * (C) Copyright 2017 - 2022, Xilinx, Inc.
> + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> */
>
> /dts-v1/;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
> b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
> index 04efa1683eaa..7c27b0e9a522 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
> @@ -2,10 +2,11 @@
> /*
> * dts file for Xilinx ZynqMP ZC1254
> *
> - * (C) Copyright 2015 - 2021, Xilinx, Inc.
> + * (C) Copyright 2015 - 2022, Xilinx, Inc.
> + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xilinx.com>
> - * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> + * Siva Durga Prasad Paladug <siva.durga.prasad.paladugu@amd.com>
There is a typo in my name here and everywhere in the patch, Please fix this. Paladug -> Paladugu
Thanks,
DP
WARNING: multiple messages have this Message-ID (diff)
From: "Paladugu, Siva Durga Prasad" <siva.durga.prasad.paladugu@amd.com>
To: "Simek, Michal" <michal.simek@amd.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"monstr@monstr.eu" <monstr@monstr.eu>,
"michal.simek@xilinx.com" <michal.simek@xilinx.com>,
"git@xilinx.com" <git@xilinx.com>
Cc: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>,
Andrew Davis <afd@ti.com>, Conor Dooley <conor+dt@kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
"Katakam, Harini" <harini.katakam@amd.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
Michael Grzeschik <m.grzeschik@pengutronix.de>,
Michael Tretter <m.tretter@pengutronix.de>,
"Gajjar, Parth" <parth.gajjar@amd.com>,
Piyush Mehta <piyush.mehta@xilinx.com>,
Rob Herring <robh+dt@kernel.org>,
Robert Hancock <robert.hancock@calian.com>,
Srinivas Neeli <srinivas.neeli@xilinx.com>,
"Shah, Tanmay" <tanmay.shah@amd.com>,
"Sagar, Vishal" <vishal.sagar@amd.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: RE: [PATCH] arm64: zynqmp: Switch to amd.com emails
Date: Wed, 17 May 2023 11:57:45 +0000 [thread overview]
Message-ID: <MW4PR12MB56676DB6C82A14A6A2451ED1917E9@MW4PR12MB5667.namprd12.prod.outlook.com> (raw)
In-Reply-To: <4c3426077075683b866f144b633cf5218a688c7c.1684244480.git.michal.simek@amd.com>
> -----Original Message-----
> From: Simek, Michal <michal.simek@amd.com>
> Sent: Tuesday, May 16, 2023 7:12 PM
> To: linux-kernel@vger.kernel.org; monstr@monstr.eu; michal.simek@xilinx.com;
> git@xilinx.com
> Cc: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>; Andrew Davis
> <afd@ti.com>; Conor Dooley <conor+dt@kernel.org>; Geert Uytterhoeven
> <geert+renesas@glider.be>; Katakam, Harini <harini.katakam@amd.com>;
> Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Laurent Pinchart
> <laurent.pinchart@ideasonboard.com>; Michael Grzeschik
> <m.grzeschik@pengutronix.de>; Michael Tretter <m.tretter@pengutronix.de>;
> Gajjar, Parth <parth.gajjar@amd.com>; Piyush Mehta
> <piyush.mehta@xilinx.com>; Rob Herring <robh+dt@kernel.org>; Robert
> Hancock <robert.hancock@calian.com>; Srinivas Neeli
> <srinivas.neeli@xilinx.com>; Shah, Tanmay <tanmay.shah@amd.com>; Sagar,
> Vishal <vishal.sagar@amd.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Subject: [PATCH] arm64: zynqmp: Switch to amd.com emails
>
> Update my and DPs email address to match current setup.
>
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
>
> arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 7 ++++---
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 7 ++++---
> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts | 7 ++++---
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 5 +++--
> 24 files changed, 51 insertions(+), 39 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
> b/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
> index 88aa06fa78a8..1495272e5668 100644
> --- a/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
> +++ b/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
> @@ -2,9 +2,10 @@
> /*
> * dts file for Avnet Ultra96 rev1
> *
> - * (C) Copyright 2018, Xilinx, Inc.
> + * (C) Copyright 2018 - 2022, Xilinx, Inc.
> + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> */
>
> /dts-v1/;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> index 719ea5d5ae88..f04716841a0c 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> @@ -5,7 +5,7 @@
> * (C) Copyright 2017 - 2022, Xilinx, Inc.
> * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> */
>
> #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> index bebbe955eec1..669fe6084f3f 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> @@ -9,7 +9,7 @@
> * "Y" - A01 board modified with legacy interposer (Nexperia)
> * "Z" - A01 board modified with Diode interposer
> *
> - * Michal Simek <michal.simek@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> */
>
> #include <dt-bindings/gpio/gpio.h>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> index 8e66448f35a9..7886a19139ee 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> @@ -4,7 +4,7 @@
> *
> * (C) Copyright 2020 - 2021, Xilinx, Inc.
> *
> - * Michal Simek <michal.simek@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> */
>
> #include <dt-bindings/gpio/gpio.h>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
> b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
> index 464e28bf078a..8d1c54e00556 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
> @@ -2,9 +2,10 @@
> /*
> * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
> *
> - * (C) Copyright 2020 - 2021, Xilinx, Inc.
> + * (C) Copyright 2020 - 2022, Xilinx, Inc.
> + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> */
>
> /dts-v1/;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts
> b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts
> index c70966c1f344..664ea7d99049 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts
> @@ -2,9 +2,10 @@
> /*
> * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A
> *
> - * (C) Copyright 2020 - 2021, Xilinx, Inc.
> + * (C) Copyright 2020 - 2022, Xilinx, Inc.
> + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> */
>
> #include "zynqmp-sm-k26-revA.dts"
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
> b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
> index f1598527e5ec..774fb773886e 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
> @@ -2,9 +2,10 @@
> /*
> * dts file for Xilinx ZynqMP ZC1232
> *
> - * (C) Copyright 2017 - 2021, Xilinx, Inc.
> + * (C) Copyright 2017 - 2022, Xilinx, Inc.
> + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> */
>
> /dts-v1/;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
> b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
> index 04efa1683eaa..7c27b0e9a522 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
> @@ -2,10 +2,11 @@
> /*
> * dts file for Xilinx ZynqMP ZC1254
> *
> - * (C) Copyright 2015 - 2021, Xilinx, Inc.
> + * (C) Copyright 2015 - 2022, Xilinx, Inc.
> + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xilinx.com>
> - * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
> + * Michal Simek <michal.simek@amd.com>
> + * Siva Durga Prasad Paladug <siva.durga.prasad.paladugu@amd.com>
There is a typo in my name here and everywhere in the patch, Please fix this. Paladug -> Paladugu
Thanks,
DP
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next prev parent reply other threads:[~2023-05-17 11:57 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-16 13:41 [PATCH] arm64: zynqmp: Switch to amd.com emails Michal Simek
2023-05-16 13:41 ` Michal Simek
2023-05-16 16:05 ` Krzysztof Kozlowski
2023-05-16 16:05 ` Krzysztof Kozlowski
2023-05-16 17:20 ` Michal Simek
2023-05-16 17:20 ` Michal Simek
2023-05-16 17:25 ` Krzysztof Kozlowski
2023-05-16 17:25 ` Krzysztof Kozlowski
2023-05-17 11:57 ` Paladugu, Siva Durga Prasad [this message]
2023-05-17 11:57 ` Paladugu, Siva Durga Prasad
2023-07-10 12:35 Michal Simek
2023-07-17 9:10 ` Michal Simek
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