RE: [PATCH RFC 0/4] Add set_iofv() callback

From: Biju Das <biju.das.jz@bp.renesas.com>
To: Michael Walle <michael@walle.cc>
Cc: Mark Brown <broonie@kernel.org>,
	Miquel Raynal <miquel.raynal@bootlin.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	"linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
	"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	biju.das.au <biju.das.au@gmail.com>,
	"linux-renesas-soc@vger.kernel.org"
	<linux-renesas-soc@vger.kernel.org>
Subject: RE: [PATCH RFC 0/4] Add set_iofv() callback
Date: Thu, 9 Nov 2023 10:04:19 +0000	[thread overview]
Message-ID: <TYVPR01MB11279E535835F2998335F770A86AFA@TYVPR01MB11279.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <877590a5e3f8c32ec0a032385049a563@walle.cc>

Hi Michael Walle,

Thanks for the feedback.

> Subject: Re: [PATCH RFC 0/4] Add set_iofv() callback
> 
> Hi Biju,
> 
> > As per section 8.14 on the AT25QL128A hardware manual[1],
> > IO0..IO3 must be set to Hi-Z state for this flash for fast read quad
> > IO.
> > Snippet from HW manual section 8.14:
> > The upper nibble of the Mode(M7-4) controls the length of the next
> > FAST Read Quad IO instruction through the inclusion or exclusion of
> > the first byte instruction code. The lower nibble bits of the
> > Mode(M3-0) are don't care. However, the IO pins must be high-impedance
> > before the falling edge of the first data out clock.
> 
> I'm still not sure what you are trying to fix here. For any quad I/O mode,
> the pins of the controller must be in hiZ during the data phase on a read
> operation. Otherwise the flash couldn't send any data, there would be two
> drivers for one signal. So being in hiZ state should be the default and
> shouldn't depend on any connected flash.

OK, I will make hiZ state as the default.

> 
> You've mentioned the micron flash which needs a '1' on its hold/reset pin.
> I would have expected a fixup for this flash, not for the flash which
> behaves normal.

I will drop fixup for Renesas AT25QL128A  and will add fixup for micron flash.

Currently,

With iofv settings {3,3,3,3} (all pins on Hi-Z state) with Micron flash
-----------------------------------------------------------------------

./rpcif_t_001.sh
[   37.950986] spi-nor spi1.0: unrecognized JEDEC id bytes: ff ff ff ff ff ff

EXIT|FAIL|rpcif_t_001.sh|[00:00:01] Failed to detect mt25qu512a flash!||

With iofv settings {3,3,3,1} with Micron falsh
---------------------------------------------
root@smarc-rzg2l:/cip-test-scripts# ./rpcif_t_001.sh
[   26.500035] spi-nor spi1.0: mt25qu512a (65536 Kbytes)
[   26.533995] 2 fixed-partitions partitions found on MTD device spi1.0
[   26.540410] Creating 2 MTD partitions on "spi1.0":
[   26.545239] 0x000000000000-0x000002000000 : "boot"
[   26.554381] 0x000002000000-0x000004000000 : "user"

EXIT|PASS|rpcif_t_001.sh|[00:03:01] ||

Cheers,
Biju

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