From: Ziyang Huang <hzyitc@outlook.com> To: Andrew Lunn <andrew@lunn.ch> Cc: mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, richardcochran@gmail.com, p.zabel@pengutronix.de, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: Re: [PATCH 7/8] arm64: dts: qcom: ipq5018: enable ethernet support Date: Mon, 22 Jan 2024 23:52:30 +0800 [thread overview] Message-ID: <TYZPR01MB5556603EA4C5D7BAF9C27C6AC9752@TYZPR01MB5556.apcprd01.prod.exchangelabs.com> (raw) In-Reply-To: <b8510b38-3669-4a04-9ca6-dbe937ecbec3@lunn.ch> 在 2024/1/22 0:45, Andrew Lunn 写道: > On Sun, Jan 21, 2024 at 08:42:36PM +0800, Ziyang Huang wrote: >> Signed-off-by: Ziyang Huang <hzyitc@outlook.com> >> --- >> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 120 +++++++++++++++++++++++++- >> 1 file changed, 116 insertions(+), 4 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi >> index e502a3ecf4b7..b36e5c2136b7 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi >> @@ -94,6 +94,63 @@ soc: soc@0 { >> #size-cells = <1>; >> ranges = <0 0 0 0xffffffff>; >> >> + mdio0: mdio@88000 { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + compatible = "qcom,ipq5018-mdio", "qcom,qca-mdio"; >> + reg = <0x88000 0x64>; >> + resets = <&gcc GCC_GEPHY_MDC_SW_ARES>, >> + <&gcc GCC_GEPHY_DSP_HW_ARES>; > > What do these two resets do? An MDIO bus controller is unlikely to > have a DSP in it. That is something a PHY is more likely to have. An > MDIO bus controller does have an MDC line, but why is it > GCC_GEPHY_MDC_SW_ARES not GCC_MDIO_MDC_SW_ARES? So this again makes me > think this is a PHY reset, so should be in the PHY node. > IPQ5018 has two mdio bus. mdio0 is an internal bus which only connects to internal PHY while mdio1 is outgoing and can be used to connect PHY or switch. So I thought GCC_GEPHY_MDC_SW_ARES is for mdio0 and GCC_MDIO_MDC_SW_ARES is for mdio1. GCC_GEPHY_DSP_HW_ARES is seem like PHY reset. But if we don't deassert it, the phy node can't be scaned. So I add it here like what reset-gpios do - to reset PHY or switch. > A device tree binding will help sort this out. Base on the functions I explained, I can't write the accurate names and number of resets here. > > > Andrew > > --- > pw-bot: cr
WARNING: multiple messages have this Message-ID (diff)
From: Ziyang Huang <hzyitc@outlook.com> To: Andrew Lunn <andrew@lunn.ch> Cc: mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, richardcochran@gmail.com, p.zabel@pengutronix.de, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: Re: [PATCH 7/8] arm64: dts: qcom: ipq5018: enable ethernet support Date: Mon, 22 Jan 2024 23:52:30 +0800 [thread overview] Message-ID: <TYZPR01MB5556603EA4C5D7BAF9C27C6AC9752@TYZPR01MB5556.apcprd01.prod.exchangelabs.com> (raw) In-Reply-To: <b8510b38-3669-4a04-9ca6-dbe937ecbec3@lunn.ch> 在 2024/1/22 0:45, Andrew Lunn 写道: > On Sun, Jan 21, 2024 at 08:42:36PM +0800, Ziyang Huang wrote: >> Signed-off-by: Ziyang Huang <hzyitc@outlook.com> >> --- >> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 120 +++++++++++++++++++++++++- >> 1 file changed, 116 insertions(+), 4 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi >> index e502a3ecf4b7..b36e5c2136b7 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi >> @@ -94,6 +94,63 @@ soc: soc@0 { >> #size-cells = <1>; >> ranges = <0 0 0 0xffffffff>; >> >> + mdio0: mdio@88000 { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + compatible = "qcom,ipq5018-mdio", "qcom,qca-mdio"; >> + reg = <0x88000 0x64>; >> + resets = <&gcc GCC_GEPHY_MDC_SW_ARES>, >> + <&gcc GCC_GEPHY_DSP_HW_ARES>; > > What do these two resets do? An MDIO bus controller is unlikely to > have a DSP in it. That is something a PHY is more likely to have. An > MDIO bus controller does have an MDC line, but why is it > GCC_GEPHY_MDC_SW_ARES not GCC_MDIO_MDC_SW_ARES? So this again makes me > think this is a PHY reset, so should be in the PHY node. > IPQ5018 has two mdio bus. mdio0 is an internal bus which only connects to internal PHY while mdio1 is outgoing and can be used to connect PHY or switch. So I thought GCC_GEPHY_MDC_SW_ARES is for mdio0 and GCC_MDIO_MDC_SW_ARES is for mdio1. GCC_GEPHY_DSP_HW_ARES is seem like PHY reset. But if we don't deassert it, the phy node can't be scaned. So I add it here like what reset-gpios do - to reset PHY or switch. > A device tree binding will help sort this out. Base on the functions I explained, I can't write the accurate names and number of resets here. > > > Andrew > > --- > pw-bot: cr _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2024-01-22 15:53 UTC|newest] Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-01-21 12:40 [PATCH 0/8] ipq5018: enable ethernet support Ziyang Huang 2024-01-21 12:40 ` Ziyang Huang 2024-01-21 12:42 ` [PATCH 1/8] net: phy: Introduce Qualcomm IPQ5018 internal PHY driver Ziyang Huang 2024-01-21 12:42 ` Ziyang Huang 2024-01-21 16:19 ` Andrew Lunn 2024-01-21 16:19 ` Andrew Lunn 2024-01-22 15:37 ` Ziyang Huang 2024-01-22 15:37 ` Ziyang Huang 2024-01-22 17:18 ` Andrew Lunn 2024-01-22 17:18 ` Andrew Lunn 2024-01-23 15:38 ` Ziyang Huang 2024-01-23 15:38 ` Ziyang Huang 2024-01-23 23:15 ` Andrew Lunn 2024-01-23 23:15 ` Andrew Lunn 2024-01-21 12:42 ` [PATCH 2/8] phy: Introduce Qualcomm ethernet uniphy driver Ziyang Huang 2024-01-21 12:42 ` Ziyang Huang 2024-01-23 15:58 ` Ziyang Huang 2024-01-23 15:58 ` Ziyang Huang 2024-01-23 23:25 ` Andrew Lunn 2024-01-23 23:25 ` Andrew Lunn 2024-01-21 12:42 ` [PATCH 3/8] net: stmmac: Introduce Qualcomm IPQ50xx DWMAC driver Ziyang Huang 2024-01-21 12:42 ` Ziyang Huang 2024-01-24 5:54 ` kernel test robot 2024-01-24 5:54 ` kernel test robot 2024-01-24 9:40 ` kernel test robot 2024-01-24 9:40 ` kernel test robot 2024-01-21 12:42 ` [PATCH 4/8] clk: qcom: gcc-ipq5018: correct gcc_gmac0_sys_clk reg Ziyang Huang 2024-01-21 12:42 ` Ziyang Huang 2024-01-21 16:28 ` Andrew Lunn 2024-01-21 16:28 ` Andrew Lunn 2024-01-22 15:39 ` Ziyang Huang 2024-01-22 15:39 ` Ziyang Huang 2024-01-21 12:42 ` [PATCH 5/8] clk: qcom: support for duplicate freq in RCG2 freq table Ziyang Huang 2024-01-21 12:42 ` Ziyang Huang 2024-01-21 16:57 ` Andrew Lunn 2024-01-21 16:57 ` Andrew Lunn 2024-01-22 16:35 ` Ziyang Huang 2024-01-22 16:35 ` Ziyang Huang 2024-01-22 17:34 ` Andrew Lunn 2024-01-22 17:34 ` Andrew Lunn 2024-01-23 15:43 ` Ziyang Huang 2024-01-23 15:43 ` Ziyang Huang 2024-01-22 7:55 ` Krzysztof Kozlowski 2024-01-22 7:55 ` Krzysztof Kozlowski 2024-01-22 14:48 ` Ziyang Huang 2024-01-22 14:48 ` Ziyang Huang 2024-01-21 12:42 ` [PATCH 6/8] net: mdio: ipq4019: support reset control Ziyang Huang 2024-01-21 12:42 ` Ziyang Huang 2024-01-21 16:35 ` Andrew Lunn 2024-01-21 16:35 ` Andrew Lunn 2024-01-22 15:52 ` Ziyang Huang 2024-01-22 15:52 ` Ziyang Huang 2024-01-21 12:42 ` [PATCH 7/8] arm64: dts: qcom: ipq5018: enable ethernet support Ziyang Huang 2024-01-21 12:42 ` Ziyang Huang 2024-01-21 16:45 ` Andrew Lunn 2024-01-21 16:45 ` Andrew Lunn 2024-01-22 15:52 ` Ziyang Huang [this message] 2024-01-22 15:52 ` Ziyang Huang 2024-01-22 17:27 ` Andrew Lunn 2024-01-22 17:27 ` Andrew Lunn 2024-01-21 12:42 ` [PATCH 8/8] arm64: dts: qcom: ipq5018-rdp432-c2: " Ziyang Huang 2024-01-21 12:42 ` Ziyang Huang 2024-01-22 7:54 ` Krzysztof Kozlowski 2024-01-22 7:54 ` Krzysztof Kozlowski 2024-01-24 0:53 ` kernel test robot 2024-01-24 0:53 ` kernel test robot 2024-01-21 15:51 ` [PATCH 0/8] ipq5018: " Andrew Lunn 2024-01-21 15:51 ` Andrew Lunn 2024-01-22 14:45 ` Ziyang Huang 2024-01-22 14:45 ` Ziyang Huang
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