From: Mark Brown <broonie@kernel.org>
To: Daniel Beer <daniel.beer@igorinstitute.com>
Cc: alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org,
Andy Liu <andy-liu@ti.com>
Subject: Re: [PATCH v3 2/2] ASoC: tas5805m: add missing page switch.
Date: Mon, 6 Feb 2023 21:14:34 +0000 [thread overview]
Message-ID: <Y+FtutYjJFlrFtvP@sirena.org.uk> (raw)
In-Reply-To: <20230206204546.GA233871@nyquist.nev>
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On Tue, Feb 07, 2023 at 09:45:46AM +1300, Daniel Beer wrote:
> We did discuss this a while back when the driver first went in.
> Unfortunately the vendor software tools provide configuration for the
> part in the form of a sequence of raw register writes, including
> explicit page changes:
> https://lore.kernel.org/lkml/Yd85bjKEX9JnoOlI@sirena.org.uk/
That seems surmountable, either bypassing regmap or parsing the
configuration files.
> Aside from this, I have two other practical issues.
> The first is that I'm not sure how exactly to implement the paging
> scheme in terms of regmap_range_cfg (assuming this is what you're
> referring to). This chip has multi-level paging (books/pages), with the
> book selection register itself requiring paging to access. A sequence of
That's absolutely fine, this isn't the first device which has such a
setup and the code handles nested windows fine.
> Secondly, the patches as submitted here have been tested, but I don't
> currently have access to hardware. I'm very hesitant to make a
> significant change without retesting and leave the driver in a broken
> state again.
Presumably someone does given that the problem was noticed?
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WARNING: multiple messages have this Message-ID (diff)
From: Mark Brown <broonie@kernel.org>
To: Daniel Beer <daniel.beer@igorinstitute.com>
Cc: Andy Liu <andy-liu@ti.com>,
alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 2/2] ASoC: tas5805m: add missing page switch.
Date: Mon, 6 Feb 2023 21:14:34 +0000 [thread overview]
Message-ID: <Y+FtutYjJFlrFtvP@sirena.org.uk> (raw)
In-Reply-To: <20230206204546.GA233871@nyquist.nev>
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On Tue, Feb 07, 2023 at 09:45:46AM +1300, Daniel Beer wrote:
> We did discuss this a while back when the driver first went in.
> Unfortunately the vendor software tools provide configuration for the
> part in the form of a sequence of raw register writes, including
> explicit page changes:
> https://lore.kernel.org/lkml/Yd85bjKEX9JnoOlI@sirena.org.uk/
That seems surmountable, either bypassing regmap or parsing the
configuration files.
> Aside from this, I have two other practical issues.
> The first is that I'm not sure how exactly to implement the paging
> scheme in terms of regmap_range_cfg (assuming this is what you're
> referring to). This chip has multi-level paging (books/pages), with the
> book selection register itself requiring paging to access. A sequence of
That's absolutely fine, this isn't the first device which has such a
setup and the code handles nested windows fine.
> Secondly, the patches as submitted here have been tested, but I don't
> currently have access to hardware. I'm very hesitant to make a
> significant change without retesting and leave the driver in a broken
> state again.
Presumably someone does given that the problem was noticed?
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next prev parent reply other threads:[~2023-02-06 21:14 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-04 7:55 [PATCH v3 0/2] Two bug fixes for tas5805m codec driver Daniel Beer
2023-02-04 7:55 ` Daniel Beer
2022-10-27 8:28 ` [PATCH v3 1/2] ASoC: tas5805m: rework to avoid scheduling while atomic Daniel Beer
2022-10-27 8:28 ` Daniel Beer
2022-10-27 8:38 ` [PATCH v3 2/2] ASoC: tas5805m: add missing page switch Daniel Beer
2022-10-27 8:38 ` Daniel Beer
2023-02-06 13:11 ` Mark Brown
2023-02-06 13:11 ` Mark Brown
2023-02-06 20:45 ` Daniel Beer
2023-02-06 20:45 ` Daniel Beer
2023-02-06 21:14 ` Mark Brown [this message]
2023-02-06 21:14 ` Mark Brown
2023-02-06 21:37 ` [PATCH v3 0/2] Two bug fixes for tas5805m codec driver Mark Brown
2023-02-06 21:37 ` Mark Brown
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