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From: Wolfram Sang <wsa@kernel.org>
To: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Magnus Damm <magnus.damm@gmail.com>,
	Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
	linux-renesas-soc@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] arm64: dts: renesas: r8a779g0: Fix HSCIF0 "brg_int" clock
Date: Mon, 10 Oct 2022 09:55:57 +0200	[thread overview]
Message-ID: <Y0PQDVzGj8O4oZZY@shikoro> (raw)
In-Reply-To: <a5bd4148f92806f7c8e577d383370f810315f586.1665155947.git.geert+renesas@glider.be>

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On Fri, Oct 07, 2022 at 05:20:03PM +0200, Geert Uytterhoeven wrote:
> As serial communication requires a clock signal, the High Speed Serial
> Communication Interfaces with FIFO (HSCIF) are clocked by a clock that
> is not affected by Spread Spectrum or Fractional Multiplication.
> 
> Hence change the clock input for the HSCIF0 Baud Rate Generator internal
> clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the
> same clock rate), cfr. R-Car V4H Hardware User's Manual rev. 0.54.
> 
> Fixes: 987da486d84a5643 ("arm64: dts: renesas: Add Renesas R8A779G0 SoC support")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Do we need to wait for the clarification about the docs mentioned in
another thread?


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WARNING: multiple messages have this Message-ID (diff)
From: Wolfram Sang <wsa@kernel.org>
To: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Magnus Damm <magnus.damm@gmail.com>,
	Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
	linux-renesas-soc@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] arm64: dts: renesas: r8a779g0: Fix HSCIF0 "brg_int" clock
Date: Mon, 10 Oct 2022 09:55:57 +0200	[thread overview]
Message-ID: <Y0PQDVzGj8O4oZZY@shikoro> (raw)
In-Reply-To: <a5bd4148f92806f7c8e577d383370f810315f586.1665155947.git.geert+renesas@glider.be>


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On Fri, Oct 07, 2022 at 05:20:03PM +0200, Geert Uytterhoeven wrote:
> As serial communication requires a clock signal, the High Speed Serial
> Communication Interfaces with FIFO (HSCIF) are clocked by a clock that
> is not affected by Spread Spectrum or Fractional Multiplication.
> 
> Hence change the clock input for the HSCIF0 Baud Rate Generator internal
> clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the
> same clock rate), cfr. R-Car V4H Hardware User's Manual rev. 0.54.
> 
> Fixes: 987da486d84a5643 ("arm64: dts: renesas: Add Renesas R8A779G0 SoC support")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Do we need to wait for the clarification about the docs mentioned in
another thread?


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  reply	other threads:[~2022-10-10  7:56 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-07 15:20 [PATCH] arm64: dts: renesas: r8a779g0: Fix HSCIF0 "brg_int" clock Geert Uytterhoeven
2022-10-07 15:20 ` Geert Uytterhoeven
2022-10-10  7:55 ` Wolfram Sang [this message]
2022-10-10  7:55   ` Wolfram Sang
2022-10-10 11:12   ` Geert Uytterhoeven
2022-10-10 11:12     ` Geert Uytterhoeven

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