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From: "Russell King (Oracle)" <linux@armlinux.org.uk>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: "Pali Rohár" <pali@kernel.org>,
	"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Marek Behún" <kabel@kernel.org>,
	linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 04/15] PCI: mvebu: Handle invalid size of read config request
Date: Fri, 7 Jan 2022 19:15:26 +0000	[thread overview]
Message-ID: <YdiRTjGGWelHZ9rA@shell.armlinux.org.uk> (raw)
In-Reply-To: <20220107184548.GA390934@bhelgaas>

On Fri, Jan 07, 2022 at 12:45:48PM -0600, Bjorn Helgaas wrote:
> On Thu, Nov 25, 2021 at 01:45:54PM +0100, Pali Rohár wrote:
> > Function mvebu_pcie_hw_rd_conf() does not handle invalid size. So correctly
> > set read value to all-ones and return appropriate error return value
> > PCIBIOS_BAD_REGISTER_NUMBER like in mvebu_pcie_hw_wr_conf() function.
> > 
> > Signed-off-by: Pali Rohár <pali@kernel.org>
> > Cc: stable@vger.kernel.org
> 
> Is there a bug that this fixes?  If not, I would drop the stable tag
> (as I see Lorenzo already did, thanks!).
> 
> > ---
> >  drivers/pci/controller/pci-mvebu.c | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
> > index 08274132cdfb..19c6ee298442 100644
> > --- a/drivers/pci/controller/pci-mvebu.c
> > +++ b/drivers/pci/controller/pci-mvebu.c
> > @@ -261,6 +261,9 @@ static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
> >  	case 4:
> >  		*val = readl_relaxed(conf_data);
> >  		break;
> > +	default:
> > +		*val = 0xffffffff;
> > +		return PCIBIOS_BAD_REGISTER_NUMBER;
> 
> Might be the right thing to do, but there are many config accessors
> that do not set *val to ~0 before returning
> PCIBIOS_BAD_REGISTER_NUMBER:

I think a better question would be - how can this function be called
with a size that isn't 1, 2 or 4? I suppose if someone were to add
another PCI_OP_READ/PCI_OP_WRITE. However... they really need to audit
every implementation if they do that.

The generic implementation does this:

        if (size == 1)
                *val = readb(addr);
        else if (size == 2)
                *val = readw(addr);
        else
                *val = readl(addr);

and therefore completely ignores the size if it isn't 1 or 2. So I
don't think this is something that needs fixing.

If we're going to fix this in drivers, shouldn't we fix the generic
implementation too?

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

WARNING: multiple messages have this Message-ID (diff)
From: "Russell King (Oracle)" <linux@armlinux.org.uk>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: "Pali Rohár" <pali@kernel.org>,
	"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Marek Behún" <kabel@kernel.org>,
	linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 04/15] PCI: mvebu: Handle invalid size of read config request
Date: Fri, 7 Jan 2022 19:15:26 +0000	[thread overview]
Message-ID: <YdiRTjGGWelHZ9rA@shell.armlinux.org.uk> (raw)
In-Reply-To: <20220107184548.GA390934@bhelgaas>

On Fri, Jan 07, 2022 at 12:45:48PM -0600, Bjorn Helgaas wrote:
> On Thu, Nov 25, 2021 at 01:45:54PM +0100, Pali Rohár wrote:
> > Function mvebu_pcie_hw_rd_conf() does not handle invalid size. So correctly
> > set read value to all-ones and return appropriate error return value
> > PCIBIOS_BAD_REGISTER_NUMBER like in mvebu_pcie_hw_wr_conf() function.
> > 
> > Signed-off-by: Pali Rohár <pali@kernel.org>
> > Cc: stable@vger.kernel.org
> 
> Is there a bug that this fixes?  If not, I would drop the stable tag
> (as I see Lorenzo already did, thanks!).
> 
> > ---
> >  drivers/pci/controller/pci-mvebu.c | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
> > index 08274132cdfb..19c6ee298442 100644
> > --- a/drivers/pci/controller/pci-mvebu.c
> > +++ b/drivers/pci/controller/pci-mvebu.c
> > @@ -261,6 +261,9 @@ static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
> >  	case 4:
> >  		*val = readl_relaxed(conf_data);
> >  		break;
> > +	default:
> > +		*val = 0xffffffff;
> > +		return PCIBIOS_BAD_REGISTER_NUMBER;
> 
> Might be the right thing to do, but there are many config accessors
> that do not set *val to ~0 before returning
> PCIBIOS_BAD_REGISTER_NUMBER:

I think a better question would be - how can this function be called
with a size that isn't 1, 2 or 4? I suppose if someone were to add
another PCI_OP_READ/PCI_OP_WRITE. However... they really need to audit
every implementation if they do that.

The generic implementation does this:

        if (size == 1)
                *val = readb(addr);
        else if (size == 2)
                *val = readw(addr);
        else
                *val = readl(addr);

and therefore completely ignores the size if it isn't 1 or 2. So I
don't think this is something that needs fixing.

If we're going to fix this in drivers, shouldn't we fix the generic
implementation too?

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2022-01-07 19:15 UTC|newest]

Thread overview: 72+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-25 12:45 [PATCH 00/15] pci: mvebu: Various fixes Pali Rohár
2021-11-25 12:45 ` Pali Rohár
2021-11-25 12:45 ` [PATCH 01/15] PCI: mvebu: Check for valid ports Pali Rohár
2021-11-25 12:45   ` Pali Rohár
2021-11-25 12:45 ` [PATCH 02/15] PCI: mvebu: Check for errors from pci_bridge_emul_init() call Pali Rohár
2021-11-25 12:45   ` Pali Rohár
2021-11-25 12:45 ` [PATCH 03/15] PCI: mvebu: Check that PCI bridge specified in DT has function number zero Pali Rohár
2021-11-25 12:45   ` Pali Rohár
2022-01-07 18:15   ` Bjorn Helgaas
2022-01-07 18:15     ` Bjorn Helgaas
2022-01-07 18:18     ` Pali Rohár
2022-01-07 18:18       ` Pali Rohár
2022-01-07 21:09       ` Bjorn Helgaas
2022-01-07 21:09         ` Bjorn Helgaas
2022-01-07 21:58         ` Pali Rohár
2022-01-07 21:58           ` Pali Rohár
2021-11-25 12:45 ` [PATCH 04/15] PCI: mvebu: Handle invalid size of read config request Pali Rohár
2021-11-25 12:45   ` Pali Rohár
2022-01-07 18:45   ` Bjorn Helgaas
2022-01-07 18:45     ` Bjorn Helgaas
2022-01-07 19:15     ` Russell King (Oracle) [this message]
2022-01-07 19:15       ` Russell King (Oracle)
2021-11-25 12:45 ` [PATCH 05/15] PCI: mvebu: Disallow mapping interrupts on emulated bridges Pali Rohár
2021-11-25 12:45   ` Pali Rohár
2022-01-07 21:32   ` Bjorn Helgaas
2022-01-07 21:32     ` Bjorn Helgaas
2022-01-07 22:13     ` Pali Rohár
2022-01-07 22:13       ` Pali Rohár
2022-01-07 23:01       ` Bjorn Helgaas
2022-01-07 23:01         ` Bjorn Helgaas
2022-01-07 23:11         ` Pali Rohár
2022-01-07 23:11           ` Pali Rohár
2021-11-25 12:45 ` [PATCH 06/15] PCI: mvebu: Fix support for bus mastering and PCI_COMMAND on emulated bridge Pali Rohár
2021-11-25 12:45   ` Pali Rohár
2021-11-25 12:45 ` [PATCH 07/15] PCI: mvebu: Do not modify PCI IO type bits in conf_write Pali Rohár
2021-11-25 12:45   ` Pali Rohár
2021-11-25 12:45 ` [PATCH 08/15] PCI: mvebu: Propagate errors when updating PCI_IO_BASE and PCI_MEM_BASE registers Pali Rohár
2021-11-25 12:45   ` Pali Rohár
2022-01-07 21:55   ` Bjorn Helgaas
2022-01-07 21:55     ` Bjorn Helgaas
2022-01-07 22:28     ` Pali Rohár
2022-01-07 22:28       ` Pali Rohár
2022-01-07 23:16       ` Bjorn Helgaas
2022-01-07 23:16         ` Bjorn Helgaas
2022-01-07 23:46         ` Pali Rohár
2022-01-07 23:46           ` Pali Rohár
2022-01-13  0:19           ` Bjorn Helgaas
2022-01-13  0:19             ` Bjorn Helgaas
2022-01-13 10:35             ` Pali Rohár
2022-01-13 10:35               ` Pali Rohár
2022-01-20 17:50               ` Bjorn Helgaas
2022-01-20 17:50                 ` Bjorn Helgaas
2022-01-20 19:08                 ` Pali Rohár
2022-01-20 19:08                   ` Pali Rohár
2022-01-20 19:37                   ` Bjorn Helgaas
2022-01-20 19:37                     ` Bjorn Helgaas
2021-11-25 12:45 ` [PATCH 09/15] PCI: mvebu: Setup PCIe controller to Root Complex mode Pali Rohár
2021-11-25 12:45   ` Pali Rohár
2021-11-25 12:46 ` [PATCH 10/15] PCI: mvebu: Set PCI Bridge Class Code to PCI Bridge Pali Rohár
2021-11-25 12:46   ` Pali Rohár
2021-11-25 12:46 ` [PATCH 11/15] PCI: mvebu: Fix configuring secondary bus of PCIe Root Port via emulated bridge Pali Rohár
2021-11-25 12:46   ` Pali Rohár
2021-11-25 12:46 ` [PATCH 12/15] PCI: mvebu: Fix support for PCI_BRIDGE_CTL_BUS_RESET on " Pali Rohár
2021-11-25 12:46   ` Pali Rohár
2021-11-25 12:46 ` [PATCH 13/15] PCI: mvebu: Fix support for PCI_EXP_DEVCTL " Pali Rohár
2021-11-25 12:46   ` Pali Rohár
2021-11-25 12:46 ` [PATCH 14/15] PCI: mvebu: Fix support for PCI_EXP_RTSTA " Pali Rohár
2021-11-25 12:46   ` Pali Rohár
2021-11-25 12:46 ` [PATCH 15/15] PCI: mvebu: Fix support for DEVCAP2, DEVCTL2 and LNKCTL2 registers " Pali Rohár
2021-11-25 12:46   ` Pali Rohár
2022-01-04 15:04 ` [PATCH 00/15] pci: mvebu: Various fixes Lorenzo Pieralisi
2022-01-04 15:04   ` Lorenzo Pieralisi

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