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From: Mark Brown <broonie@kernel.org>
To: "Amadeusz Sławiński" <amadeuszx.slawinski@linux.intel.com>
Cc: Cezary Rojewski <cezary.rojewski@intel.com>,
	upstream@semihalf.com, harshapriya.n@intel.com,
	peter.ujfalusi@linux.intel.com, rad@semihalf.com,
	alsa-devel@alsa-project.org,
	pierre-louis.bossart@linux.intel.com, hdegoede@redhat.com,
	ranjani.sridharan@linux.intel.com, tiwai@suse.com,
	yung-chuan.liao@linux.intel.com, cujomalainey@chromium.org,
	lma@semihalf.com
Subject: Re: [RFC 00/37] ASoC: Intel: AVS - Audio DSP for cAVS
Date: Wed, 2 Feb 2022 16:08:14 +0000	[thread overview]
Message-ID: <YfqsbnroVj8ln66g@sirena.org.uk> (raw)
In-Reply-To: <7695fc34-143d-7715-85cb-7790386bbacc@linux.intel.com>

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On Wed, Feb 02, 2022 at 02:26:01PM +0100, Amadeusz Sławiński wrote:

> Although Cezary wrote that avs_path_reset/_pause/_run maps nicely to trigger
> operation it's not direct mapping. AVS FW has requirements on order of
> operations on pipelines (which are grouped in paths on kernel side). For
> example on TRIGGER_STOP we need to first pause all pipelines before issuing
> reset to any of them. This is required by FW, so that if there are two
> pipelines it doesn't pause and reset one of them, while the other one is
> still in running state, as this causes xruns on FW side.

...

> I would say that such behavior doesn't translate nicely to generic API.

This doesn't sound particularly strange, it's not a million miles away
from the requirements we have from hardware around keeping clocks alive.

> I tried looking once again at how one would split the path concept to make
> it more generic, but it is hard. On one hand paths are tied to AVS driver
> topology design, on the other hand we have (mentioned above) FW
> requirements.

Please understand that it is incredibly common for people to belive that
their system is somehow unique and needs to special case things that on
further examination turn out to be perfectly reasonable to handle in a
generic fashion.  Sometimes it's simply a case of just needing to do the
work, sometimes small enhancements are needed to the generic framework
and sometimes it's a case of refactoring the code so that some bits land
in generic code and some bits land in the driver.  Especially with
enormous amounts of code like you've got here there's a natural bias
towards wanting to make minimal changes.

> now for the concept of paths the most interesting field is
> "path_tmpl2_path0_ppl0_bindid0_tuples" as it describes to which path we want
> to bind. It is done this way as FW modules internally have pins, and while
> in most cases one wants to just bind on pin 0, sometimes there is a need to
> describe more complicated connections. And so we circled back to FW
> requirements.

The idea of an algorithm having multiple inputs or outputs seems logical
and generic - the examples that spring to mind are things like mixers,
beam forming or echo/noise cancellation.  These seem like they're going
to be present in a wide range of DSP firmwares.

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  reply	other threads:[~2022-02-02 16:09 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-08 11:12 [RFC 00/37] ASoC: Intel: AVS - Audio DSP for cAVS Cezary Rojewski
2021-12-08 11:12 ` [RFC 01/37] ALSA: hda: Add snd_hdac_ext_bus_link_at() helper Cezary Rojewski
2021-12-08 11:12 ` [RFC 02/37] ALSA: hda: Update and expose snd_hda_codec_device_init() Cezary Rojewski
2021-12-08 11:12 ` [RFC 03/37] ALSA: hda: Update and expose codec register procedures Cezary Rojewski
2021-12-08 11:12 ` [RFC 04/37] ALSA: hda: Expose codec cleanup and power-save functions Cezary Rojewski
2021-12-08 11:12 ` [RFC 05/37] ALSA: hda: Add helper macros for DSP capable devices Cezary Rojewski
2021-12-08 11:12 ` [RFC 06/37] ASoC: Export DAI register and widget ctor and dctor functions Cezary Rojewski
2021-12-21 13:41   ` Mark Brown
2021-12-21 16:40     ` Cezary Rojewski
2021-12-08 11:12 ` [RFC 07/37] ASoC: Intel: Introduce AVS driver Cezary Rojewski
2021-12-08 11:12 ` [RFC 08/37] ASoC: Intel: avs: Inter process communication Cezary Rojewski
2021-12-08 11:12 ` [RFC 09/37] ASoC: Intel: avs: Add code loading requests Cezary Rojewski
2021-12-08 11:12 ` [RFC 10/37] ASoC: Intel: avs: Add pipeline management requests Cezary Rojewski
2021-12-08 11:12 ` [RFC 11/37] ASoC: Intel: avs: Add module " Cezary Rojewski
2021-12-08 11:12 ` [RFC 12/37] ASoC: Intel: avs: Add power " Cezary Rojewski
2021-12-08 11:12 ` [RFC 13/37] ASoC: Intel: avs: Add ROM requests Cezary Rojewski
2021-12-08 11:12 ` [RFC 14/37] ASoC: Intel: avs: Add basefw runtime-parameter requests Cezary Rojewski
2021-12-08 11:12 ` [RFC 15/37] ASoC: Intel: avs: Firmware resources management utilities Cezary Rojewski
2021-12-08 11:12 ` [RFC 16/37] ASoC: Intel: avs: Declare module configuration types Cezary Rojewski
2021-12-08 11:12 ` [RFC 17/37] ASoC: Intel: avs: Dynamic firmware resources management Cezary Rojewski
2021-12-21 14:40   ` Mark Brown
2021-12-21 17:07     ` Cezary Rojewski
2021-12-08 11:12 ` [RFC 18/37] ASoC: Intel: avs: Topology parsing Cezary Rojewski
2021-12-21 17:39   ` Mark Brown
2021-12-22 14:21     ` Cezary Rojewski
2021-12-08 11:12 ` [RFC 19/37] ASoC: Intel: avs: Path management Cezary Rojewski
2021-12-08 11:12 ` [RFC 20/37] ASoC: Intel: avs: Conditional-path support Cezary Rojewski
2021-12-08 11:12 ` [RFC 21/37] ASoC: Intel: avs: General code loading flow Cezary Rojewski
2021-12-08 11:12 ` [RFC 22/37] ASoC: Intel: avs: Implement CLDMA transfer Cezary Rojewski
2021-12-08 11:12 ` [RFC 23/37] ASoC: Intel: avs: Code loading over CLDMA Cezary Rojewski
2021-12-08 11:12 ` [RFC 24/37] ASoC: Intel: avs: Code loading over HDA Cezary Rojewski
2021-12-08 11:12 ` [RFC 25/37] ASoC: Intel: avs: Generic soc component driver Cezary Rojewski
2021-12-08 11:12 ` [RFC 26/37] ASoC: Intel: avs: Generic PCM FE operations Cezary Rojewski
2021-12-08 11:12 ` [RFC 27/37] ASoC: Intel: avs: non-HDA PCM BE operations Cezary Rojewski
2021-12-08 11:12 ` [RFC 28/37] ASoC: Intel: avs: HDA " Cezary Rojewski
2021-12-08 11:12 ` [RFC 29/37] ASoC: Intel: avs: Coredump and recovery flow Cezary Rojewski
2021-12-08 11:12 ` [RFC 30/37] ASoC: Intel: avs: Prepare for firmware tracing Cezary Rojewski
2021-12-08 11:12 ` [RFC 31/37] ASoC: Intel: avs: D0ix power state support Cezary Rojewski
2021-12-08 11:12 ` [RFC 32/37] ASoC: Intel: avs: Event tracing Cezary Rojewski
2021-12-08 11:12 ` [RFC 33/37] ASoC: Intel: avs: Machine board registration Cezary Rojewski
2021-12-08 11:12 ` [RFC 34/37] ASoC: Intel: avs: PCI driver implementation Cezary Rojewski
2021-12-08 11:12 ` [RFC 35/37] ASoC: Intel: avs: Power management Cezary Rojewski
2021-12-08 11:13 ` [RFC 36/37] ASoC: Intel: avs: SKL-based platforms support Cezary Rojewski
2021-12-08 11:13 ` [RFC 37/37] ASoC: Intel: avs: APL-based " Cezary Rojewski
2021-12-08 16:27 ` [RFC 00/37] ASoC: Intel: AVS - Audio DSP for cAVS Pierre-Louis Bossart
2021-12-08 17:51   ` Mark Brown
2021-12-09  9:59   ` Cezary Rojewski
2021-12-24 13:06 ` Mark Brown
2022-01-06 13:39   ` Cezary Rojewski
2022-01-18  9:42     ` Cezary Rojewski
2022-01-25 13:25       ` Mark Brown
2022-01-28 17:00     ` Mark Brown
2022-01-30 19:15       ` Cezary Rojewski
2022-02-02 13:26         ` Amadeusz Sławiński
2022-02-02 16:08           ` Mark Brown [this message]
2022-02-02 14:41         ` Mark Brown
2022-02-07 13:42           ` Cezary Rojewski

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