From: Oliver Upton <oliver.upton@linux.dev> To: Raghavendra Rao Ananta <rananta@google.com> Cc: Oliver Upton <oupton@google.com>, Marc Zyngier <maz@kernel.org>, Ricardo Koller <ricarkol@google.com>, Reiji Watanabe <reijiw@google.com>, James Morse <james.morse@arm.com>, Alexandru Elisei <alexandru.elisei@arm.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Will Deacon <will@kernel.org>, Paolo Bonzini <pbonzini@redhat.com>, Catalin Marinas <catalin.marinas@arm.com>, Jing Zhang <jingzhangos@google.com>, Colton Lewis <coltonlewis@google.com>, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: Re: [PATCH v2 6/7] KVM: arm64: Break the table entries using TLBI range instructions Date: Thu, 30 Mar 2023 00:17:25 +0000 [thread overview] Message-ID: <ZCTVFYd2oJnGR6O+@linux.dev> (raw) In-Reply-To: <20230206172340.2639971-7-rananta@google.com> nit: s/break/invalidate/g There is a rather important degree of nuance there. 'Break' as it relates to break-before-make implies that the PTE is made invalid and visible to hardware _before_ a subsequent invalidation. There will be systems that relax this requirement and also support TLBIRANGE. On Mon, Feb 06, 2023 at 05:23:39PM +0000, Raghavendra Rao Ananta wrote: Some nitpicking on the changelog: > Currently, when breaking up the stage-2 table entries, KVM 'breaking up stage-2 table entries' is rather ambiguous. Instead describe the operation taking place on the page tables (i.e. hugepage collapse). > would flush the entire VM's context using 'vmalls12e1is' > TLBI operation. One of the problematic situation is collapsing > table entries into a hugepage, specifically if the VM is > faulting on many hugepages (say after dirty-logging). This > creates a performance penality for the guest whose pages have typo: penalty > already been faulted earlier as they would have to refill their > TLBs again. > > Hence, if the system supports it, use __kvm_tlb_flush_range_vmid_ipa() > to flush only the range of pages governed by the table entry, > while leaving other TLB entries alone. An upcoming patch also > takes advantage of this when breaking up table entries during > the unmap operation. Language regarding an upcoming patch isn't necessary, as this one stands on its own (implements and uses a range-based invalidation helper). > Signed-off-by: Raghavendra Rao Ananta <rananta@google.com> > --- > arch/arm64/kvm/hyp/pgtable.c | 23 ++++++++++++++++++++--- > 1 file changed, 20 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c > index b11cf2c618a6c..0858d1fa85d6b 100644 > --- a/arch/arm64/kvm/hyp/pgtable.c > +++ b/arch/arm64/kvm/hyp/pgtable.c > @@ -686,6 +686,20 @@ static bool stage2_try_set_pte(const struct kvm_pgtable_visit_ctx *ctx, kvm_pte_ > return cmpxchg(ctx->ptep, ctx->old, new) == ctx->old; > } > > +static void kvm_pgtable_stage2_flush_range(struct kvm_s2_mmu *mmu, u64 start, u64 end, > + u32 level, u32 tlb_level) > +{ > + if (system_supports_tlb_range()) You also check this in __kvm_tlb_flush_range(), ideally this should be done exactly once per call. > + kvm_call_hyp(__kvm_tlb_flush_range_vmid_ipa, mmu, start, end, level, tlb_level); > + else > + /* > + * Invalidate the whole stage-2, as we may have numerous leaf > + * entries below us which would otherwise need invalidating > + * individually. > + */ > + kvm_call_hyp(__kvm_tlb_flush_vmid, mmu); > +} > + > /** > * stage2_try_break_pte() - Invalidates a pte according to the > * 'break-before-make' requirements of the > @@ -721,10 +735,13 @@ static bool stage2_try_break_pte(const struct kvm_pgtable_visit_ctx *ctx, > * Perform the appropriate TLB invalidation based on the evicted pte > * value (if any). > */ > - if (kvm_pte_table(ctx->old, ctx->level)) > - kvm_call_hyp(__kvm_tlb_flush_vmid, mmu); > - else if (kvm_pte_valid(ctx->old)) > + if (kvm_pte_table(ctx->old, ctx->level)) { > + u64 end = ctx->addr + kvm_granule_size(ctx->level); > + > + kvm_pgtable_stage2_flush_range(mmu, ctx->addr, end, ctx->level, 0); > + } else if (kvm_pte_valid(ctx->old)) { > kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, mmu, ctx->addr, ctx->level); > + } > > if (stage2_pte_is_counted(ctx->old)) > mm_ops->put_page(ctx->ptep); > -- > 2.39.1.519.gcb327c4b5f-goog > > -- Thanks, Oliver
WARNING: multiple messages have this Message-ID (diff)
From: Oliver Upton <oliver.upton@linux.dev> To: Raghavendra Rao Ananta <rananta@google.com> Cc: Oliver Upton <oupton@google.com>, Marc Zyngier <maz@kernel.org>, Ricardo Koller <ricarkol@google.com>, Reiji Watanabe <reijiw@google.com>, James Morse <james.morse@arm.com>, Alexandru Elisei <alexandru.elisei@arm.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Will Deacon <will@kernel.org>, Paolo Bonzini <pbonzini@redhat.com>, Catalin Marinas <catalin.marinas@arm.com>, Jing Zhang <jingzhangos@google.com>, Colton Lewis <coltonlewis@google.com>, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: Re: [PATCH v2 6/7] KVM: arm64: Break the table entries using TLBI range instructions Date: Thu, 30 Mar 2023 00:17:25 +0000 [thread overview] Message-ID: <ZCTVFYd2oJnGR6O+@linux.dev> (raw) In-Reply-To: <20230206172340.2639971-7-rananta@google.com> nit: s/break/invalidate/g There is a rather important degree of nuance there. 'Break' as it relates to break-before-make implies that the PTE is made invalid and visible to hardware _before_ a subsequent invalidation. There will be systems that relax this requirement and also support TLBIRANGE. On Mon, Feb 06, 2023 at 05:23:39PM +0000, Raghavendra Rao Ananta wrote: Some nitpicking on the changelog: > Currently, when breaking up the stage-2 table entries, KVM 'breaking up stage-2 table entries' is rather ambiguous. Instead describe the operation taking place on the page tables (i.e. hugepage collapse). > would flush the entire VM's context using 'vmalls12e1is' > TLBI operation. One of the problematic situation is collapsing > table entries into a hugepage, specifically if the VM is > faulting on many hugepages (say after dirty-logging). This > creates a performance penality for the guest whose pages have typo: penalty > already been faulted earlier as they would have to refill their > TLBs again. > > Hence, if the system supports it, use __kvm_tlb_flush_range_vmid_ipa() > to flush only the range of pages governed by the table entry, > while leaving other TLB entries alone. An upcoming patch also > takes advantage of this when breaking up table entries during > the unmap operation. Language regarding an upcoming patch isn't necessary, as this one stands on its own (implements and uses a range-based invalidation helper). > Signed-off-by: Raghavendra Rao Ananta <rananta@google.com> > --- > arch/arm64/kvm/hyp/pgtable.c | 23 ++++++++++++++++++++--- > 1 file changed, 20 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c > index b11cf2c618a6c..0858d1fa85d6b 100644 > --- a/arch/arm64/kvm/hyp/pgtable.c > +++ b/arch/arm64/kvm/hyp/pgtable.c > @@ -686,6 +686,20 @@ static bool stage2_try_set_pte(const struct kvm_pgtable_visit_ctx *ctx, kvm_pte_ > return cmpxchg(ctx->ptep, ctx->old, new) == ctx->old; > } > > +static void kvm_pgtable_stage2_flush_range(struct kvm_s2_mmu *mmu, u64 start, u64 end, > + u32 level, u32 tlb_level) > +{ > + if (system_supports_tlb_range()) You also check this in __kvm_tlb_flush_range(), ideally this should be done exactly once per call. > + kvm_call_hyp(__kvm_tlb_flush_range_vmid_ipa, mmu, start, end, level, tlb_level); > + else > + /* > + * Invalidate the whole stage-2, as we may have numerous leaf > + * entries below us which would otherwise need invalidating > + * individually. > + */ > + kvm_call_hyp(__kvm_tlb_flush_vmid, mmu); > +} > + > /** > * stage2_try_break_pte() - Invalidates a pte according to the > * 'break-before-make' requirements of the > @@ -721,10 +735,13 @@ static bool stage2_try_break_pte(const struct kvm_pgtable_visit_ctx *ctx, > * Perform the appropriate TLB invalidation based on the evicted pte > * value (if any). > */ > - if (kvm_pte_table(ctx->old, ctx->level)) > - kvm_call_hyp(__kvm_tlb_flush_vmid, mmu); > - else if (kvm_pte_valid(ctx->old)) > + if (kvm_pte_table(ctx->old, ctx->level)) { > + u64 end = ctx->addr + kvm_granule_size(ctx->level); > + > + kvm_pgtable_stage2_flush_range(mmu, ctx->addr, end, ctx->level, 0); > + } else if (kvm_pte_valid(ctx->old)) { > kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, mmu, ctx->addr, ctx->level); > + } > > if (stage2_pte_is_counted(ctx->old)) > mm_ops->put_page(ctx->ptep); > -- > 2.39.1.519.gcb327c4b5f-goog > > -- Thanks, Oliver _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-03-30 0:17 UTC|newest] Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-02-06 17:23 [PATCH v2 0/7] KVM: arm64: Add support for FEAT_TLBIRANGE Raghavendra Rao Ananta 2023-02-06 17:23 ` Raghavendra Rao Ananta 2023-02-06 17:23 ` [PATCH v2 1/7] arm64: tlb: Refactor the core flush algorithm of __flush_tlb_range Raghavendra Rao Ananta 2023-02-06 17:23 ` Raghavendra Rao Ananta 2023-02-06 17:23 ` [PATCH v2 2/7] KVM: arm64: Add FEAT_TLBIRANGE support Raghavendra Rao Ananta 2023-02-06 17:23 ` Raghavendra Rao Ananta 2023-03-30 1:19 ` Oliver Upton 2023-03-30 1:19 ` Oliver Upton 2023-04-03 17:26 ` Raghavendra Rao Ananta 2023-04-03 17:26 ` Raghavendra Rao Ananta 2023-04-04 18:41 ` Oliver Upton 2023-04-04 18:41 ` Oliver Upton 2023-04-04 18:50 ` Oliver Upton 2023-04-04 18:50 ` Oliver Upton 2023-04-04 21:39 ` Raghavendra Rao Ananta 2023-04-04 21:39 ` Raghavendra Rao Ananta 2023-02-06 17:23 ` [PATCH v2 3/7] KVM: arm64: Implement __kvm_tlb_flush_range_vmid_ipa() Raghavendra Rao Ananta 2023-02-06 17:23 ` Raghavendra Rao Ananta 2023-03-30 0:59 ` Oliver Upton 2023-03-30 0:59 ` Oliver Upton 2023-04-03 21:08 ` Raghavendra Rao Ananta 2023-04-03 21:08 ` Raghavendra Rao Ananta 2023-04-04 18:46 ` Oliver Upton 2023-04-04 18:46 ` Oliver Upton 2023-04-04 20:50 ` Raghavendra Rao Ananta 2023-04-04 20:50 ` Raghavendra Rao Ananta 2023-02-06 17:23 ` [PATCH v2 4/7] KVM: arm64: Implement kvm_arch_flush_remote_tlbs_range() Raghavendra Rao Ananta 2023-02-06 17:23 ` Raghavendra Rao Ananta 2023-03-30 0:53 ` Oliver Upton 2023-03-30 0:53 ` Oliver Upton 2023-04-03 21:23 ` Raghavendra Rao Ananta 2023-04-03 21:23 ` Raghavendra Rao Ananta 2023-04-04 19:09 ` Oliver Upton 2023-04-04 19:09 ` Oliver Upton 2023-04-04 20:59 ` Raghavendra Rao Ananta 2023-04-04 20:59 ` Raghavendra Rao Ananta 2023-02-06 17:23 ` [PATCH v2 5/7] KVM: arm64: Flush only the memslot after write-protect Raghavendra Rao Ananta 2023-02-06 17:23 ` Raghavendra Rao Ananta 2023-02-06 17:23 ` [PATCH v2 6/7] KVM: arm64: Break the table entries using TLBI range instructions Raghavendra Rao Ananta 2023-02-06 17:23 ` Raghavendra Rao Ananta 2023-03-30 0:17 ` Oliver Upton [this message] 2023-03-30 0:17 ` Oliver Upton 2023-04-03 21:25 ` Raghavendra Rao Ananta 2023-04-03 21:25 ` Raghavendra Rao Ananta 2023-02-06 17:23 ` [PATCH v2 7/7] KVM: arm64: Create a fast stage-2 unmap path Raghavendra Rao Ananta 2023-02-06 17:23 ` Raghavendra Rao Ananta 2023-03-30 0:42 ` Oliver Upton 2023-03-30 0:42 ` Oliver Upton 2023-04-04 17:52 ` Raghavendra Rao Ananta 2023-04-04 17:52 ` Raghavendra Rao Ananta 2023-04-04 19:19 ` Oliver Upton 2023-04-04 19:19 ` Oliver Upton 2023-04-04 21:07 ` Raghavendra Rao Ananta 2023-04-04 21:07 ` Raghavendra Rao Ananta 2023-04-04 21:30 ` Oliver Upton 2023-04-04 21:30 ` Oliver Upton 2023-04-04 21:45 ` Raghavendra Rao Ananta 2023-04-04 21:45 ` Raghavendra Rao Ananta
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