Re: [PATCH 3/4] drm/i915/dmc: Also disable HRR event on TGL main DMC

From: Imre Deak <imre.deak@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/4] drm/i915/dmc: Also disable HRR event on TGL main DMC
Date: Wed, 13 Dec 2023 12:58:08 +0200	[thread overview]
Message-ID: <ZXmOQOgTOCOMbwkz@ideak-desk.fi.intel.com> (raw)
In-Reply-To: <ZXl57Kgi78g9Wx-h@intel.com>

On Wed, Dec 13, 2023 at 11:31:24AM +0200, Ville Syrjälä wrote:
> On Wed, Dec 13, 2023 at 10:17:58AM +0200, Imre Deak wrote:
> > On Mon, Dec 11, 2023 at 11:37:49PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Unlike later platforms TGL has the half refresh rate (HRR) event
> > > on the main DMC (as opposed to the pipe DMC). Since we're disabling
> > > that event on all later platforms already let's do the same on
> > > TGL as well.
> > > 
> > > There is supposedly a bit somewhere (DMC_CHICKEN on TGL) to make
> > > the handler not do anything, but we don't currently have code
> > > to frob it. Though that bit should be off by default, the ADL+
> > > experience has shown us that trusting any of this isn't a good
> > > idea. So seems safer to just disable all event handlers we know
> > > that we don't need.
> > > 
> > > Also the TGL DMC firmware is apparently using the wrong event
> > > (undelayed vblank) here anyway. It should be using the delayed
> > > vblank event instead (like ADL+ firmware does), but they didn't
> > > release a firmware fix for this and instead just hacked around
> > > this in the Windows driver code :/
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_dmc.c      | 5 +++++
> > >  drivers/gpu/drm/i915/display/intel_dmc_regs.h | 1 +
> > >  2 files changed, 6 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> > > index 9385898e3aa5..0722d322ec63 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > > @@ -448,6 +448,11 @@ static bool disable_dmc_evt(struct drm_i915_private *i915,
> > >  	    REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_CLK_MSEC)
> > >  		return true;
> > >  
> > > +	/* also disable the HRR event on the main DMC on TGL */
> > > +	if (IS_TIGERLAKE(i915) &&
> > > +	    REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_VBLANK_A)
> > 
> > The adls FW has the same event (but not the MSEC flip-queue one for some
> > reason).
> 
> I can't see it in the binary. Though I am using hexdump so it might
> also be that I'm looking in the wrong place :P

I see
dmc-dump -p 0 -i ~/Downloads/adls_dmc_ver2_01.bin

CSS module
=================================
Module type            : 9
Module header len      : 128 bytes
Module header version  : 1.0
Module id              : 0x00000000
Module vendor          : 0x00000000
Module build date      : 2020/05/26
Module size            : 18704 bytes
Module key size        : 0
Module modulus size    : 0
Module exponent size   : 0
Module version         : 2.1
Module kernel header   : 0x0

Package
===================================
Package header len     : 400 bytes
Package header version : 2
Package payload entries: 2

Payload#0
-----------------------------------
Payload type           : main
Payload CPU stepping   : *
Payload CPU substepping: *
Payload file offset    : 528
-----------------------------------
FW signature           : 0x40403e3e
FW header len          : 256 bytes
FW header version      : 3
FW DMC HW version      : 12.2
FW Project             : 0x0c00
FW program size        : 16784 bytes
FW program area        : 0x080000 - 0x08418f
FW file offset         : 784
FW source version      : 0.1
FW fix MMIO count      : 7
FW fix MMIOs           :
  [8f074]=00086fc0
  [8f034]=c003b400
  [8f004]=01a40188
  [8f038]=c003b200
  [8f008]=3dc43bf4
  [8f03c]=c0033200
  [8f00c]=40b8408c
FW source file name    : d12adls_fw_main_0.1.d\x00-device\x00D1

> 
> > 
> > > +		return true;
> > > +
> > >  	return false;
> > >  }
> > >  
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> > > index cf10094acae3..90d0dbb41cfe 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> > > @@ -60,6 +60,7 @@
> > >  
> > >  #define DMC_EVT_CTL_EVENT_ID_MASK	REG_GENMASK(15, 8)
> > >  #define DMC_EVT_CTL_EVENT_ID_FALSE	0x01
> > > +#define DMC_EVT_CTL_EVENT_ID_VBLANK_A	0x32 /* main DMC */
> > >  /* An event handler scheduled to run at a 1 kHz frequency. */
> > >  #define DMC_EVT_CTL_EVENT_ID_CLK_MSEC	0xbf
> > >  
> > > -- 
> > > 2.41.0
> > > 
> 
> -- 
> Ville Syrjälä
> Intel