From: "Michał Mirosław" <mirq-linux@rere.qmqm.pl> To: Kevin Liu <kliu5@marvell.com>, Suneel Garapati <suneel.garapati@xilinx.com>, Ulf Hansson <ulf.hansson@linaro.org> Cc: Adrian Hunter <adrian.hunter@intel.com>, Chris Ball <cjb@laptop.org>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, Michal Simek <michal.simek@xilinx.com> Subject: [PATCH v3 5/5] mmc: sdhci: simplify v2/v3+ clock calculation Date: Sun, 25 Jul 2021 06:25:18 +0200 [thread overview] Message-ID: <a1d220656a6851e05739ac5438bb86cb13cc6e3c.1627186831.git.mirq-linux@rere.qmqm.pl> (raw) In-Reply-To: <cover.1627186831.git.mirq-linux@rere.qmqm.pl> For base clock setting, SDHCI V2 differs from V3+ only in allowed divisor values. Remove the duplicate version of code and reduce indentation levels. We can see now, that 'real_div' can't be zero, so the check is removed. While at it, replace divisor search loops with divide-and-clamp to make the code even more readable. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> --- v3: squashed div-conversion and deduplication patches to avoid code churn v2: no changes --- drivers/mmc/host/sdhci.c | 124 ++++++++++++++++++--------------------- drivers/mmc/host/sdhci.h | 4 +- 2 files changed, 58 insertions(+), 70 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index cfa314e659bc..90bda4150083 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1848,88 +1848,76 @@ static u16 sdhci_get_preset_value(struct sdhci_host *host) u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, unsigned int *actual_clock) { - int div = 0; /* Initialized for compiler warning */ - int real_div = div, clk_mul = 1; + unsigned int div, real_div, clk_mul = 1; u16 clk = 0; - bool switch_base_clk = false; - if (host->version >= SDHCI_SPEC_300) { - if (host->preset_enabled) { - u16 pre_val; + if (clock == 0) + return clk; + + if (host->preset_enabled) { + /* Only version 3.00+ can have preset_enabled */ + u16 pre_val; + + pre_val = sdhci_get_preset_value(host); + div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val); + if (!(pre_val & SDHCI_PRESET_CLKGEN_SEL)) + goto base_div_set; + + clk = SDHCI_PROG_CLOCK_MODE; + real_div = div + 1; + clk_mul = host->clk_mul; + if (!clk_mul) { + /* The clock frequency is unknown. Assume undivided base. */ + clk_mul = 1; + } + + goto clock_set; + } + + /* + * Check if the Host Controller supports Programmable Clock + * Mode. + */ + if (host->version >= SDHCI_SPEC_300 && host->clk_mul) { + div = DIV_ROUND_UP(host->max_clk * host->clk_mul, clock); + if (div <= SDHCI_MAX_DIV_SPEC_300 / 2 + 1) { + /* + * Set Programmable Clock Mode in the Clock + * Control register. + */ + clk = SDHCI_PROG_CLOCK_MODE; + clk_mul = host->clk_mul; + real_div = div--; - pre_val = sdhci_get_preset_value(host); - div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val); - if (pre_val & SDHCI_PRESET_CLKGEN_SEL) { - clk = SDHCI_PROG_CLOCK_MODE; - real_div = div + 1; - clk_mul = host->clk_mul; - if (!clk_mul) { - /* The clock frequency is unknown. Assume undivided base. */ - clk_mul = 1; - } - } else { - real_div = max_t(int, 1, div << 1); - } goto clock_set; } /* - * Check if the Host Controller supports Programmable Clock - * Mode. + * Divisor is too big for requested clock rate. + * Fall back to the base clock. */ - if (host->clk_mul) { - for (div = 1; div <= 1024; div++) { - if ((host->max_clk * host->clk_mul / div) - <= clock) - break; - } - if ((host->max_clk * host->clk_mul / div) <= clock) { - /* - * Set Programmable Clock Mode in the Clock - * Control register. - */ - clk = SDHCI_PROG_CLOCK_MODE; - real_div = div; - clk_mul = host->clk_mul; - div--; - } else { - /* - * Divisor can be too small to reach clock - * speed requirement. Then use the base clock. - */ - switch_base_clk = true; - } - } + } - if (!host->clk_mul || switch_base_clk) { - /* Version 3.00 divisors must be a multiple of 2. */ - if (host->max_clk <= clock) { - div = 1; - if (host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) - div = 2; - } else { - for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; - div += 2) { - if ((host->max_clk / div) <= clock) - break; - } - } - real_div = div; - div >>= 1; - } + div = DIV_ROUND_UP(host->max_clk, clock); + + if (div == 1 && (host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)) + div = 2; + + if (host->version >= SDHCI_SPEC_300) { + /* Version 3.00 divisors must be a multiple of 2. */ + div = min(div, SDHCI_MAX_DIV_SPEC_300); + div = DIV_ROUND_UP(div, 2); } else { /* Version 2.00 divisors must be a power of 2. */ - for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { - if ((host->max_clk / div) <= clock) - break; - } - real_div = div; - div >>= 1; + div = min(div, SDHCI_MAX_DIV_SPEC_200); + div = roundup_pow_of_two(div) / 2; } +base_div_set: + real_div = div * 2 + !div; + clock_set: - if (real_div) - *actual_clock = (host->max_clk * clk_mul) / real_div; + *actual_clock = (host->max_clk * clk_mul) / real_div; clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) << SDHCI_DIVIDER_HI_SHIFT; diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 074dc182b184..a3fa70d91410 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -284,8 +284,8 @@ * End of controller registers. */ -#define SDHCI_MAX_DIV_SPEC_200 256 -#define SDHCI_MAX_DIV_SPEC_300 2046 +#define SDHCI_MAX_DIV_SPEC_200 256u +#define SDHCI_MAX_DIV_SPEC_300 2046u /* * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: "Michał Mirosław" <mirq-linux@rere.qmqm.pl> To: Kevin Liu <kliu5@marvell.com>, Suneel Garapati <suneel.garapati@xilinx.com>, Ulf Hansson <ulf.hansson@linaro.org> Cc: Adrian Hunter <adrian.hunter@intel.com>, Chris Ball <cjb@laptop.org>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, Michal Simek <michal.simek@xilinx.com> Subject: [PATCH v3 5/5] mmc: sdhci: simplify v2/v3+ clock calculation Date: Sun, 25 Jul 2021 06:25:18 +0200 [thread overview] Message-ID: <a1d220656a6851e05739ac5438bb86cb13cc6e3c.1627186831.git.mirq-linux@rere.qmqm.pl> (raw) In-Reply-To: <cover.1627186831.git.mirq-linux@rere.qmqm.pl> For base clock setting, SDHCI V2 differs from V3+ only in allowed divisor values. Remove the duplicate version of code and reduce indentation levels. We can see now, that 'real_div' can't be zero, so the check is removed. While at it, replace divisor search loops with divide-and-clamp to make the code even more readable. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> --- v3: squashed div-conversion and deduplication patches to avoid code churn v2: no changes --- drivers/mmc/host/sdhci.c | 124 ++++++++++++++++++--------------------- drivers/mmc/host/sdhci.h | 4 +- 2 files changed, 58 insertions(+), 70 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index cfa314e659bc..90bda4150083 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1848,88 +1848,76 @@ static u16 sdhci_get_preset_value(struct sdhci_host *host) u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, unsigned int *actual_clock) { - int div = 0; /* Initialized for compiler warning */ - int real_div = div, clk_mul = 1; + unsigned int div, real_div, clk_mul = 1; u16 clk = 0; - bool switch_base_clk = false; - if (host->version >= SDHCI_SPEC_300) { - if (host->preset_enabled) { - u16 pre_val; + if (clock == 0) + return clk; + + if (host->preset_enabled) { + /* Only version 3.00+ can have preset_enabled */ + u16 pre_val; + + pre_val = sdhci_get_preset_value(host); + div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val); + if (!(pre_val & SDHCI_PRESET_CLKGEN_SEL)) + goto base_div_set; + + clk = SDHCI_PROG_CLOCK_MODE; + real_div = div + 1; + clk_mul = host->clk_mul; + if (!clk_mul) { + /* The clock frequency is unknown. Assume undivided base. */ + clk_mul = 1; + } + + goto clock_set; + } + + /* + * Check if the Host Controller supports Programmable Clock + * Mode. + */ + if (host->version >= SDHCI_SPEC_300 && host->clk_mul) { + div = DIV_ROUND_UP(host->max_clk * host->clk_mul, clock); + if (div <= SDHCI_MAX_DIV_SPEC_300 / 2 + 1) { + /* + * Set Programmable Clock Mode in the Clock + * Control register. + */ + clk = SDHCI_PROG_CLOCK_MODE; + clk_mul = host->clk_mul; + real_div = div--; - pre_val = sdhci_get_preset_value(host); - div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val); - if (pre_val & SDHCI_PRESET_CLKGEN_SEL) { - clk = SDHCI_PROG_CLOCK_MODE; - real_div = div + 1; - clk_mul = host->clk_mul; - if (!clk_mul) { - /* The clock frequency is unknown. Assume undivided base. */ - clk_mul = 1; - } - } else { - real_div = max_t(int, 1, div << 1); - } goto clock_set; } /* - * Check if the Host Controller supports Programmable Clock - * Mode. + * Divisor is too big for requested clock rate. + * Fall back to the base clock. */ - if (host->clk_mul) { - for (div = 1; div <= 1024; div++) { - if ((host->max_clk * host->clk_mul / div) - <= clock) - break; - } - if ((host->max_clk * host->clk_mul / div) <= clock) { - /* - * Set Programmable Clock Mode in the Clock - * Control register. - */ - clk = SDHCI_PROG_CLOCK_MODE; - real_div = div; - clk_mul = host->clk_mul; - div--; - } else { - /* - * Divisor can be too small to reach clock - * speed requirement. Then use the base clock. - */ - switch_base_clk = true; - } - } + } - if (!host->clk_mul || switch_base_clk) { - /* Version 3.00 divisors must be a multiple of 2. */ - if (host->max_clk <= clock) { - div = 1; - if (host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) - div = 2; - } else { - for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; - div += 2) { - if ((host->max_clk / div) <= clock) - break; - } - } - real_div = div; - div >>= 1; - } + div = DIV_ROUND_UP(host->max_clk, clock); + + if (div == 1 && (host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)) + div = 2; + + if (host->version >= SDHCI_SPEC_300) { + /* Version 3.00 divisors must be a multiple of 2. */ + div = min(div, SDHCI_MAX_DIV_SPEC_300); + div = DIV_ROUND_UP(div, 2); } else { /* Version 2.00 divisors must be a power of 2. */ - for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { - if ((host->max_clk / div) <= clock) - break; - } - real_div = div; - div >>= 1; + div = min(div, SDHCI_MAX_DIV_SPEC_200); + div = roundup_pow_of_two(div) / 2; } +base_div_set: + real_div = div * 2 + !div; + clock_set: - if (real_div) - *actual_clock = (host->max_clk * clk_mul) / real_div; + *actual_clock = (host->max_clk * clk_mul) / real_div; clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) << SDHCI_DIVIDER_HI_SHIFT; diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 074dc182b184..a3fa70d91410 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -284,8 +284,8 @@ * End of controller registers. */ -#define SDHCI_MAX_DIV_SPEC_200 256 -#define SDHCI_MAX_DIV_SPEC_300 2046 +#define SDHCI_MAX_DIV_SPEC_200 256u +#define SDHCI_MAX_DIV_SPEC_300 2046u /* * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-07-25 4:25 UTC|newest] Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-25 4:25 [PATCH v3 0/5] SDHCI clock handling fixes and cleanups Michał Mirosław 2021-07-25 4:25 ` [PATCH v3 3/5] mmc: sdhci: fix SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN Michał Mirosław 2021-07-25 4:25 ` Michał Mirosław 2021-07-25 4:25 ` [PATCH v3 2/5] mmc: sdhci: always obey programmable clock config in preset value Michał Mirosław 2021-07-25 4:25 ` Michał Mirosław 2021-07-25 4:25 ` [PATCH v3 1/5] mmc: sdhci: fix base clock usage " Michał Mirosław 2021-07-25 4:25 ` Michał Mirosław 2021-07-25 4:25 ` [PATCH v3 4/5] mmc: sdhci: move SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN frequency limit Michał Mirosław 2021-07-25 4:25 ` Michał Mirosław 2021-07-25 9:05 ` kernel test robot 2021-07-25 9:05 ` kernel test robot 2021-07-25 9:05 ` kernel test robot 2021-07-25 19:16 ` kernel test robot 2021-07-25 19:16 ` kernel test robot 2021-07-25 19:16 ` kernel test robot 2021-07-25 4:25 ` Michał Mirosław [this message] 2021-07-25 4:25 ` [PATCH v3 5/5] mmc: sdhci: simplify v2/v3+ clock calculation Michał Mirosław
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