Re: [XEN v6 3/3] xen/arm: arm32: Add emulation of Debug Data Transfer Registers

From: Julien Grall <julien@xen.org>
To: Ayan Kumar Halder <ayan.kumar.halder@amd.com>,
	xen-devel@lists.xenproject.org
Cc: sstabellini@kernel.org, stefano.stabellini@amd.com,
	Volodymyr_Babchuk@epam.com, bertrand.marquis@arm.com,
	michal.orzel@amd.com
Subject: Re: [XEN v6 3/3] xen/arm: arm32: Add emulation of Debug Data Transfer Registers
Date: Tue, 12 Mar 2024 22:33:52 +0000	[thread overview]
Message-ID: <a60c8977-8a62-475f-a392-8f0c75bcd6c7@xen.org> (raw)
In-Reply-To: <20240307123943.1991755-4-ayan.kumar.halder@amd.com>

Hi Ayan,

On 07/03/2024 12:39, Ayan Kumar Halder wrote:
> When user enables HVC_DCC config option in Linux, it invokes access to debug
> transfer register (i.e. DBGDTRTXINT). As this register is not emulated, Xen
> injects an undefined exception to the guest and Linux crashes.
> 
> To prevent this crash, introduce a partial emulation of DBGDTR[TR]XINT (these
> registers share the same encoding) as RAZ/WI and DBGDSCRINT as TXfull.
> 
> Refer ARM DDI 0487J.a ID042523, G8.3.19, DBGDTRTXint:
> "If TXfull is set to 1, set DTRTX to UNKNOWN".
> 
> As a pre-requisite, DBGOSLSR should be emulated in the same way as its AArch64
> variant (i.e. OSLSR_EL1). This is to ensure that DBGOSLSR.OSLK is 0, which
> allows us to skip the emulation of DBGDSCREXT (TXfull is treated as UNK/SBZP)
> and focus on DBGDSCRINT. DBGOSLSR.OSLM[1] is set to 1 to mantain consistency
> with Arm64.
> 
> Take the opportunity to fix the minimum EL for DBGDSCRINT, which should be 0.

NIT: Strictly speaking Arm32 is using PL (Priviledge) rather than EL 
(Exception Level) to describe each level :).

Anyway,

> 
> Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
> Signed-off-by: Michal Orzel <michal.orzel@amd.com>

Acked-by: Julien Grall <jgrall@amazon.com>

Cheers,

-- 
Julien Grall