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From: "Verma, Achal" <a-verma1@ti.com>
To: "Li Chen" <me@linux.beauty>,
	"Vignesh Raghavendra" <vigneshr@ti.com>,
	"Tom Joseph" <tjoseph@cadence.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	linux-omap <linux-omap@vger.kernel.org>,
	linux-pci <linux-pci@vger.kernel.org>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/2] PCI: j721e: Allow async probe
Date: Tue, 11 Jul 2023 11:46:01 +0530	[thread overview]
Message-ID: <ac95ffd2-50c6-f715-5c37-f658bacf4ca4@ti.com> (raw)
In-Reply-To: <1892e291fa4.1219137911620526.2248312811348305435@linux.beauty>



On 7/7/2023 7:53 AM, Li Chen wrote:
> From: Li Chen <lchen@ambarella.com>
> 
> I observed that on Ambarella SoC, which also utilizes
> the Cadence controller, the boot time increases by 1
> second when no endpoints (including switch) are connected
> to PCIe. This increase is caused by cdns_pcie_host_wait_for_link.
> 
> Enabling async probe can eliminate this boot time increase.
> 
> I guess j721e also has this issue.
I have tested this along with:
https://lore.kernel.org 
/all/1892e2ae15f.f7e5dc061620757.4339091752690983066@linux.beauty/

But I couldn't find second patch in this series.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
Tested-by: Achal Verma <a-verma1@ti.com>
> ---
>   drivers/pci/controller/cadence/pci-j721e.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index e70213c9060a..660c13bdb606 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -561,6 +561,7 @@ static struct platform_driver j721e_pcie_driver = {
>   		.name	= "j721e-pcie",
>   		.of_match_table = of_j721e_pcie_match,
>   		.suppress_bind_attrs = true,
> +		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
>   	},
>   };
>   builtin_platform_driver(j721e_pcie_driver);

WARNING: multiple messages have this Message-ID (diff)
From: "Verma, Achal" <a-verma1@ti.com>
To: "Li Chen" <me@linux.beauty>,
	"Vignesh Raghavendra" <vigneshr@ti.com>,
	"Tom Joseph" <tjoseph@cadence.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	linux-omap <linux-omap@vger.kernel.org>,
	linux-pci <linux-pci@vger.kernel.org>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/2] PCI: j721e: Allow async probe
Date: Tue, 11 Jul 2023 11:46:01 +0530	[thread overview]
Message-ID: <ac95ffd2-50c6-f715-5c37-f658bacf4ca4@ti.com> (raw)
In-Reply-To: <1892e291fa4.1219137911620526.2248312811348305435@linux.beauty>



On 7/7/2023 7:53 AM, Li Chen wrote:
> From: Li Chen <lchen@ambarella.com>
> 
> I observed that on Ambarella SoC, which also utilizes
> the Cadence controller, the boot time increases by 1
> second when no endpoints (including switch) are connected
> to PCIe. This increase is caused by cdns_pcie_host_wait_for_link.
> 
> Enabling async probe can eliminate this boot time increase.
> 
> I guess j721e also has this issue.
I have tested this along with:
https://lore.kernel.org 
/all/1892e2ae15f.f7e5dc061620757.4339091752690983066@linux.beauty/

But I couldn't find second patch in this series.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
Tested-by: Achal Verma <a-verma1@ti.com>
> ---
>   drivers/pci/controller/cadence/pci-j721e.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index e70213c9060a..660c13bdb606 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -561,6 +561,7 @@ static struct platform_driver j721e_pcie_driver = {
>   		.name	= "j721e-pcie",
>   		.of_match_table = of_j721e_pcie_match,
>   		.suppress_bind_attrs = true,
> +		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
>   	},
>   };
>   builtin_platform_driver(j721e_pcie_driver);

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  reply	other threads:[~2023-07-11  6:16 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-07  2:23 [PATCH 1/2] PCI: j721e: Allow async probe Li Chen
2023-07-07  2:23 ` Li Chen
2023-07-11  6:16 ` Verma, Achal [this message]
2023-07-11  6:16   ` Verma, Achal
2023-07-11  8:43   ` Li Chen
2023-07-11  8:43     ` Li Chen
2023-07-12  8:27     ` [EXTERNAL] " Verma, Achal
2023-07-12  8:27       ` Verma, Achal

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