From: Joseph Lo <josephl@nvidia.com>
To: Jon Hunter <jonathanh@nvidia.com>,
Thierry Reding <thierry.reding@gmail.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH V2 09/21] clk: tegra: dfll: add protection for find_vdd_map APIs
Date: Fri, 14 Dec 2018 15:42:45 +0800 [thread overview]
Message-ID: <acaf37e4-e581-597f-fdcf-5f627e396b88@nvidia.com> (raw)
In-Reply-To: <a56194ce-ce96-8b3a-99e8-b4348db39f42@nvidia.com>
On 12/13/18 8:46 PM, Jon Hunter wrote:
>
> On 13/12/2018 09:34, Joseph Lo wrote:
>> The DFLL hardware supports both I2C and PWM based regulator. SW driver
>> only touches I2C regulator when generating LUT. And shouldn't touch it
>> anymore once the DFLL is enabled.
>
> I am not sure that the last two sentences are above are relevant and
> confused me a little at first. I would be tempted to drop them.
Indeed, they are irrelevant. Just want to describe that once we created
LUT table, it means we cached the regulator output table in driver. Then
we don't need to query voltage data from regulator again. This is
specific to the I2C mode only and happens in driver initialization time.
Which means the two APIs we add the WARN here maybe not really
necessary. Because this is suggested by Peter.
Hi Peter,
Just want to double confirm again, do we really need to add a WARN here?
Since we don't and shouldn't access these two APIs once the driver is
working, all the voltage query should be via LUT. So I think add WARN
here is not really necessary.
Thanks,
Joseph
>
>> This patch adds the protection for the APIs that only work with I2C mode
>> to avoid they could be called accidentally.
>>
>> Signed-off-by: Joseph Lo <josephl@nvidia.com>
>
> Furthermore, I would be tempted to squash this into patch #7. I am not
> sure another patch is warranted here.
>
> Cheers
> Jon
>
WARNING: multiple messages have this Message-ID (diff)
From: Joseph Lo <josephl@nvidia.com>
To: Jon Hunter <jonathanh@nvidia.com>,
Thierry Reding <thierry.reding@gmail.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
<linux-tegra@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: Re: [PATCH V2 09/21] clk: tegra: dfll: add protection for find_vdd_map APIs
Date: Fri, 14 Dec 2018 15:42:45 +0800 [thread overview]
Message-ID: <acaf37e4-e581-597f-fdcf-5f627e396b88@nvidia.com> (raw)
In-Reply-To: <a56194ce-ce96-8b3a-99e8-b4348db39f42@nvidia.com>
On 12/13/18 8:46 PM, Jon Hunter wrote:
>
> On 13/12/2018 09:34, Joseph Lo wrote:
>> The DFLL hardware supports both I2C and PWM based regulator. SW driver
>> only touches I2C regulator when generating LUT. And shouldn't touch it
>> anymore once the DFLL is enabled.
>
> I am not sure that the last two sentences are above are relevant and
> confused me a little at first. I would be tempted to drop them.
Indeed, they are irrelevant. Just want to describe that once we created
LUT table, it means we cached the regulator output table in driver. Then
we don't need to query voltage data from regulator again. This is
specific to the I2C mode only and happens in driver initialization time.
Which means the two APIs we add the WARN here maybe not really
necessary. Because this is suggested by Peter.
Hi Peter,
Just want to double confirm again, do we really need to add a WARN here?
Since we don't and shouldn't access these two APIs once the driver is
working, all the voltage query should be via LUT. So I think add WARN
here is not really necessary.
Thanks,
Joseph
>
>> This patch adds the protection for the APIs that only work with I2C mode
>> to avoid they could be called accidentally.
>>
>> Signed-off-by: Joseph Lo <josephl@nvidia.com>
>
> Furthermore, I would be tempted to squash this into patch #7. I am not
> sure another patch is warranted here.
>
> Cheers
> Jon
>
WARNING: multiple messages have this Message-ID (diff)
From: Joseph Lo <josephl@nvidia.com>
To: Jon Hunter <jonathanh@nvidia.com>,
Thierry Reding <thierry.reding@gmail.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH V2 09/21] clk: tegra: dfll: add protection for find_vdd_map APIs
Date: Fri, 14 Dec 2018 15:42:45 +0800 [thread overview]
Message-ID: <acaf37e4-e581-597f-fdcf-5f627e396b88@nvidia.com> (raw)
In-Reply-To: <a56194ce-ce96-8b3a-99e8-b4348db39f42@nvidia.com>
On 12/13/18 8:46 PM, Jon Hunter wrote:
>
> On 13/12/2018 09:34, Joseph Lo wrote:
>> The DFLL hardware supports both I2C and PWM based regulator. SW driver
>> only touches I2C regulator when generating LUT. And shouldn't touch it
>> anymore once the DFLL is enabled.
>
> I am not sure that the last two sentences are above are relevant and
> confused me a little at first. I would be tempted to drop them.
Indeed, they are irrelevant. Just want to describe that once we created
LUT table, it means we cached the regulator output table in driver. Then
we don't need to query voltage data from regulator again. This is
specific to the I2C mode only and happens in driver initialization time.
Which means the two APIs we add the WARN here maybe not really
necessary. Because this is suggested by Peter.
Hi Peter,
Just want to double confirm again, do we really need to add a WARN here?
Since we don't and shouldn't access these two APIs once the driver is
working, all the voltage query should be via LUT. So I think add WARN
here is not really necessary.
Thanks,
Joseph
>
>> This patch adds the protection for the APIs that only work with I2C mode
>> to avoid they could be called accidentally.
>>
>> Signed-off-by: Joseph Lo <josephl@nvidia.com>
>
> Furthermore, I would be tempted to squash this into patch #7. I am not
> sure another patch is warranted here.
>
> Cheers
> Jon
>
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next prev parent reply other threads:[~2018-12-14 7:42 UTC|newest]
Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-13 9:34 [PATCH V2 00/21] Tegra210 DFLL support Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 01/21] dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 02/21] dt-bindings: clock: tegra124-dfll: add Tegra210 support Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 03/21] dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 04/21] dt-bindings: cpufreq: tegra124: remove cpu_lp clock " Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 05/21] clk: tegra: dfll: registration for multiple SoCs Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 06/21] clk: tegra: dfll: CVB calculation alignment with the regulator Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 11:18 ` Jon Hunter
2018-12-13 11:18 ` Jon Hunter
2018-12-13 11:18 ` Jon Hunter
2018-12-14 7:08 ` Joseph Lo
2018-12-14 7:08 ` Joseph Lo
2018-12-14 7:08 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 07/21] clk: tegra: dfll: support PWM regulator control Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 11:41 ` Jon Hunter
2018-12-13 11:41 ` Jon Hunter
2018-12-13 11:41 ` Jon Hunter
2018-12-14 7:11 ` Joseph Lo
2018-12-14 7:11 ` Joseph Lo
2018-12-14 7:11 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 08/21] clk: tegra: dfll: round down voltages based on alignment Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 11:46 ` Jon Hunter
2018-12-13 11:46 ` Jon Hunter
2018-12-13 11:46 ` Jon Hunter
2018-12-14 7:18 ` Joseph Lo
2018-12-14 7:18 ` Joseph Lo
2018-12-14 7:18 ` Joseph Lo
2018-12-14 10:00 ` Jon Hunter
2018-12-14 10:00 ` Jon Hunter
2018-12-14 10:00 ` Jon Hunter
2018-12-13 9:34 ` [PATCH V2 09/21] clk: tegra: dfll: add protection for find_vdd_map APIs Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 12:46 ` Jon Hunter
2018-12-13 12:46 ` Jon Hunter
2018-12-13 12:46 ` Jon Hunter
2018-12-14 7:42 ` Joseph Lo [this message]
2018-12-14 7:42 ` Joseph Lo
2018-12-14 7:42 ` Joseph Lo
2018-12-17 11:38 ` Peter De Schrijver
2018-12-17 11:38 ` Peter De Schrijver
2018-12-17 11:38 ` Peter De Schrijver
2018-12-13 9:34 ` [PATCH V2 10/21] clk: tegra: dfll: add CVB tables for Tegra210 Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 12:50 ` Jon Hunter
2018-12-13 12:50 ` Jon Hunter
2018-12-13 12:50 ` Jon Hunter
2018-12-14 7:43 ` Joseph Lo
2018-12-14 7:43 ` Joseph Lo
2018-12-14 7:43 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 11/21] clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 12/21] cpufreq: tegra124: do not handle the CPU rail Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 10:49 ` Rafael J. Wysocki
2018-12-13 10:49 ` Rafael J. Wysocki
2018-12-13 10:49 ` Rafael J. Wysocki
2018-12-13 12:55 ` Jon Hunter
2018-12-13 12:55 ` Jon Hunter
2018-12-13 12:55 ` Jon Hunter
2018-12-18 5:34 ` Viresh Kumar
2018-12-18 5:34 ` Viresh Kumar
2018-12-18 5:34 ` Viresh Kumar
2018-12-13 9:34 ` [PATCH V2 13/21] cpufreq: tegra124: extend to support Tegra210 Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 14/21] cpufreq: dt-platdev: add Tegra210 to blacklist Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 13:09 ` Jon Hunter
2018-12-13 13:09 ` Jon Hunter
2018-12-13 13:09 ` Jon Hunter
2018-12-18 5:33 ` Viresh Kumar
2018-12-18 5:33 ` Viresh Kumar
2018-12-18 5:33 ` Viresh Kumar
2018-12-13 9:34 ` [PATCH V2 15/21] arm64: dts: tegra210: add DFLL clock Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 16/21] arm64: dts: tegra210: add CPU clocks Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 17/21] arm64: dts: tegra210-p2597: add pinmux for PWM-based DFLL support Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 18/21] arm64: dts: tegra210-p2371-2180: enable DFLL clock Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 13:11 ` Jon Hunter
2018-12-13 13:11 ` Jon Hunter
2018-12-13 13:11 ` Jon Hunter
2018-12-13 9:34 ` [PATCH V2 19/21] arm64: dts: tegra210-smaug: add CPU power rail regulator Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 20/21] arm64: dts: tegra210-smaug: enable DFLL clock Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` [PATCH V2 21/21] arm64: defconfig: Enable MAX8973 regulator Joseph Lo
2018-12-13 9:34 ` Joseph Lo
2018-12-13 9:34 ` Joseph Lo
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