* [PATCH 0/2] Exynos3250: add DT node and clock for UART2 and UART3
@ 2014-09-27 4:58 ` Pankaj Dubey
0 siblings, 0 replies; 16+ messages in thread
From: Pankaj Dubey @ 2014-09-27 4:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc
Cc: kgene.kim, tomasz.figa, robh+dt, linux, naushad, Pankaj Dubey
This patch series adds device tree node and missing clock support of UART2
and UART3 for Exynos3250. DT patch is dependent on clock patch.
Pankaj Dubey (2):
clk: samsung: exynos3250: add uart2/3 related clocks
arm: dts: exynos3250: add device node support for serial2 and serial3
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 21 +++++++++++++++++++++
arch/arm/boot/dts/exynos3250.dtsi | 24 ++++++++++++++++++++++++
drivers/clk/samsung/clk-exynos3250.c | 11 +++++++++++
include/dt-bindings/clock/exynos3250.h | 10 +++++++++-
4 files changed, 65 insertions(+), 1 deletion(-)
--
1.7.9.5
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 0/2] Exynos3250: add DT node and clock for UART2 and UART3
@ 2014-09-27 4:58 ` Pankaj Dubey
0 siblings, 0 replies; 16+ messages in thread
From: Pankaj Dubey @ 2014-09-27 4:58 UTC (permalink / raw)
To: linux-arm-kernel
This patch series adds device tree node and missing clock support of UART2
and UART3 for Exynos3250. DT patch is dependent on clock patch.
Pankaj Dubey (2):
clk: samsung: exynos3250: add uart2/3 related clocks
arm: dts: exynos3250: add device node support for serial2 and serial3
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 21 +++++++++++++++++++++
arch/arm/boot/dts/exynos3250.dtsi | 24 ++++++++++++++++++++++++
drivers/clk/samsung/clk-exynos3250.c | 11 +++++++++++
include/dt-bindings/clock/exynos3250.h | 10 +++++++++-
4 files changed, 65 insertions(+), 1 deletion(-)
--
1.7.9.5
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related clocks
2014-09-27 4:58 ` Pankaj Dubey
@ 2014-09-27 4:58 ` Pankaj Dubey
-1 siblings, 0 replies; 16+ messages in thread
From: Pankaj Dubey @ 2014-09-27 4:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc
Cc: kgene.kim, tomasz.figa, robh+dt, linux, naushad, Pankaj Dubey,
Mike Turquette, Sylwester Nawrocki
Exynos3250 has four UART channels UART0,1,2 and 3. This patch adds
missing clock entries for UART2 and UART3.
CC: Mike Turquette <mturquette@linaro.org>
CC: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
drivers/clk/samsung/clk-exynos3250.c | 11 +++++++++++
include/dt-bindings/clock/exynos3250.h | 10 +++++++++-
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index dc85f8e..0722fef 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -357,6 +357,8 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 3),
/* SRC_PERIL0 */
+ MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0, 12, 4),
+ MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
@@ -439,6 +441,8 @@ static struct samsung_div_clock div_clks[] __initdata = {
DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
/* DIV_PERIL0 */
+ DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
+ DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
@@ -601,6 +605,10 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
+ GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
+ GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
@@ -679,6 +687,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
+ GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
@@ -698,6 +707,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
+ GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0, 0),
+ GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
};
diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
index b535e9d..ffeb695 100644
--- a/include/dt-bindings/clock/exynos3250.h
+++ b/include/dt-bindings/clock/exynos3250.h
@@ -78,6 +78,8 @@
#define CLK_MOUT_CORE 58
#define CLK_MOUT_APLL 59
#define CLK_MOUT_ACLK_266_SUB 60
+#define CLK_MOUT_UART2 61
+#define CLK_MOUT_UART3 62
/* Dividers */
#define CLK_DIV_GPL 64
@@ -126,6 +128,8 @@
#define CLK_DIV_CORE 107
#define CLK_DIV_HPM 108
#define CLK_DIV_COPY 109
+#define CLK_DIV_UART2 110
+#define CLK_DIV_UART3 111
/* Gates */
#define CLK_ASYNC_G3D 128
@@ -222,6 +226,8 @@
#define CLK_BLOCK_MFC 219
#define CLK_BLOCK_CAM 220
#define CLK_SMIES 221
+#define CLK_UART2 222
+#define CLK_UART3 223
/* Special clocks */
#define CLK_SCLK_JPEG 224
@@ -248,11 +254,13 @@
#define CLK_SCLK_SPI0 245
#define CLK_SCLK_UART1 246
#define CLK_SCLK_UART0 247
+#define CLK_SCLK_UART2 248
+#define CLK_SCLK_UART3 249
/*
* Total number of clocks of main CMU.
* NOTE: Must be equal to last clock ID increased by one.
*/
-#define CLK_NR_CLKS 248
+#define CLK_NR_CLKS 250
#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related clocks
@ 2014-09-27 4:58 ` Pankaj Dubey
0 siblings, 0 replies; 16+ messages in thread
From: Pankaj Dubey @ 2014-09-27 4:58 UTC (permalink / raw)
To: linux-arm-kernel
Exynos3250 has four UART channels UART0,1,2 and 3. This patch adds
missing clock entries for UART2 and UART3.
CC: Mike Turquette <mturquette@linaro.org>
CC: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
drivers/clk/samsung/clk-exynos3250.c | 11 +++++++++++
include/dt-bindings/clock/exynos3250.h | 10 +++++++++-
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index dc85f8e..0722fef 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -357,6 +357,8 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 3),
/* SRC_PERIL0 */
+ MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0, 12, 4),
+ MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
@@ -439,6 +441,8 @@ static struct samsung_div_clock div_clks[] __initdata = {
DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
/* DIV_PERIL0 */
+ DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
+ DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
@@ -601,6 +605,10 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
+ GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
+ GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
@@ -679,6 +687,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
+ GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
@@ -698,6 +707,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
+ GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0, 0),
+ GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
};
diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
index b535e9d..ffeb695 100644
--- a/include/dt-bindings/clock/exynos3250.h
+++ b/include/dt-bindings/clock/exynos3250.h
@@ -78,6 +78,8 @@
#define CLK_MOUT_CORE 58
#define CLK_MOUT_APLL 59
#define CLK_MOUT_ACLK_266_SUB 60
+#define CLK_MOUT_UART2 61
+#define CLK_MOUT_UART3 62
/* Dividers */
#define CLK_DIV_GPL 64
@@ -126,6 +128,8 @@
#define CLK_DIV_CORE 107
#define CLK_DIV_HPM 108
#define CLK_DIV_COPY 109
+#define CLK_DIV_UART2 110
+#define CLK_DIV_UART3 111
/* Gates */
#define CLK_ASYNC_G3D 128
@@ -222,6 +226,8 @@
#define CLK_BLOCK_MFC 219
#define CLK_BLOCK_CAM 220
#define CLK_SMIES 221
+#define CLK_UART2 222
+#define CLK_UART3 223
/* Special clocks */
#define CLK_SCLK_JPEG 224
@@ -248,11 +254,13 @@
#define CLK_SCLK_SPI0 245
#define CLK_SCLK_UART1 246
#define CLK_SCLK_UART0 247
+#define CLK_SCLK_UART2 248
+#define CLK_SCLK_UART3 249
/*
* Total number of clocks of main CMU.
* NOTE: Must be equal to last clock ID increased by one.
*/
-#define CLK_NR_CLKS 248
+#define CLK_NR_CLKS 250
#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/2] arm: dts: exynos3250: add device node support for serial2 and serial3
2014-09-27 4:58 ` Pankaj Dubey
@ 2014-09-27 4:58 ` Pankaj Dubey
-1 siblings, 0 replies; 16+ messages in thread
From: Pankaj Dubey @ 2014-09-27 4:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc
Cc: kgene.kim, tomasz.figa, robh+dt, linux, naushad, Pankaj Dubey
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 21 +++++++++++++++++++++
arch/arm/boot/dts/exynos3250.dtsi | 24 ++++++++++++++++++++++++
2 files changed, 45 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index 47b92c1..9887bba 100644
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -97,6 +97,27 @@
samsung,pin-drv = <0>;
};
+ uart2_data: uart2-data {
+ samsung,pins = "gpa1-0", "gpa1-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart2_fctl: uart2-fctl {
+ samsung,pins = "gpa1-2", "gpa1-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart3_data: uart3-data {
+ samsung,pins = "gpa1-4", "gpa1-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
i2c2_bus: i2c2-bus {
samsung,pins = "gpa0-6", "gpa0-7";
samsung,pin-function = <3>;
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 9de1252..aaeb321 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -41,6 +41,8 @@
i2c7 = &i2c_7;
serial0 = &serial_0;
serial1 = &serial_1;
+ serial2 = &serial_2;
+ serial3 = &serial_3;
};
cpus {
@@ -346,6 +348,28 @@
status = "disabled";
};
+ serial_2: serial@13820000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13820000 0x100>;
+ interrupts = <0 111 0>;
+ clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
+ clock-names = "uart", "clk_uart_baud0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_data &uart2_fctl>;
+ status = "disabled";
+ };
+
+ serial_3: serial@13830000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13830000 0x100>;
+ interrupts = <0 112 0>;
+ clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>;
+ clock-names = "uart", "clk_uart_baud0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_data>;
+ status = "disabled";
+ };
+
i2c_0: i2c@13860000 {
#address-cells = <1>;
#size-cells = <0>;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/2] arm: dts: exynos3250: add device node support for serial2 and serial3
@ 2014-09-27 4:58 ` Pankaj Dubey
0 siblings, 0 replies; 16+ messages in thread
From: Pankaj Dubey @ 2014-09-27 4:58 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 21 +++++++++++++++++++++
arch/arm/boot/dts/exynos3250.dtsi | 24 ++++++++++++++++++++++++
2 files changed, 45 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index 47b92c1..9887bba 100644
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -97,6 +97,27 @@
samsung,pin-drv = <0>;
};
+ uart2_data: uart2-data {
+ samsung,pins = "gpa1-0", "gpa1-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart2_fctl: uart2-fctl {
+ samsung,pins = "gpa1-2", "gpa1-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart3_data: uart3-data {
+ samsung,pins = "gpa1-4", "gpa1-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
i2c2_bus: i2c2-bus {
samsung,pins = "gpa0-6", "gpa0-7";
samsung,pin-function = <3>;
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 9de1252..aaeb321 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -41,6 +41,8 @@
i2c7 = &i2c_7;
serial0 = &serial_0;
serial1 = &serial_1;
+ serial2 = &serial_2;
+ serial3 = &serial_3;
};
cpus {
@@ -346,6 +348,28 @@
status = "disabled";
};
+ serial_2: serial at 13820000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13820000 0x100>;
+ interrupts = <0 111 0>;
+ clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
+ clock-names = "uart", "clk_uart_baud0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_data &uart2_fctl>;
+ status = "disabled";
+ };
+
+ serial_3: serial at 13830000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13830000 0x100>;
+ interrupts = <0 112 0>;
+ clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>;
+ clock-names = "uart", "clk_uart_baud0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_data>;
+ status = "disabled";
+ };
+
i2c_0: i2c at 13860000 {
#address-cells = <1>;
#size-cells = <0>;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related clocks
2014-09-27 4:58 ` Pankaj Dubey
@ 2014-09-29 2:12 ` Chanwoo Choi
-1 siblings, 0 replies; 16+ messages in thread
From: Chanwoo Choi @ 2014-09-29 2:12 UTC (permalink / raw)
To: Pankaj Dubey
Cc: linux-arm-kernel, linux-samsung-soc, kgene.kim, tomasz.figa,
robh+dt, linux, naushad, Mike Turquette, Sylwester Nawrocki
Hi Pankaj,
On 09/27/2014 01:58 PM, Pankaj Dubey wrote:
> Exynos3250 has four UART channels UART0,1,2 and 3. This patch adds
> missing clock entries for UART2 and UART3.
>
> CC: Mike Turquette <mturquette@linaro.org>
> CC: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> ---
> drivers/clk/samsung/clk-exynos3250.c | 11 +++++++++++
> include/dt-bindings/clock/exynos3250.h | 10 +++++++++-
> 2 files changed, 20 insertions(+), 1 deletion(-)
Exynos3250 has only two UART(0,1) port. Exynos3250 don't support UART 2,3.
Thanks,
Chanwoo Choi
>
> diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
> index dc85f8e..0722fef 100644
> --- a/drivers/clk/samsung/clk-exynos3250.c
> +++ b/drivers/clk/samsung/clk-exynos3250.c
> @@ -357,6 +357,8 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
> MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 3),
>
> /* SRC_PERIL0 */
> + MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0, 12, 4),
> + MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
> MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
> MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
>
> @@ -439,6 +441,8 @@ static struct samsung_div_clock div_clks[] __initdata = {
> DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
>
> /* DIV_PERIL0 */
> + DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
> + DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
> DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
> DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
>
> @@ -601,6 +605,10 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
> GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
> GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
> + GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
> + GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
> GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
> @@ -679,6 +687,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
> GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
> GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
> GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
> + GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
> GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
> GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
> GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
> @@ -698,6 +707,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
> GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
> GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
> GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
> + GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0, 0),
> + GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
> GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
> GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
> };
> diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
> index b535e9d..ffeb695 100644
> --- a/include/dt-bindings/clock/exynos3250.h
> +++ b/include/dt-bindings/clock/exynos3250.h
> @@ -78,6 +78,8 @@
> #define CLK_MOUT_CORE 58
> #define CLK_MOUT_APLL 59
> #define CLK_MOUT_ACLK_266_SUB 60
> +#define CLK_MOUT_UART2 61
> +#define CLK_MOUT_UART3 62
>
> /* Dividers */
> #define CLK_DIV_GPL 64
> @@ -126,6 +128,8 @@
> #define CLK_DIV_CORE 107
> #define CLK_DIV_HPM 108
> #define CLK_DIV_COPY 109
> +#define CLK_DIV_UART2 110
> +#define CLK_DIV_UART3 111
>
> /* Gates */
> #define CLK_ASYNC_G3D 128
> @@ -222,6 +226,8 @@
> #define CLK_BLOCK_MFC 219
> #define CLK_BLOCK_CAM 220
> #define CLK_SMIES 221
> +#define CLK_UART2 222
> +#define CLK_UART3 223
>
> /* Special clocks */
> #define CLK_SCLK_JPEG 224
> @@ -248,11 +254,13 @@
> #define CLK_SCLK_SPI0 245
> #define CLK_SCLK_UART1 246
> #define CLK_SCLK_UART0 247
> +#define CLK_SCLK_UART2 248
> +#define CLK_SCLK_UART3 249
>
> /*
> * Total number of clocks of main CMU.
> * NOTE: Must be equal to last clock ID increased by one.
> */
> -#define CLK_NR_CLKS 248
> +#define CLK_NR_CLKS 250
>
> #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related clocks
@ 2014-09-29 2:12 ` Chanwoo Choi
0 siblings, 0 replies; 16+ messages in thread
From: Chanwoo Choi @ 2014-09-29 2:12 UTC (permalink / raw)
To: linux-arm-kernel
Hi Pankaj,
On 09/27/2014 01:58 PM, Pankaj Dubey wrote:
> Exynos3250 has four UART channels UART0,1,2 and 3. This patch adds
> missing clock entries for UART2 and UART3.
>
> CC: Mike Turquette <mturquette@linaro.org>
> CC: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> ---
> drivers/clk/samsung/clk-exynos3250.c | 11 +++++++++++
> include/dt-bindings/clock/exynos3250.h | 10 +++++++++-
> 2 files changed, 20 insertions(+), 1 deletion(-)
Exynos3250 has only two UART(0,1) port. Exynos3250 don't support UART 2,3.
Thanks,
Chanwoo Choi
>
> diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
> index dc85f8e..0722fef 100644
> --- a/drivers/clk/samsung/clk-exynos3250.c
> +++ b/drivers/clk/samsung/clk-exynos3250.c
> @@ -357,6 +357,8 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
> MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 3),
>
> /* SRC_PERIL0 */
> + MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0, 12, 4),
> + MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
> MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
> MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
>
> @@ -439,6 +441,8 @@ static struct samsung_div_clock div_clks[] __initdata = {
> DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
>
> /* DIV_PERIL0 */
> + DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
> + DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
> DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
> DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
>
> @@ -601,6 +605,10 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
> GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
> GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
> + GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
> + GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
> GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
> @@ -679,6 +687,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
> GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
> GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
> GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
> + GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
> GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
> GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
> GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
> @@ -698,6 +707,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
> GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
> GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
> GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
> + GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0, 0),
> + GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
> GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
> GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
> };
> diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
> index b535e9d..ffeb695 100644
> --- a/include/dt-bindings/clock/exynos3250.h
> +++ b/include/dt-bindings/clock/exynos3250.h
> @@ -78,6 +78,8 @@
> #define CLK_MOUT_CORE 58
> #define CLK_MOUT_APLL 59
> #define CLK_MOUT_ACLK_266_SUB 60
> +#define CLK_MOUT_UART2 61
> +#define CLK_MOUT_UART3 62
>
> /* Dividers */
> #define CLK_DIV_GPL 64
> @@ -126,6 +128,8 @@
> #define CLK_DIV_CORE 107
> #define CLK_DIV_HPM 108
> #define CLK_DIV_COPY 109
> +#define CLK_DIV_UART2 110
> +#define CLK_DIV_UART3 111
>
> /* Gates */
> #define CLK_ASYNC_G3D 128
> @@ -222,6 +226,8 @@
> #define CLK_BLOCK_MFC 219
> #define CLK_BLOCK_CAM 220
> #define CLK_SMIES 221
> +#define CLK_UART2 222
> +#define CLK_UART3 223
>
> /* Special clocks */
> #define CLK_SCLK_JPEG 224
> @@ -248,11 +254,13 @@
> #define CLK_SCLK_SPI0 245
> #define CLK_SCLK_UART1 246
> #define CLK_SCLK_UART0 247
> +#define CLK_SCLK_UART2 248
> +#define CLK_SCLK_UART3 249
>
> /*
> * Total number of clocks of main CMU.
> * NOTE: Must be equal to last clock ID increased by one.
> */
> -#define CLK_NR_CLKS 248
> +#define CLK_NR_CLKS 250
>
> #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related clocks
2014-09-29 2:12 ` Chanwoo Choi
@ 2014-09-29 2:47 ` Pankaj Dubey
-1 siblings, 0 replies; 16+ messages in thread
From: Pankaj Dubey @ 2014-09-29 2:47 UTC (permalink / raw)
To: 'Chanwoo Choi'
Cc: linux-arm-kernel, linux-samsung-soc, kgene.kim, tomasz.figa,
robh+dt, linux, naushad, 'Mike Turquette',
'Sylwester Nawrocki'
Hi Chanwoo,
On Monday, September 29, 2014 7:42 AM, Chanwoo Choi wrote,
> To: Pankaj Dubey
> Cc: linux-arm-kernel@lists.infradead.org;
linux-samsung-soc@vger.kernel.org;
> kgene.kim@samsung.com; tomasz.figa@gmail.com; robh+dt@kernel.org;
> linux@arm.linux.org.uk; naushad@samsung.com; Mike Turquette; Sylwester
> Nawrocki
> Subject: Re: [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related
clocks
>
> Hi Pankaj,
>
> On 09/27/2014 01:58 PM, Pankaj Dubey wrote:
> > Exynos3250 has four UART channels UART0,1,2 and 3. This patch adds
> > missing clock entries for UART2 and UART3.
> >
> > CC: Mike Turquette <mturquette@linaro.org>
> > CC: Sylwester Nawrocki <s.nawrocki@samsung.com>
> > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> > ---
> > drivers/clk/samsung/clk-exynos3250.c | 11 +++++++++++
> > include/dt-bindings/clock/exynos3250.h | 10 +++++++++-
> > 2 files changed, 20 insertions(+), 1 deletion(-)
>
> Exynos3250 has only two UART(0,1) port. Exynos3250 don't support UART 2,3.
>
As per Exynos3250 user manual that I have with me it supports UART(0,1,2,3).
It has been mentioned
in UART Chapter as well as CMU IP details also mentioned about the clock
entries. We have tested it
also on Espresso3250 board which is based on Exynos3250 SoC.
Thanks,
Pankaj Dubey
> Thanks,
> Chanwoo Choi
>
> >
> > diff --git a/drivers/clk/samsung/clk-exynos3250.c
> > b/drivers/clk/samsung/clk-exynos3250.c
> > index dc85f8e..0722fef 100644
> > --- a/drivers/clk/samsung/clk-exynos3250.c
> > +++ b/drivers/clk/samsung/clk-exynos3250.c
> > @@ -357,6 +357,8 @@ static struct samsung_mux_clock mux_clks[]
__initdata =
> {
> > MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 3),
> >
> > /* SRC_PERIL0 */
> > + MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0,
> 12, 4),
> > + MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8,
> 4),
> > MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4,
> 4),
> > MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0,
> 4),
> >
> > @@ -439,6 +441,8 @@ static struct samsung_div_clock div_clks[]
__initdata = {
> > DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
> >
> > /* DIV_PERIL0 */
> > + DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
> > + DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
> > DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
> > DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
> >
> > @@ -601,6 +605,10 @@ static struct samsung_gate_clock gate_clks[]
__initdata
> = {
> > GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
> > GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
> > GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
> > + GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
> > + GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
> > + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
> > + GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
> > GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
> > GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
> > GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", @@ -679,6 +687,7
> @@
> > static struct samsung_gate_clock gate_clks[] __initdata = {
> > GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0,
> 0),
> > GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12,
> 0, 0),
> > GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
> > + GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0,
> 0),
> > GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0,
> 0),
> > GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0,
> 0),
> > GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
> @@
> > -698,6 +707,8 @@ static struct samsung_gate_clock gate_clks[] __initdata
= {
> > GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
> > GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
> > GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
> > + GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0, 0),
> > + GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
> > GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
> > GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
> > }; diff --git a/include/dt-bindings/clock/exynos3250.h
> > b/include/dt-bindings/clock/exynos3250.h
> > index b535e9d..ffeb695 100644
> > --- a/include/dt-bindings/clock/exynos3250.h
> > +++ b/include/dt-bindings/clock/exynos3250.h
> > @@ -78,6 +78,8 @@
> > #define CLK_MOUT_CORE 58
> > #define CLK_MOUT_APLL 59
> > #define CLK_MOUT_ACLK_266_SUB 60
> > +#define CLK_MOUT_UART2 61
> > +#define CLK_MOUT_UART3 62
> >
> > /* Dividers */
> > #define CLK_DIV_GPL 64
> > @@ -126,6 +128,8 @@
> > #define CLK_DIV_CORE 107
> > #define CLK_DIV_HPM 108
> > #define CLK_DIV_COPY 109
> > +#define CLK_DIV_UART2 110
> > +#define CLK_DIV_UART3 111
> >
> > /* Gates */
> > #define CLK_ASYNC_G3D 128
> > @@ -222,6 +226,8 @@
> > #define CLK_BLOCK_MFC 219
> > #define CLK_BLOCK_CAM 220
> > #define CLK_SMIES 221
> > +#define CLK_UART2 222
> > +#define CLK_UART3 223
> >
> > /* Special clocks */
> > #define CLK_SCLK_JPEG 224
> > @@ -248,11 +254,13 @@
> > #define CLK_SCLK_SPI0 245
> > #define CLK_SCLK_UART1 246
> > #define CLK_SCLK_UART0 247
> > +#define CLK_SCLK_UART2 248
> > +#define CLK_SCLK_UART3 249
> >
> > /*
> > * Total number of clocks of main CMU.
> > * NOTE: Must be equal to last clock ID increased by one.
> > */
> > -#define CLK_NR_CLKS 248
> > +#define CLK_NR_CLKS 250
> >
> > #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
> */
> >
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related clocks
@ 2014-09-29 2:47 ` Pankaj Dubey
0 siblings, 0 replies; 16+ messages in thread
From: Pankaj Dubey @ 2014-09-29 2:47 UTC (permalink / raw)
To: linux-arm-kernel
Hi Chanwoo,
On Monday, September 29, 2014 7:42 AM, Chanwoo Choi wrote,
> To: Pankaj Dubey
> Cc: linux-arm-kernel at lists.infradead.org;
linux-samsung-soc at vger.kernel.org;
> kgene.kim at samsung.com; tomasz.figa at gmail.com; robh+dt at kernel.org;
> linux at arm.linux.org.uk; naushad at samsung.com; Mike Turquette; Sylwester
> Nawrocki
> Subject: Re: [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related
clocks
>
> Hi Pankaj,
>
> On 09/27/2014 01:58 PM, Pankaj Dubey wrote:
> > Exynos3250 has four UART channels UART0,1,2 and 3. This patch adds
> > missing clock entries for UART2 and UART3.
> >
> > CC: Mike Turquette <mturquette@linaro.org>
> > CC: Sylwester Nawrocki <s.nawrocki@samsung.com>
> > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> > ---
> > drivers/clk/samsung/clk-exynos3250.c | 11 +++++++++++
> > include/dt-bindings/clock/exynos3250.h | 10 +++++++++-
> > 2 files changed, 20 insertions(+), 1 deletion(-)
>
> Exynos3250 has only two UART(0,1) port. Exynos3250 don't support UART 2,3.
>
As per Exynos3250 user manual that I have with me it supports UART(0,1,2,3).
It has been mentioned
in UART Chapter as well as CMU IP details also mentioned about the clock
entries. We have tested it
also on Espresso3250 board which is based on Exynos3250 SoC.
Thanks,
Pankaj Dubey
> Thanks,
> Chanwoo Choi
>
> >
> > diff --git a/drivers/clk/samsung/clk-exynos3250.c
> > b/drivers/clk/samsung/clk-exynos3250.c
> > index dc85f8e..0722fef 100644
> > --- a/drivers/clk/samsung/clk-exynos3250.c
> > +++ b/drivers/clk/samsung/clk-exynos3250.c
> > @@ -357,6 +357,8 @@ static struct samsung_mux_clock mux_clks[]
__initdata =
> {
> > MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 3),
> >
> > /* SRC_PERIL0 */
> > + MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0,
> 12, 4),
> > + MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8,
> 4),
> > MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4,
> 4),
> > MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0,
> 4),
> >
> > @@ -439,6 +441,8 @@ static struct samsung_div_clock div_clks[]
__initdata = {
> > DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
> >
> > /* DIV_PERIL0 */
> > + DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
> > + DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
> > DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
> > DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
> >
> > @@ -601,6 +605,10 @@ static struct samsung_gate_clock gate_clks[]
__initdata
> = {
> > GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
> > GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
> > GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
> > + GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
> > + GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
> > + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
> > + GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
> > GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
> > GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
> > GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", @@ -679,6 +687,7
> @@
> > static struct samsung_gate_clock gate_clks[] __initdata = {
> > GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0,
> 0),
> > GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12,
> 0, 0),
> > GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
> > + GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0,
> 0),
> > GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0,
> 0),
> > GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0,
> 0),
> > GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
> @@
> > -698,6 +707,8 @@ static struct samsung_gate_clock gate_clks[] __initdata
= {
> > GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
> > GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
> > GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
> > + GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0, 0),
> > + GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
> > GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
> > GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
> > }; diff --git a/include/dt-bindings/clock/exynos3250.h
> > b/include/dt-bindings/clock/exynos3250.h
> > index b535e9d..ffeb695 100644
> > --- a/include/dt-bindings/clock/exynos3250.h
> > +++ b/include/dt-bindings/clock/exynos3250.h
> > @@ -78,6 +78,8 @@
> > #define CLK_MOUT_CORE 58
> > #define CLK_MOUT_APLL 59
> > #define CLK_MOUT_ACLK_266_SUB 60
> > +#define CLK_MOUT_UART2 61
> > +#define CLK_MOUT_UART3 62
> >
> > /* Dividers */
> > #define CLK_DIV_GPL 64
> > @@ -126,6 +128,8 @@
> > #define CLK_DIV_CORE 107
> > #define CLK_DIV_HPM 108
> > #define CLK_DIV_COPY 109
> > +#define CLK_DIV_UART2 110
> > +#define CLK_DIV_UART3 111
> >
> > /* Gates */
> > #define CLK_ASYNC_G3D 128
> > @@ -222,6 +226,8 @@
> > #define CLK_BLOCK_MFC 219
> > #define CLK_BLOCK_CAM 220
> > #define CLK_SMIES 221
> > +#define CLK_UART2 222
> > +#define CLK_UART3 223
> >
> > /* Special clocks */
> > #define CLK_SCLK_JPEG 224
> > @@ -248,11 +254,13 @@
> > #define CLK_SCLK_SPI0 245
> > #define CLK_SCLK_UART1 246
> > #define CLK_SCLK_UART0 247
> > +#define CLK_SCLK_UART2 248
> > +#define CLK_SCLK_UART3 249
> >
> > /*
> > * Total number of clocks of main CMU.
> > * NOTE: Must be equal to last clock ID increased by one.
> > */
> > -#define CLK_NR_CLKS 248
> > +#define CLK_NR_CLKS 250
> >
> > #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
> */
> >
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related clocks
2014-09-29 2:47 ` Pankaj Dubey
@ 2014-09-29 3:37 ` Kyungmin Park
-1 siblings, 0 replies; 16+ messages in thread
From: Kyungmin Park @ 2014-09-29 3:37 UTC (permalink / raw)
To: Pankaj Dubey
Cc: Chanwoo Choi, Kukjin Kim, Russell King - ARM Linux, naushad,
Tomasz Figa, linux-samsung-soc, robh+dt, Sylwester Nawrocki,
Mike Turquette, arm-linux
On Mon, Sep 29, 2014 at 11:47 AM, Pankaj Dubey <pankaj.dubey@samsung.com> wrote:
> Hi Chanwoo,
>
> On Monday, September 29, 2014 7:42 AM, Chanwoo Choi wrote,
>> To: Pankaj Dubey
>> Cc: linux-arm-kernel@lists.infradead.org;
> linux-samsung-soc@vger.kernel.org;
>> kgene.kim@samsung.com; tomasz.figa@gmail.com; robh+dt@kernel.org;
>> linux@arm.linux.org.uk; naushad@samsung.com; Mike Turquette; Sylwester
>> Nawrocki
>> Subject: Re: [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related
> clocks
>>
>> Hi Pankaj,
>>
>> On 09/27/2014 01:58 PM, Pankaj Dubey wrote:
>> > Exynos3250 has four UART channels UART0,1,2 and 3. This patch adds
>> > missing clock entries for UART2 and UART3.
>> >
>> > CC: Mike Turquette <mturquette@linaro.org>
>> > CC: Sylwester Nawrocki <s.nawrocki@samsung.com>
>> > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
>> > ---
>> > drivers/clk/samsung/clk-exynos3250.c | 11 +++++++++++
>> > include/dt-bindings/clock/exynos3250.h | 10 +++++++++-
>> > 2 files changed, 20 insertions(+), 1 deletion(-)
>>
>> Exynos3250 has only two UART(0,1) port. Exynos3250 don't support UART 2,3.
>>
>
> As per Exynos3250 user manual that I have with me it supports UART(0,1,2,3).
> It has been mentioned
which UM do you use? There are two UARTs at rev0.01
> in UART Chapter as well as CMU IP details also mentioned about the clock
> entries. We have tested it
> also on Espresso3250 board which is based on Exynos3250 SoC.
I can't find it at my UM.
Kyungmin Park
>
> Thanks,
> Pankaj Dubey
>
>> Thanks,
>> Chanwoo Choi
>>
>> >
>> > diff --git a/drivers/clk/samsung/clk-exynos3250.c
>> > b/drivers/clk/samsung/clk-exynos3250.c
>> > index dc85f8e..0722fef 100644
>> > --- a/drivers/clk/samsung/clk-exynos3250.c
>> > +++ b/drivers/clk/samsung/clk-exynos3250.c
>> > @@ -357,6 +357,8 @@ static struct samsung_mux_clock mux_clks[]
> __initdata =
>> {
>> > MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 3),
>> >
>> > /* SRC_PERIL0 */
>> > + MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0,
>> 12, 4),
>> > + MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8,
>> 4),
>> > MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4,
>> 4),
>> > MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0,
>> 4),
>> >
>> > @@ -439,6 +441,8 @@ static struct samsung_div_clock div_clks[]
> __initdata = {
>> > DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
>> >
>> > /* DIV_PERIL0 */
>> > + DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
>> > + DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
>> > DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
>> > DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
>> >
>> > @@ -601,6 +605,10 @@ static struct samsung_gate_clock gate_clks[]
> __initdata
>> = {
>> > GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
>> > GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
>> > GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
>> > + GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
>> > + GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
>> > + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
>> > + GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
>> > GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
>> > GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
>> > GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", @@ -679,6 +687,7
>> @@
>> > static struct samsung_gate_clock gate_clks[] __initdata = {
>> > GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0,
>> 0),
>> > GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12,
>> 0, 0),
>> > GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
>> > + GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0,
>> 0),
>> > GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0,
>> 0),
>> > GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0,
>> 0),
>> > GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
>> @@
>> > -698,6 +707,8 @@ static struct samsung_gate_clock gate_clks[] __initdata
> = {
>> > GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
>> > GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
>> > GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
>> > + GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0, 0),
>> > + GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
>> > GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
>> > GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
>> > }; diff --git a/include/dt-bindings/clock/exynos3250.h
>> > b/include/dt-bindings/clock/exynos3250.h
>> > index b535e9d..ffeb695 100644
>> > --- a/include/dt-bindings/clock/exynos3250.h
>> > +++ b/include/dt-bindings/clock/exynos3250.h
>> > @@ -78,6 +78,8 @@
>> > #define CLK_MOUT_CORE 58
>> > #define CLK_MOUT_APLL 59
>> > #define CLK_MOUT_ACLK_266_SUB 60
>> > +#define CLK_MOUT_UART2 61
>> > +#define CLK_MOUT_UART3 62
>> >
>> > /* Dividers */
>> > #define CLK_DIV_GPL 64
>> > @@ -126,6 +128,8 @@
>> > #define CLK_DIV_CORE 107
>> > #define CLK_DIV_HPM 108
>> > #define CLK_DIV_COPY 109
>> > +#define CLK_DIV_UART2 110
>> > +#define CLK_DIV_UART3 111
>> >
>> > /* Gates */
>> > #define CLK_ASYNC_G3D 128
>> > @@ -222,6 +226,8 @@
>> > #define CLK_BLOCK_MFC 219
>> > #define CLK_BLOCK_CAM 220
>> > #define CLK_SMIES 221
>> > +#define CLK_UART2 222
>> > +#define CLK_UART3 223
>> >
>> > /* Special clocks */
>> > #define CLK_SCLK_JPEG 224
>> > @@ -248,11 +254,13 @@
>> > #define CLK_SCLK_SPI0 245
>> > #define CLK_SCLK_UART1 246
>> > #define CLK_SCLK_UART0 247
>> > +#define CLK_SCLK_UART2 248
>> > +#define CLK_SCLK_UART3 249
>> >
>> > /*
>> > * Total number of clocks of main CMU.
>> > * NOTE: Must be equal to last clock ID increased by one.
>> > */
>> > -#define CLK_NR_CLKS 248
>> > +#define CLK_NR_CLKS 250
>> >
>> > #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
>> */
>> >
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related clocks
@ 2014-09-29 3:37 ` Kyungmin Park
0 siblings, 0 replies; 16+ messages in thread
From: Kyungmin Park @ 2014-09-29 3:37 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Sep 29, 2014 at 11:47 AM, Pankaj Dubey <pankaj.dubey@samsung.com> wrote:
> Hi Chanwoo,
>
> On Monday, September 29, 2014 7:42 AM, Chanwoo Choi wrote,
>> To: Pankaj Dubey
>> Cc: linux-arm-kernel at lists.infradead.org;
> linux-samsung-soc at vger.kernel.org;
>> kgene.kim at samsung.com; tomasz.figa at gmail.com; robh+dt at kernel.org;
>> linux at arm.linux.org.uk; naushad at samsung.com; Mike Turquette; Sylwester
>> Nawrocki
>> Subject: Re: [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related
> clocks
>>
>> Hi Pankaj,
>>
>> On 09/27/2014 01:58 PM, Pankaj Dubey wrote:
>> > Exynos3250 has four UART channels UART0,1,2 and 3. This patch adds
>> > missing clock entries for UART2 and UART3.
>> >
>> > CC: Mike Turquette <mturquette@linaro.org>
>> > CC: Sylwester Nawrocki <s.nawrocki@samsung.com>
>> > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
>> > ---
>> > drivers/clk/samsung/clk-exynos3250.c | 11 +++++++++++
>> > include/dt-bindings/clock/exynos3250.h | 10 +++++++++-
>> > 2 files changed, 20 insertions(+), 1 deletion(-)
>>
>> Exynos3250 has only two UART(0,1) port. Exynos3250 don't support UART 2,3.
>>
>
> As per Exynos3250 user manual that I have with me it supports UART(0,1,2,3).
> It has been mentioned
which UM do you use? There are two UARTs at rev0.01
> in UART Chapter as well as CMU IP details also mentioned about the clock
> entries. We have tested it
> also on Espresso3250 board which is based on Exynos3250 SoC.
I can't find it at my UM.
Kyungmin Park
>
> Thanks,
> Pankaj Dubey
>
>> Thanks,
>> Chanwoo Choi
>>
>> >
>> > diff --git a/drivers/clk/samsung/clk-exynos3250.c
>> > b/drivers/clk/samsung/clk-exynos3250.c
>> > index dc85f8e..0722fef 100644
>> > --- a/drivers/clk/samsung/clk-exynos3250.c
>> > +++ b/drivers/clk/samsung/clk-exynos3250.c
>> > @@ -357,6 +357,8 @@ static struct samsung_mux_clock mux_clks[]
> __initdata =
>> {
>> > MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 3),
>> >
>> > /* SRC_PERIL0 */
>> > + MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0,
>> 12, 4),
>> > + MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8,
>> 4),
>> > MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4,
>> 4),
>> > MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0,
>> 4),
>> >
>> > @@ -439,6 +441,8 @@ static struct samsung_div_clock div_clks[]
> __initdata = {
>> > DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
>> >
>> > /* DIV_PERIL0 */
>> > + DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
>> > + DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
>> > DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
>> > DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
>> >
>> > @@ -601,6 +605,10 @@ static struct samsung_gate_clock gate_clks[]
> __initdata
>> = {
>> > GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
>> > GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
>> > GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
>> > + GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
>> > + GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
>> > + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
>> > + GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
>> > GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
>> > GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
>> > GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", @@ -679,6 +687,7
>> @@
>> > static struct samsung_gate_clock gate_clks[] __initdata = {
>> > GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0,
>> 0),
>> > GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12,
>> 0, 0),
>> > GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
>> > + GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0,
>> 0),
>> > GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0,
>> 0),
>> > GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0,
>> 0),
>> > GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
>> @@
>> > -698,6 +707,8 @@ static struct samsung_gate_clock gate_clks[] __initdata
> = {
>> > GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
>> > GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
>> > GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
>> > + GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0, 0),
>> > + GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
>> > GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
>> > GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
>> > }; diff --git a/include/dt-bindings/clock/exynos3250.h
>> > b/include/dt-bindings/clock/exynos3250.h
>> > index b535e9d..ffeb695 100644
>> > --- a/include/dt-bindings/clock/exynos3250.h
>> > +++ b/include/dt-bindings/clock/exynos3250.h
>> > @@ -78,6 +78,8 @@
>> > #define CLK_MOUT_CORE 58
>> > #define CLK_MOUT_APLL 59
>> > #define CLK_MOUT_ACLK_266_SUB 60
>> > +#define CLK_MOUT_UART2 61
>> > +#define CLK_MOUT_UART3 62
>> >
>> > /* Dividers */
>> > #define CLK_DIV_GPL 64
>> > @@ -126,6 +128,8 @@
>> > #define CLK_DIV_CORE 107
>> > #define CLK_DIV_HPM 108
>> > #define CLK_DIV_COPY 109
>> > +#define CLK_DIV_UART2 110
>> > +#define CLK_DIV_UART3 111
>> >
>> > /* Gates */
>> > #define CLK_ASYNC_G3D 128
>> > @@ -222,6 +226,8 @@
>> > #define CLK_BLOCK_MFC 219
>> > #define CLK_BLOCK_CAM 220
>> > #define CLK_SMIES 221
>> > +#define CLK_UART2 222
>> > +#define CLK_UART3 223
>> >
>> > /* Special clocks */
>> > #define CLK_SCLK_JPEG 224
>> > @@ -248,11 +254,13 @@
>> > #define CLK_SCLK_SPI0 245
>> > #define CLK_SCLK_UART1 246
>> > #define CLK_SCLK_UART0 247
>> > +#define CLK_SCLK_UART2 248
>> > +#define CLK_SCLK_UART3 249
>> >
>> > /*
>> > * Total number of clocks of main CMU.
>> > * NOTE: Must be equal to last clock ID increased by one.
>> > */
>> > -#define CLK_NR_CLKS 248
>> > +#define CLK_NR_CLKS 250
>> >
>> > #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
>> */
>> >
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related clocks
2014-09-29 3:37 ` Kyungmin Park
@ 2014-09-29 7:22 ` Pankaj Dubey
-1 siblings, 0 replies; 16+ messages in thread
From: Pankaj Dubey @ 2014-09-29 7:22 UTC (permalink / raw)
To: 'Kyungmin Park'
Cc: 'Chanwoo Choi', 'Kukjin Kim',
'Russell King - ARM Linux',
naushad, 'Tomasz Figa', 'linux-samsung-soc',
robh+dt, 'Sylwester Nawrocki', 'Mike Turquette',
'arm-linux'
Hi,
On Monday, September 29, 2014 9:07 AM, Kyungmin Park wrote,
> To: Pankaj Dubey
> Cc: Chanwoo Choi; Kukjin Kim; Russell King - ARM Linux;
naushad@samsung.com;
> Tomasz Figa; linux-samsung-soc; robh+dt@kernel.org; Sylwester Nawrocki;
Mike
> Turquette; arm-linux
> Subject: Re: [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related
clocks
>
> On Mon, Sep 29, 2014 at 11:47 AM, Pankaj Dubey <pankaj.dubey@samsung.com>
> wrote:
> > Hi Chanwoo,
> >
> > On Monday, September 29, 2014 7:42 AM, Chanwoo Choi wrote,
> >> To: Pankaj Dubey
> >> Cc: linux-arm-kernel@lists.infradead.org;
> > linux-samsung-soc@vger.kernel.org;
> >> kgene.kim@samsung.com; tomasz.figa@gmail.com; robh+dt@kernel.org;
> >> linux@arm.linux.org.uk; naushad@samsung.com; Mike Turquette;
> >> Sylwester Nawrocki
> >> Subject: Re: [PATCH 1/2] clk: samsung: exynos3250: add uart2/3
> >> related
> > clocks
> >>
> >> Hi Pankaj,
> >>
> >> On 09/27/2014 01:58 PM, Pankaj Dubey wrote:
> >> > Exynos3250 has four UART channels UART0,1,2 and 3. This patch adds
> >> > missing clock entries for UART2 and UART3.
> >> >
> >> > CC: Mike Turquette <mturquette@linaro.org>
> >> > CC: Sylwester Nawrocki <s.nawrocki@samsung.com>
> >> > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> >> > ---
> >> > drivers/clk/samsung/clk-exynos3250.c | 11 +++++++++++
> >> > include/dt-bindings/clock/exynos3250.h | 10 +++++++++-
> >> > 2 files changed, 20 insertions(+), 1 deletion(-)
> >>
> >> Exynos3250 has only two UART(0,1) port. Exynos3250 don't support UART
> 2,3.
> >>
> >
> > As per Exynos3250 user manual that I have with me it supports
UART(0,1,2,3).
> > It has been mentioned
> which UM do you use? There are two UARTs at rev0.01
>
I am using Rev 2.0.
Thanks,
Pankaj Dubey
> > in UART Chapter as well as CMU IP details also mentioned about the
> > clock entries. We have tested it also on Espresso3250 board which is
> > based on Exynos3250 SoC.
> I can't find it at my UM.
>
> Kyungmin Park
> >
> > Thanks,
> > Pankaj Dubey
> >
> >> Thanks,
> >> Chanwoo Choi
> >>
> >> >
> >> > diff --git a/drivers/clk/samsung/clk-exynos3250.c
> >> > b/drivers/clk/samsung/clk-exynos3250.c
> >> > index dc85f8e..0722fef 100644
> >> > --- a/drivers/clk/samsung/clk-exynos3250.c
> >> > +++ b/drivers/clk/samsung/clk-exynos3250.c
> >> > @@ -357,6 +357,8 @@ static struct samsung_mux_clock mux_clks[]
> > __initdata =
> >> {
> >> > MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0,
> 3),
> >> >
> >> > /* SRC_PERIL0 */
> >> > + MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0,
> >> 12, 4),
> >> > + MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0,
> 8,
> >> 4),
> >> > MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0,
> 4,
> >> 4),
> >> > MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0,
> 0,
> >> 4),
> >> >
> >> > @@ -439,6 +441,8 @@ static struct samsung_div_clock div_clks[]
> > __initdata = {
> >> > DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
> >> >
> >> > /* DIV_PERIL0 */
> >> > + DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12,
> 4),
> >> > + DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8,
> >> > + 4),
> >> > DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
> >> > DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0,
> >> > 4),
> >> >
> >> > @@ -601,6 +605,10 @@ static struct samsung_gate_clock gate_clks[]
> > __initdata
> >> = {
> >> > GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
> >> > GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
> >> > GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
> >> > + GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
> >> > + GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
> >> > + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
> >> > + GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
> >> > GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
> >> > GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
> >> > GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", @@ -679,6
> >> > +687,7
> >> @@
> >> > static struct samsung_gate_clock gate_clks[] __initdata = {
> >> > GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13,
> 0,
> >> 0),
> >> > GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12,
> >> 0, 0),
> >> > GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0,
> >> > 0),
> >> > + GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7,
> 0,
> >> 0),
> >> > GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6,
> 0,
> >> 0),
> >> > GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5,
> 0,
> >> 0),
> >> > GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0,
> >> > 0),
> >> @@
> >> > -698,6 +707,8 @@ static struct samsung_gate_clock gate_clks[]
> >> > __initdata
> > = {
> >> > GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
> >> > GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
> >> > GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
> >> > + GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0,
> 0),
> >> > + GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0,
> >> > + 0),
> >> > GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
> >> > GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0,
> >> > 0), }; diff --git a/include/dt-bindings/clock/exynos3250.h
> >> > b/include/dt-bindings/clock/exynos3250.h
> >> > index b535e9d..ffeb695 100644
> >> > --- a/include/dt-bindings/clock/exynos3250.h
> >> > +++ b/include/dt-bindings/clock/exynos3250.h
> >> > @@ -78,6 +78,8 @@
> >> > #define CLK_MOUT_CORE 58
> >> > #define CLK_MOUT_APLL 59
> >> > #define CLK_MOUT_ACLK_266_SUB 60
> >> > +#define CLK_MOUT_UART2 61
> >> > +#define CLK_MOUT_UART3 62
> >> >
> >> > /* Dividers */
> >> > #define CLK_DIV_GPL 64
> >> > @@ -126,6 +128,8 @@
> >> > #define CLK_DIV_CORE 107
> >> > #define CLK_DIV_HPM 108
> >> > #define CLK_DIV_COPY 109
> >> > +#define CLK_DIV_UART2 110
> >> > +#define CLK_DIV_UART3 111
> >> >
> >> > /* Gates */
> >> > #define CLK_ASYNC_G3D 128
> >> > @@ -222,6 +226,8 @@
> >> > #define CLK_BLOCK_MFC 219
> >> > #define CLK_BLOCK_CAM 220
> >> > #define CLK_SMIES 221
> >> > +#define CLK_UART2 222
> >> > +#define CLK_UART3 223
> >> >
> >> > /* Special clocks */
> >> > #define CLK_SCLK_JPEG 224
> >> > @@ -248,11 +254,13 @@
> >> > #define CLK_SCLK_SPI0 245
> >> > #define CLK_SCLK_UART1 246
> >> > #define CLK_SCLK_UART0 247
> >> > +#define CLK_SCLK_UART2 248
> >> > +#define CLK_SCLK_UART3 249
> >> >
> >> > /*
> >> > * Total number of clocks of main CMU.
> >> > * NOTE: Must be equal to last clock ID increased by one.
> >> > */
> >> > -#define CLK_NR_CLKS 248
> >> > +#define CLK_NR_CLKS 250
> >> >
> >> > #endif /*
> _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
> >> */
> >> >
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related clocks
@ 2014-09-29 7:22 ` Pankaj Dubey
0 siblings, 0 replies; 16+ messages in thread
From: Pankaj Dubey @ 2014-09-29 7:22 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Monday, September 29, 2014 9:07 AM, Kyungmin Park wrote,
> To: Pankaj Dubey
> Cc: Chanwoo Choi; Kukjin Kim; Russell King - ARM Linux;
naushad at samsung.com;
> Tomasz Figa; linux-samsung-soc; robh+dt at kernel.org; Sylwester Nawrocki;
Mike
> Turquette; arm-linux
> Subject: Re: [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related
clocks
>
> On Mon, Sep 29, 2014 at 11:47 AM, Pankaj Dubey <pankaj.dubey@samsung.com>
> wrote:
> > Hi Chanwoo,
> >
> > On Monday, September 29, 2014 7:42 AM, Chanwoo Choi wrote,
> >> To: Pankaj Dubey
> >> Cc: linux-arm-kernel at lists.infradead.org;
> > linux-samsung-soc at vger.kernel.org;
> >> kgene.kim at samsung.com; tomasz.figa at gmail.com; robh+dt at kernel.org;
> >> linux at arm.linux.org.uk; naushad at samsung.com; Mike Turquette;
> >> Sylwester Nawrocki
> >> Subject: Re: [PATCH 1/2] clk: samsung: exynos3250: add uart2/3
> >> related
> > clocks
> >>
> >> Hi Pankaj,
> >>
> >> On 09/27/2014 01:58 PM, Pankaj Dubey wrote:
> >> > Exynos3250 has four UART channels UART0,1,2 and 3. This patch adds
> >> > missing clock entries for UART2 and UART3.
> >> >
> >> > CC: Mike Turquette <mturquette@linaro.org>
> >> > CC: Sylwester Nawrocki <s.nawrocki@samsung.com>
> >> > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> >> > ---
> >> > drivers/clk/samsung/clk-exynos3250.c | 11 +++++++++++
> >> > include/dt-bindings/clock/exynos3250.h | 10 +++++++++-
> >> > 2 files changed, 20 insertions(+), 1 deletion(-)
> >>
> >> Exynos3250 has only two UART(0,1) port. Exynos3250 don't support UART
> 2,3.
> >>
> >
> > As per Exynos3250 user manual that I have with me it supports
UART(0,1,2,3).
> > It has been mentioned
> which UM do you use? There are two UARTs at rev0.01
>
I am using Rev 2.0.
Thanks,
Pankaj Dubey
> > in UART Chapter as well as CMU IP details also mentioned about the
> > clock entries. We have tested it also on Espresso3250 board which is
> > based on Exynos3250 SoC.
> I can't find it at my UM.
>
> Kyungmin Park
> >
> > Thanks,
> > Pankaj Dubey
> >
> >> Thanks,
> >> Chanwoo Choi
> >>
> >> >
> >> > diff --git a/drivers/clk/samsung/clk-exynos3250.c
> >> > b/drivers/clk/samsung/clk-exynos3250.c
> >> > index dc85f8e..0722fef 100644
> >> > --- a/drivers/clk/samsung/clk-exynos3250.c
> >> > +++ b/drivers/clk/samsung/clk-exynos3250.c
> >> > @@ -357,6 +357,8 @@ static struct samsung_mux_clock mux_clks[]
> > __initdata =
> >> {
> >> > MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0,
> 3),
> >> >
> >> > /* SRC_PERIL0 */
> >> > + MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0,
> >> 12, 4),
> >> > + MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0,
> 8,
> >> 4),
> >> > MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0,
> 4,
> >> 4),
> >> > MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0,
> 0,
> >> 4),
> >> >
> >> > @@ -439,6 +441,8 @@ static struct samsung_div_clock div_clks[]
> > __initdata = {
> >> > DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
> >> >
> >> > /* DIV_PERIL0 */
> >> > + DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12,
> 4),
> >> > + DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8,
> >> > + 4),
> >> > DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
> >> > DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0,
> >> > 4),
> >> >
> >> > @@ -601,6 +605,10 @@ static struct samsung_gate_clock gate_clks[]
> > __initdata
> >> = {
> >> > GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
> >> > GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
> >> > GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
> >> > + GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
> >> > + GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
> >> > + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
> >> > + GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
> >> > GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
> >> > GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
> >> > GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", @@ -679,6
> >> > +687,7
> >> @@
> >> > static struct samsung_gate_clock gate_clks[] __initdata = {
> >> > GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13,
> 0,
> >> 0),
> >> > GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12,
> >> 0, 0),
> >> > GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0,
> >> > 0),
> >> > + GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7,
> 0,
> >> 0),
> >> > GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6,
> 0,
> >> 0),
> >> > GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5,
> 0,
> >> 0),
> >> > GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0,
> >> > 0),
> >> @@
> >> > -698,6 +707,8 @@ static struct samsung_gate_clock gate_clks[]
> >> > __initdata
> > = {
> >> > GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
> >> > GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
> >> > GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
> >> > + GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0,
> 0),
> >> > + GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0,
> >> > + 0),
> >> > GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
> >> > GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0,
> >> > 0), }; diff --git a/include/dt-bindings/clock/exynos3250.h
> >> > b/include/dt-bindings/clock/exynos3250.h
> >> > index b535e9d..ffeb695 100644
> >> > --- a/include/dt-bindings/clock/exynos3250.h
> >> > +++ b/include/dt-bindings/clock/exynos3250.h
> >> > @@ -78,6 +78,8 @@
> >> > #define CLK_MOUT_CORE 58
> >> > #define CLK_MOUT_APLL 59
> >> > #define CLK_MOUT_ACLK_266_SUB 60
> >> > +#define CLK_MOUT_UART2 61
> >> > +#define CLK_MOUT_UART3 62
> >> >
> >> > /* Dividers */
> >> > #define CLK_DIV_GPL 64
> >> > @@ -126,6 +128,8 @@
> >> > #define CLK_DIV_CORE 107
> >> > #define CLK_DIV_HPM 108
> >> > #define CLK_DIV_COPY 109
> >> > +#define CLK_DIV_UART2 110
> >> > +#define CLK_DIV_UART3 111
> >> >
> >> > /* Gates */
> >> > #define CLK_ASYNC_G3D 128
> >> > @@ -222,6 +226,8 @@
> >> > #define CLK_BLOCK_MFC 219
> >> > #define CLK_BLOCK_CAM 220
> >> > #define CLK_SMIES 221
> >> > +#define CLK_UART2 222
> >> > +#define CLK_UART3 223
> >> >
> >> > /* Special clocks */
> >> > #define CLK_SCLK_JPEG 224
> >> > @@ -248,11 +254,13 @@
> >> > #define CLK_SCLK_SPI0 245
> >> > #define CLK_SCLK_UART1 246
> >> > #define CLK_SCLK_UART0 247
> >> > +#define CLK_SCLK_UART2 248
> >> > +#define CLK_SCLK_UART3 249
> >> >
> >> > /*
> >> > * Total number of clocks of main CMU.
> >> > * NOTE: Must be equal to last clock ID increased by one.
> >> > */
> >> > -#define CLK_NR_CLKS 248
> >> > +#define CLK_NR_CLKS 250
> >> >
> >> > #endif /*
> _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
> >> */
> >> >
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related clocks
2014-09-29 7:22 ` Pankaj Dubey
@ 2014-09-29 8:47 ` Kyungmin Park
-1 siblings, 0 replies; 16+ messages in thread
From: Kyungmin Park @ 2014-09-29 8:47 UTC (permalink / raw)
To: Pankaj Dubey
Cc: Chanwoo Choi, Kukjin Kim, Russell King - ARM Linux, naushad,
Tomasz Figa, linux-samsung-soc, robh+dt, Sylwester Nawrocki,
Mike Turquette, arm-linux
On Mon, Sep 29, 2014 at 4:22 PM, Pankaj Dubey <pankaj.dubey@samsung.com> wrote:
> Hi,
>
> On Monday, September 29, 2014 9:07 AM, Kyungmin Park wrote,
>> To: Pankaj Dubey
>> Cc: Chanwoo Choi; Kukjin Kim; Russell King - ARM Linux;
> naushad@samsung.com;
>> Tomasz Figa; linux-samsung-soc; robh+dt@kernel.org; Sylwester Nawrocki;
> Mike
>> Turquette; arm-linux
>> Subject: Re: [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related
> clocks
>>
>> On Mon, Sep 29, 2014 at 11:47 AM, Pankaj Dubey <pankaj.dubey@samsung.com>
>> wrote:
>> > Hi Chanwoo,
>> >
>> > On Monday, September 29, 2014 7:42 AM, Chanwoo Choi wrote,
>> >> To: Pankaj Dubey
>> >> Cc: linux-arm-kernel@lists.infradead.org;
>> > linux-samsung-soc@vger.kernel.org;
>> >> kgene.kim@samsung.com; tomasz.figa@gmail.com; robh+dt@kernel.org;
>> >> linux@arm.linux.org.uk; naushad@samsung.com; Mike Turquette;
>> >> Sylwester Nawrocki
>> >> Subject: Re: [PATCH 1/2] clk: samsung: exynos3250: add uart2/3
>> >> related
>> > clocks
>> >>
>> >> Hi Pankaj,
>> >>
>> >> On 09/27/2014 01:58 PM, Pankaj Dubey wrote:
>> >> > Exynos3250 has four UART channels UART0,1,2 and 3. This patch adds
>> >> > missing clock entries for UART2 and UART3.
>> >> >
>> >> > CC: Mike Turquette <mturquette@linaro.org>
>> >> > CC: Sylwester Nawrocki <s.nawrocki@samsung.com>
>> >> > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
>> >> > ---
>> >> > drivers/clk/samsung/clk-exynos3250.c | 11 +++++++++++
>> >> > include/dt-bindings/clock/exynos3250.h | 10 +++++++++-
>> >> > 2 files changed, 20 insertions(+), 1 deletion(-)
>> >>
>> >> Exynos3250 has only two UART(0,1) port. Exynos3250 don't support UART
>> 2,3.
>> >>
>> >
>> > As per Exynos3250 user manual that I have with me it supports
> UART(0,1,2,3).
>> > It has been mentioned
>> which UM do you use? There are two UARTs at rev0.01
>>
>
> I am using Rev 2.0.
I received the latest manual from LSI. but it's still v1.40.
>
> Thanks,
> Pankaj Dubey
>
>
>> > in UART Chapter as well as CMU IP details also mentioned about the
>> > clock entries. We have tested it also on Espresso3250 board which is
>> > based on Exynos3250 SoC.
>> I can't find it at my UM.
>>
>> Kyungmin Park
>> >
>> > Thanks,
>> > Pankaj Dubey
>> >
>> >> Thanks,
>> >> Chanwoo Choi
>> >>
>> >> >
>> >> > diff --git a/drivers/clk/samsung/clk-exynos3250.c
>> >> > b/drivers/clk/samsung/clk-exynos3250.c
>> >> > index dc85f8e..0722fef 100644
>> >> > --- a/drivers/clk/samsung/clk-exynos3250.c
>> >> > +++ b/drivers/clk/samsung/clk-exynos3250.c
>> >> > @@ -357,6 +357,8 @@ static struct samsung_mux_clock mux_clks[]
>> > __initdata =
>> >> {
>> >> > MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0,
>> 3),
>> >> >
>> >> > /* SRC_PERIL0 */
>> >> > + MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0,
>> >> 12, 4),
>> >> > + MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0,
>> 8,
>> >> 4),
>> >> > MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0,
>> 4,
>> >> 4),
>> >> > MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0,
>> 0,
>> >> 4),
>> >> >
>> >> > @@ -439,6 +441,8 @@ static struct samsung_div_clock div_clks[]
>> > __initdata = {
>> >> > DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
>> >> >
>> >> > /* DIV_PERIL0 */
>> >> > + DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12,
>> 4),
>> >> > + DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8,
>> >> > + 4),
>> >> > DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
>> >> > DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0,
>> >> > 4),
>> >> >
>> >> > @@ -601,6 +605,10 @@ static struct samsung_gate_clock gate_clks[]
>> > __initdata
>> >> = {
>> >> > GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
>> >> > GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
>> >> > GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
>> >> > + GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
>> >> > + GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
>> >> > + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
>> >> > + GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
>> >> > GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
>> >> > GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
>> >> > GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", @@ -679,6
>> >> > +687,7
>> >> @@
>> >> > static struct samsung_gate_clock gate_clks[] __initdata = {
>> >> > GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13,
>> 0,
>> >> 0),
>> >> > GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12,
>> >> 0, 0),
>> >> > GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0,
>> >> > 0),
>> >> > + GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7,
>> 0,
>> >> 0),
>> >> > GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6,
>> 0,
>> >> 0),
>> >> > GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5,
>> 0,
>> >> 0),
>> >> > GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0,
>> >> > 0),
>> >> @@
>> >> > -698,6 +707,8 @@ static struct samsung_gate_clock gate_clks[]
>> >> > __initdata
>> > = {
>> >> > GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
>> >> > GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
>> >> > GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
>> >> > + GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0,
>> 0),
>> >> > + GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0,
>> >> > + 0),
>> >> > GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
>> >> > GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0,
>> >> > 0), }; diff --git a/include/dt-bindings/clock/exynos3250.h
>> >> > b/include/dt-bindings/clock/exynos3250.h
>> >> > index b535e9d..ffeb695 100644
>> >> > --- a/include/dt-bindings/clock/exynos3250.h
>> >> > +++ b/include/dt-bindings/clock/exynos3250.h
>> >> > @@ -78,6 +78,8 @@
>> >> > #define CLK_MOUT_CORE 58
>> >> > #define CLK_MOUT_APLL 59
>> >> > #define CLK_MOUT_ACLK_266_SUB 60
>> >> > +#define CLK_MOUT_UART2 61
>> >> > +#define CLK_MOUT_UART3 62
>> >> >
>> >> > /* Dividers */
>> >> > #define CLK_DIV_GPL 64
>> >> > @@ -126,6 +128,8 @@
>> >> > #define CLK_DIV_CORE 107
>> >> > #define CLK_DIV_HPM 108
>> >> > #define CLK_DIV_COPY 109
>> >> > +#define CLK_DIV_UART2 110
>> >> > +#define CLK_DIV_UART3 111
>> >> >
>> >> > /* Gates */
>> >> > #define CLK_ASYNC_G3D 128
>> >> > @@ -222,6 +226,8 @@
>> >> > #define CLK_BLOCK_MFC 219
>> >> > #define CLK_BLOCK_CAM 220
>> >> > #define CLK_SMIES 221
>> >> > +#define CLK_UART2 222
>> >> > +#define CLK_UART3 223
>> >> >
>> >> > /* Special clocks */
>> >> > #define CLK_SCLK_JPEG 224
>> >> > @@ -248,11 +254,13 @@
>> >> > #define CLK_SCLK_SPI0 245
>> >> > #define CLK_SCLK_UART1 246
>> >> > #define CLK_SCLK_UART0 247
>> >> > +#define CLK_SCLK_UART2 248
>> >> > +#define CLK_SCLK_UART3 249
>> >> >
>> >> > /*
>> >> > * Total number of clocks of main CMU.
>> >> > * NOTE: Must be equal to last clock ID increased by one.
>> >> > */
>> >> > -#define CLK_NR_CLKS 248
>> >> > +#define CLK_NR_CLKS 250
>> >> >
>> >> > #endif /*
>> _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
>> >> */
>> >> >
>> >
>> >
>> > _______________________________________________
>> > linux-arm-kernel mailing list
>> > linux-arm-kernel@lists.infradead.org
>> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related clocks
@ 2014-09-29 8:47 ` Kyungmin Park
0 siblings, 0 replies; 16+ messages in thread
From: Kyungmin Park @ 2014-09-29 8:47 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Sep 29, 2014 at 4:22 PM, Pankaj Dubey <pankaj.dubey@samsung.com> wrote:
> Hi,
>
> On Monday, September 29, 2014 9:07 AM, Kyungmin Park wrote,
>> To: Pankaj Dubey
>> Cc: Chanwoo Choi; Kukjin Kim; Russell King - ARM Linux;
> naushad at samsung.com;
>> Tomasz Figa; linux-samsung-soc; robh+dt at kernel.org; Sylwester Nawrocki;
> Mike
>> Turquette; arm-linux
>> Subject: Re: [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related
> clocks
>>
>> On Mon, Sep 29, 2014 at 11:47 AM, Pankaj Dubey <pankaj.dubey@samsung.com>
>> wrote:
>> > Hi Chanwoo,
>> >
>> > On Monday, September 29, 2014 7:42 AM, Chanwoo Choi wrote,
>> >> To: Pankaj Dubey
>> >> Cc: linux-arm-kernel at lists.infradead.org;
>> > linux-samsung-soc at vger.kernel.org;
>> >> kgene.kim at samsung.com; tomasz.figa at gmail.com; robh+dt at kernel.org;
>> >> linux at arm.linux.org.uk; naushad at samsung.com; Mike Turquette;
>> >> Sylwester Nawrocki
>> >> Subject: Re: [PATCH 1/2] clk: samsung: exynos3250: add uart2/3
>> >> related
>> > clocks
>> >>
>> >> Hi Pankaj,
>> >>
>> >> On 09/27/2014 01:58 PM, Pankaj Dubey wrote:
>> >> > Exynos3250 has four UART channels UART0,1,2 and 3. This patch adds
>> >> > missing clock entries for UART2 and UART3.
>> >> >
>> >> > CC: Mike Turquette <mturquette@linaro.org>
>> >> > CC: Sylwester Nawrocki <s.nawrocki@samsung.com>
>> >> > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
>> >> > ---
>> >> > drivers/clk/samsung/clk-exynos3250.c | 11 +++++++++++
>> >> > include/dt-bindings/clock/exynos3250.h | 10 +++++++++-
>> >> > 2 files changed, 20 insertions(+), 1 deletion(-)
>> >>
>> >> Exynos3250 has only two UART(0,1) port. Exynos3250 don't support UART
>> 2,3.
>> >>
>> >
>> > As per Exynos3250 user manual that I have with me it supports
> UART(0,1,2,3).
>> > It has been mentioned
>> which UM do you use? There are two UARTs at rev0.01
>>
>
> I am using Rev 2.0.
I received the latest manual from LSI. but it's still v1.40.
>
> Thanks,
> Pankaj Dubey
>
>
>> > in UART Chapter as well as CMU IP details also mentioned about the
>> > clock entries. We have tested it also on Espresso3250 board which is
>> > based on Exynos3250 SoC.
>> I can't find it at my UM.
>>
>> Kyungmin Park
>> >
>> > Thanks,
>> > Pankaj Dubey
>> >
>> >> Thanks,
>> >> Chanwoo Choi
>> >>
>> >> >
>> >> > diff --git a/drivers/clk/samsung/clk-exynos3250.c
>> >> > b/drivers/clk/samsung/clk-exynos3250.c
>> >> > index dc85f8e..0722fef 100644
>> >> > --- a/drivers/clk/samsung/clk-exynos3250.c
>> >> > +++ b/drivers/clk/samsung/clk-exynos3250.c
>> >> > @@ -357,6 +357,8 @@ static struct samsung_mux_clock mux_clks[]
>> > __initdata =
>> >> {
>> >> > MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0,
>> 3),
>> >> >
>> >> > /* SRC_PERIL0 */
>> >> > + MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0,
>> >> 12, 4),
>> >> > + MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0,
>> 8,
>> >> 4),
>> >> > MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0,
>> 4,
>> >> 4),
>> >> > MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0,
>> 0,
>> >> 4),
>> >> >
>> >> > @@ -439,6 +441,8 @@ static struct samsung_div_clock div_clks[]
>> > __initdata = {
>> >> > DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
>> >> >
>> >> > /* DIV_PERIL0 */
>> >> > + DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12,
>> 4),
>> >> > + DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8,
>> >> > + 4),
>> >> > DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
>> >> > DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0,
>> >> > 4),
>> >> >
>> >> > @@ -601,6 +605,10 @@ static struct samsung_gate_clock gate_clks[]
>> > __initdata
>> >> = {
>> >> > GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
>> >> > GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
>> >> > GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
>> >> > + GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
>> >> > + GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
>> >> > + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
>> >> > + GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
>> >> > GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
>> >> > GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
>> >> > GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", @@ -679,6
>> >> > +687,7
>> >> @@
>> >> > static struct samsung_gate_clock gate_clks[] __initdata = {
>> >> > GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13,
>> 0,
>> >> 0),
>> >> > GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12,
>> >> 0, 0),
>> >> > GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0,
>> >> > 0),
>> >> > + GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7,
>> 0,
>> >> 0),
>> >> > GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6,
>> 0,
>> >> 0),
>> >> > GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5,
>> 0,
>> >> 0),
>> >> > GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0,
>> >> > 0),
>> >> @@
>> >> > -698,6 +707,8 @@ static struct samsung_gate_clock gate_clks[]
>> >> > __initdata
>> > = {
>> >> > GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
>> >> > GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
>> >> > GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
>> >> > + GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0,
>> 0),
>> >> > + GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0,
>> >> > + 0),
>> >> > GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
>> >> > GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0,
>> >> > 0), }; diff --git a/include/dt-bindings/clock/exynos3250.h
>> >> > b/include/dt-bindings/clock/exynos3250.h
>> >> > index b535e9d..ffeb695 100644
>> >> > --- a/include/dt-bindings/clock/exynos3250.h
>> >> > +++ b/include/dt-bindings/clock/exynos3250.h
>> >> > @@ -78,6 +78,8 @@
>> >> > #define CLK_MOUT_CORE 58
>> >> > #define CLK_MOUT_APLL 59
>> >> > #define CLK_MOUT_ACLK_266_SUB 60
>> >> > +#define CLK_MOUT_UART2 61
>> >> > +#define CLK_MOUT_UART3 62
>> >> >
>> >> > /* Dividers */
>> >> > #define CLK_DIV_GPL 64
>> >> > @@ -126,6 +128,8 @@
>> >> > #define CLK_DIV_CORE 107
>> >> > #define CLK_DIV_HPM 108
>> >> > #define CLK_DIV_COPY 109
>> >> > +#define CLK_DIV_UART2 110
>> >> > +#define CLK_DIV_UART3 111
>> >> >
>> >> > /* Gates */
>> >> > #define CLK_ASYNC_G3D 128
>> >> > @@ -222,6 +226,8 @@
>> >> > #define CLK_BLOCK_MFC 219
>> >> > #define CLK_BLOCK_CAM 220
>> >> > #define CLK_SMIES 221
>> >> > +#define CLK_UART2 222
>> >> > +#define CLK_UART3 223
>> >> >
>> >> > /* Special clocks */
>> >> > #define CLK_SCLK_JPEG 224
>> >> > @@ -248,11 +254,13 @@
>> >> > #define CLK_SCLK_SPI0 245
>> >> > #define CLK_SCLK_UART1 246
>> >> > #define CLK_SCLK_UART0 247
>> >> > +#define CLK_SCLK_UART2 248
>> >> > +#define CLK_SCLK_UART3 249
>> >> >
>> >> > /*
>> >> > * Total number of clocks of main CMU.
>> >> > * NOTE: Must be equal to last clock ID increased by one.
>> >> > */
>> >> > -#define CLK_NR_CLKS 248
>> >> > +#define CLK_NR_CLKS 250
>> >> >
>> >> > #endif /*
>> _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
>> >> */
>> >> >
>> >
>> >
>> > _______________________________________________
>> > linux-arm-kernel mailing list
>> > linux-arm-kernel at lists.infradead.org
>> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2014-09-29 8:47 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-09-27 4:58 [PATCH 0/2] Exynos3250: add DT node and clock for UART2 and UART3 Pankaj Dubey
2014-09-27 4:58 ` Pankaj Dubey
2014-09-27 4:58 ` [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related clocks Pankaj Dubey
2014-09-27 4:58 ` Pankaj Dubey
2014-09-29 2:12 ` Chanwoo Choi
2014-09-29 2:12 ` Chanwoo Choi
2014-09-29 2:47 ` Pankaj Dubey
2014-09-29 2:47 ` Pankaj Dubey
2014-09-29 3:37 ` Kyungmin Park
2014-09-29 3:37 ` Kyungmin Park
2014-09-29 7:22 ` Pankaj Dubey
2014-09-29 7:22 ` Pankaj Dubey
2014-09-29 8:47 ` Kyungmin Park
2014-09-29 8:47 ` Kyungmin Park
2014-09-27 4:58 ` [PATCH 2/2] arm: dts: exynos3250: add device node support for serial2 and serial3 Pankaj Dubey
2014-09-27 4:58 ` Pankaj Dubey
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