[PATCH 0/6] Add support for UFS controller found in FSD SoC

[PATCH 0/6] Add support for UFS controller found in FSD SoC

[Alim Akhtar]

This series adds support for UFS controller found in FSD SoC.
The HCI is almost same as found on other Exynos SoCs with minor
differences. This also adds the required UFS-PHY driver changes.

Patch 2/6: common change to handle different CDR offsets


Alim Akhtar (6):
  dt-bindings: phy: Add FSD UFS PHY bindings
  phy: samsung-ufs: move cdr offset to drvdata
  phy: samsung-ufs: add support for FSD ufs phy driver
  dt-bindings: ufs: exynos-ufs: add fsd compatible
  ufs: host: ufs-exynos: add support for fsd ufs hci
  arm64: dts: fsd: add ufs device node

 .../bindings/phy/samsung,ufs-phy.yaml         |   1 +
 .../bindings/ufs/samsung,exynos-ufs.yaml      |   1 +
 arch/arm64/boot/dts/tesla/fsd-evb.dts         |   4 +
 arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi    |  14 ++
 arch/arm64/boot/dts/tesla/fsd.dtsi            |  29 ++++
 drivers/phy/samsung/Makefile                  |   1 +
 drivers/phy/samsung/phy-exynos7-ufs.c         |   3 +
 drivers/phy/samsung/phy-exynosautov9-ufs.c    |   2 +
 drivers/phy/samsung/phy-fsd-ufs.c             |  63 ++++++++
 drivers/phy/samsung/phy-samsung-ufs.c         |   6 +-
 drivers/phy/samsung/phy-samsung-ufs.h         |   3 +-
 drivers/ufs/host/ufs-exynos.c                 | 143 +++++++++++++++++-
 12 files changed, 267 insertions(+), 3 deletions(-)
 create mode 100644 drivers/phy/samsung/phy-fsd-ufs.c


base-commit: d3fde8ff50ab265749704bd7fbcf70d35235421f
-- 
2.25.1

[PATCH 0/6] Add support for UFS controller found in FSD SoC

[Alim Akhtar]

This series adds support for UFS controller found in FSD SoC.
The HCI is almost same as found on other Exynos SoCs with minor
differences. This also adds the required UFS-PHY driver changes.

Patch 2/6: common change to handle different CDR offsets


Alim Akhtar (6):
  dt-bindings: phy: Add FSD UFS PHY bindings
  phy: samsung-ufs: move cdr offset to drvdata
  phy: samsung-ufs: add support for FSD ufs phy driver
  dt-bindings: ufs: exynos-ufs: add fsd compatible
  ufs: host: ufs-exynos: add support for fsd ufs hci
  arm64: dts: fsd: add ufs device node

 .../bindings/phy/samsung,ufs-phy.yaml         |   1 +
 .../bindings/ufs/samsung,exynos-ufs.yaml      |   1 +
 arch/arm64/boot/dts/tesla/fsd-evb.dts         |   4 +
 arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi    |  14 ++
 arch/arm64/boot/dts/tesla/fsd.dtsi            |  29 ++++
 drivers/phy/samsung/Makefile                  |   1 +
 drivers/phy/samsung/phy-exynos7-ufs.c         |   3 +
 drivers/phy/samsung/phy-exynosautov9-ufs.c    |   2 +
 drivers/phy/samsung/phy-fsd-ufs.c             |  63 ++++++++
 drivers/phy/samsung/phy-samsung-ufs.c         |   6 +-
 drivers/phy/samsung/phy-samsung-ufs.h         |   3 +-
 drivers/ufs/host/ufs-exynos.c                 | 143 +++++++++++++++++-
 12 files changed, 267 insertions(+), 3 deletions(-)
 create mode 100644 drivers/phy/samsung/phy-fsd-ufs.c


base-commit: d3fde8ff50ab265749704bd7fbcf70d35235421f
-- 
2.25.1


-- 
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

[PATCH 0/6] Add support for UFS controller found in FSD SoC

[Alim Akhtar]

This series adds support for UFS controller found in FSD SoC.
The HCI is almost same as found on other Exynos SoCs with minor
differences. This also adds the required UFS-PHY driver changes.

Patch 2/6: common change to handle different CDR offsets


Alim Akhtar (6):
  dt-bindings: phy: Add FSD UFS PHY bindings
  phy: samsung-ufs: move cdr offset to drvdata
  phy: samsung-ufs: add support for FSD ufs phy driver
  dt-bindings: ufs: exynos-ufs: add fsd compatible
  ufs: host: ufs-exynos: add support for fsd ufs hci
  arm64: dts: fsd: add ufs device node

 .../bindings/phy/samsung,ufs-phy.yaml         |   1 +
 .../bindings/ufs/samsung,exynos-ufs.yaml      |   1 +
 arch/arm64/boot/dts/tesla/fsd-evb.dts         |   4 +
 arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi    |  14 ++
 arch/arm64/boot/dts/tesla/fsd.dtsi            |  29 ++++
 drivers/phy/samsung/Makefile                  |   1 +
 drivers/phy/samsung/phy-exynos7-ufs.c         |   3 +
 drivers/phy/samsung/phy-exynosautov9-ufs.c    |   2 +
 drivers/phy/samsung/phy-fsd-ufs.c             |  63 ++++++++
 drivers/phy/samsung/phy-samsung-ufs.c         |   6 +-
 drivers/phy/samsung/phy-samsung-ufs.h         |   3 +-
 drivers/ufs/host/ufs-exynos.c                 | 143 +++++++++++++++++-
 12 files changed, 267 insertions(+), 3 deletions(-)
 create mode 100644 drivers/phy/samsung/phy-fsd-ufs.c


base-commit: d3fde8ff50ab265749704bd7fbcf70d35235421f
-- 
2.25.1


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 1/6] dt-bindings: phy: Add FSD UFS PHY bindings

[Alim Akhtar]

Adds tesla,fsd-ufs-phy compatible for Tesla FSD SoC

Cc: linux-fsd@tesla.com
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
index f6ed1a005e7a..ee354bf37c64 100644
--- a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -17,6 +17,7 @@ properties:
     enum:
       - samsung,exynos7-ufs-phy
       - samsung,exynosautov9-ufs-phy
+      - tesla,fsd-ufs-phy
 
   reg:
     maxItems: 1
-- 
2.25.1

[PATCH 1/6] dt-bindings: phy: Add FSD UFS PHY bindings

[Alim Akhtar]

Adds tesla,fsd-ufs-phy compatible for Tesla FSD SoC

Cc: linux-fsd@tesla.com
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
index f6ed1a005e7a..ee354bf37c64 100644
--- a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -17,6 +17,7 @@ properties:
     enum:
       - samsung,exynos7-ufs-phy
       - samsung,exynosautov9-ufs-phy
+      - tesla,fsd-ufs-phy
 
   reg:
     maxItems: 1
-- 
2.25.1


-- 
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

[PATCH 1/6] dt-bindings: phy: Add FSD UFS PHY bindings

[Alim Akhtar]

Adds tesla,fsd-ufs-phy compatible for Tesla FSD SoC

Cc: linux-fsd@tesla.com
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
index f6ed1a005e7a..ee354bf37c64 100644
--- a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -17,6 +17,7 @@ properties:
     enum:
       - samsung,exynos7-ufs-phy
       - samsung,exynosautov9-ufs-phy
+      - tesla,fsd-ufs-phy
 
   reg:
     maxItems: 1
-- 
2.25.1


_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 2/6] phy: samsung-ufs: move cdr offset to drvdata

[Alim Akhtar]

Move CDR lock offset to drv data so that it can
be extended for other SoCs which are having CDR
lock at different register offset.

Cc: linux-fsd@tesla.com
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/phy/samsung/phy-exynos7-ufs.c      | 3 +++
 drivers/phy/samsung/phy-exynosautov9-ufs.c | 2 ++
 drivers/phy/samsung/phy-samsung-ufs.c      | 3 ++-
 drivers/phy/samsung/phy-samsung-ufs.h      | 2 +-
 4 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c b/drivers/phy/samsung/phy-exynos7-ufs.c
index 7c9008e163db..d1a37273cb1f 100644
--- a/drivers/phy/samsung/phy-exynos7-ufs.c
+++ b/drivers/phy/samsung/phy-exynos7-ufs.c
@@ -11,6 +11,8 @@
 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK	0x1
 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN	BIT(0)
 
+#define PHY_CDR_LOCK_STATUS    0x5e
+
 /* Calibration for phy initialization */
 static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
 	PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
@@ -74,4 +76,5 @@ const struct samsung_ufs_phy_drvdata exynos7_ufs_phy = {
 		.en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN,
 	},
 	.has_symbol_clk = 1,
+	.cdr_lock_status_offset = PHY_CDR_LOCK_STATUS,
 };
diff --git a/drivers/phy/samsung/phy-exynosautov9-ufs.c b/drivers/phy/samsung/phy-exynosautov9-ufs.c
index 36398a15c2db..1572b985c70d 100644
--- a/drivers/phy/samsung/phy-exynosautov9-ufs.c
+++ b/drivers/phy/samsung/phy-exynosautov9-ufs.c
@@ -10,6 +10,7 @@
 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL		0x728
 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK	0x1
 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN		BIT(0)
+#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS	0x5e
 
 #define PHY_TRSV_REG_CFG_AUTOV9(o, v, d) \
 	PHY_TRSV_REG_CFG_OFFSET(o, v, d, 0x50)
@@ -64,4 +65,5 @@ const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy = {
 		.en = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN,
 	},
 	.has_symbol_clk = 0,
+	.cdr_lock_status_offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
 };
diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
index 602ddef259eb..8e5ae228daa7 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.c
+++ b/drivers/phy/samsung/phy-samsung-ufs.c
@@ -63,7 +63,8 @@ static int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy)
 	}
 
 	err = readl_poll_timeout(
-			ufs_phy->reg_pma + PHY_APB_ADDR(PHY_CDR_LOCK_STATUS),
+			ufs_phy->reg_pma +
+			PHY_APB_ADDR(ufs_phy->drvdata->cdr_lock_status_offset),
 			val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us);
 	if (err)
 		dev_err(ufs_phy->dev,
diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
index 91a0e9f94f98..965c79bbc278 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.h
+++ b/drivers/phy/samsung/phy-samsung-ufs.h
@@ -40,7 +40,6 @@
 
 /* UFS PHY registers */
 #define PHY_PLL_LOCK_STATUS	0x1e
-#define PHY_CDR_LOCK_STATUS	0x5e
 
 #define PHY_PLL_LOCK_BIT	BIT(5)
 #define PHY_CDR_LOCK_BIT	BIT(4)
@@ -109,6 +108,7 @@ struct samsung_ufs_phy_drvdata {
 		u32 en;
 	} isol;
 	bool has_symbol_clk;
+	u32 cdr_lock_status_offset;
 };
 
 struct samsung_ufs_phy {
-- 
2.25.1

[PATCH 2/6] phy: samsung-ufs: move cdr offset to drvdata

[Alim Akhtar]

Move CDR lock offset to drv data so that it can
be extended for other SoCs which are having CDR
lock at different register offset.

Cc: linux-fsd@tesla.com
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/phy/samsung/phy-exynos7-ufs.c      | 3 +++
 drivers/phy/samsung/phy-exynosautov9-ufs.c | 2 ++
 drivers/phy/samsung/phy-samsung-ufs.c      | 3 ++-
 drivers/phy/samsung/phy-samsung-ufs.h      | 2 +-
 4 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c b/drivers/phy/samsung/phy-exynos7-ufs.c
index 7c9008e163db..d1a37273cb1f 100644
--- a/drivers/phy/samsung/phy-exynos7-ufs.c
+++ b/drivers/phy/samsung/phy-exynos7-ufs.c
@@ -11,6 +11,8 @@
 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK	0x1
 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN	BIT(0)
 
+#define PHY_CDR_LOCK_STATUS    0x5e
+
 /* Calibration for phy initialization */
 static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
 	PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
@@ -74,4 +76,5 @@ const struct samsung_ufs_phy_drvdata exynos7_ufs_phy = {
 		.en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN,
 	},
 	.has_symbol_clk = 1,
+	.cdr_lock_status_offset = PHY_CDR_LOCK_STATUS,
 };
diff --git a/drivers/phy/samsung/phy-exynosautov9-ufs.c b/drivers/phy/samsung/phy-exynosautov9-ufs.c
index 36398a15c2db..1572b985c70d 100644
--- a/drivers/phy/samsung/phy-exynosautov9-ufs.c
+++ b/drivers/phy/samsung/phy-exynosautov9-ufs.c
@@ -10,6 +10,7 @@
 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL		0x728
 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK	0x1
 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN		BIT(0)
+#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS	0x5e
 
 #define PHY_TRSV_REG_CFG_AUTOV9(o, v, d) \
 	PHY_TRSV_REG_CFG_OFFSET(o, v, d, 0x50)
@@ -64,4 +65,5 @@ const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy = {
 		.en = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN,
 	},
 	.has_symbol_clk = 0,
+	.cdr_lock_status_offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
 };
diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
index 602ddef259eb..8e5ae228daa7 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.c
+++ b/drivers/phy/samsung/phy-samsung-ufs.c
@@ -63,7 +63,8 @@ static int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy)
 	}
 
 	err = readl_poll_timeout(
-			ufs_phy->reg_pma + PHY_APB_ADDR(PHY_CDR_LOCK_STATUS),
+			ufs_phy->reg_pma +
+			PHY_APB_ADDR(ufs_phy->drvdata->cdr_lock_status_offset),
 			val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us);
 	if (err)
 		dev_err(ufs_phy->dev,
diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
index 91a0e9f94f98..965c79bbc278 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.h
+++ b/drivers/phy/samsung/phy-samsung-ufs.h
@@ -40,7 +40,6 @@
 
 /* UFS PHY registers */
 #define PHY_PLL_LOCK_STATUS	0x1e
-#define PHY_CDR_LOCK_STATUS	0x5e
 
 #define PHY_PLL_LOCK_BIT	BIT(5)
 #define PHY_CDR_LOCK_BIT	BIT(4)
@@ -109,6 +108,7 @@ struct samsung_ufs_phy_drvdata {
 		u32 en;
 	} isol;
 	bool has_symbol_clk;
+	u32 cdr_lock_status_offset;
 };
 
 struct samsung_ufs_phy {
-- 
2.25.1


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[PATCH 2/6] phy: samsung-ufs: move cdr offset to drvdata

[Alim Akhtar]

Move CDR lock offset to drv data so that it can
be extended for other SoCs which are having CDR
lock at different register offset.

Cc: linux-fsd@tesla.com
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/phy/samsung/phy-exynos7-ufs.c      | 3 +++
 drivers/phy/samsung/phy-exynosautov9-ufs.c | 2 ++
 drivers/phy/samsung/phy-samsung-ufs.c      | 3 ++-
 drivers/phy/samsung/phy-samsung-ufs.h      | 2 +-
 4 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c b/drivers/phy/samsung/phy-exynos7-ufs.c
index 7c9008e163db..d1a37273cb1f 100644
--- a/drivers/phy/samsung/phy-exynos7-ufs.c
+++ b/drivers/phy/samsung/phy-exynos7-ufs.c
@@ -11,6 +11,8 @@
 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK	0x1
 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN	BIT(0)
 
+#define PHY_CDR_LOCK_STATUS    0x5e
+
 /* Calibration for phy initialization */
 static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
 	PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
@@ -74,4 +76,5 @@ const struct samsung_ufs_phy_drvdata exynos7_ufs_phy = {
 		.en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN,
 	},
 	.has_symbol_clk = 1,
+	.cdr_lock_status_offset = PHY_CDR_LOCK_STATUS,
 };
diff --git a/drivers/phy/samsung/phy-exynosautov9-ufs.c b/drivers/phy/samsung/phy-exynosautov9-ufs.c
index 36398a15c2db..1572b985c70d 100644
--- a/drivers/phy/samsung/phy-exynosautov9-ufs.c
+++ b/drivers/phy/samsung/phy-exynosautov9-ufs.c
@@ -10,6 +10,7 @@
 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL		0x728
 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK	0x1
 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN		BIT(0)
+#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS	0x5e
 
 #define PHY_TRSV_REG_CFG_AUTOV9(o, v, d) \
 	PHY_TRSV_REG_CFG_OFFSET(o, v, d, 0x50)
@@ -64,4 +65,5 @@ const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy = {
 		.en = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN,
 	},
 	.has_symbol_clk = 0,
+	.cdr_lock_status_offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
 };
diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
index 602ddef259eb..8e5ae228daa7 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.c
+++ b/drivers/phy/samsung/phy-samsung-ufs.c
@@ -63,7 +63,8 @@ static int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy)
 	}
 
 	err = readl_poll_timeout(
-			ufs_phy->reg_pma + PHY_APB_ADDR(PHY_CDR_LOCK_STATUS),
+			ufs_phy->reg_pma +
+			PHY_APB_ADDR(ufs_phy->drvdata->cdr_lock_status_offset),
 			val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us);
 	if (err)
 		dev_err(ufs_phy->dev,
diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
index 91a0e9f94f98..965c79bbc278 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.h
+++ b/drivers/phy/samsung/phy-samsung-ufs.h
@@ -40,7 +40,6 @@
 
 /* UFS PHY registers */
 #define PHY_PLL_LOCK_STATUS	0x1e
-#define PHY_CDR_LOCK_STATUS	0x5e
 
 #define PHY_PLL_LOCK_BIT	BIT(5)
 #define PHY_CDR_LOCK_BIT	BIT(4)
@@ -109,6 +108,7 @@ struct samsung_ufs_phy_drvdata {
 		u32 en;
 	} isol;
 	bool has_symbol_clk;
+	u32 cdr_lock_status_offset;
 };
 
 struct samsung_ufs_phy {
-- 
2.25.1


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[PATCH 3/6] phy: samsung-ufs: add support for FSD ufs phy driver

[Alim Akhtar]

Adds support for Tesla FSD ufs phy driver. This SoC has
different cdr lock status offset.

Cc: linux-fsd@tesla.com
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/phy/samsung/Makefile          |  1 +
 drivers/phy/samsung/phy-fsd-ufs.c     | 63 +++++++++++++++++++++++++++
 drivers/phy/samsung/phy-samsung-ufs.c |  3 ++
 drivers/phy/samsung/phy-samsung-ufs.h |  1 +
 4 files changed, 68 insertions(+)
 create mode 100644 drivers/phy/samsung/phy-fsd-ufs.c

diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
index 65e4cc59403f..afb34a153e34 100644
--- a/drivers/phy/samsung/Makefile
+++ b/drivers/phy/samsung/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_SAMSUNG_UFS)		+= phy-exynos-ufs.o
 phy-exynos-ufs-y			+= phy-samsung-ufs.o
 phy-exynos-ufs-y			+= phy-exynos7-ufs.o
 phy-exynos-ufs-y			+= phy-exynosautov9-ufs.o
+phy-exynos-ufs-y			+= phy-fsd-ufs.o
 obj-$(CONFIG_PHY_SAMSUNG_USB2)		+= phy-exynos-usb2.o
 phy-exynos-usb2-y			+= phy-samsung-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2)	+= phy-exynos4210-usb2.o
diff --git a/drivers/phy/samsung/phy-fsd-ufs.c b/drivers/phy/samsung/phy-fsd-ufs.c
new file mode 100644
index 000000000000..a03656006093
--- /dev/null
+++ b/drivers/phy/samsung/phy-fsd-ufs.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * UFS PHY driver data for FSD SoC
+ *
+ * Copyright (C) 2022 Samsung Electronics Co., Ltd.
+ *
+ */
+#ifndef _PHY_FSD_UFS_H_
+#define _PHY_FSD_UFS_H_
+
+#include "phy-samsung-ufs.h"
+
+#define FSD_EMBEDDED_COMBO_PHY_CTRL	0x724
+#define FSD_EMBEDDED_COMBO_PHY_CTRL_MASK	0x1
+#define FSD_EMBEDDED_COMBO_PHY_CTRL_EN	BIT(0)
+#define FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS	0x6e
+
+static const struct samsung_ufs_phy_cfg fsd_pre_init_cfg[] = {
+	PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
+	PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
+	PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
+	PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
+	END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B */
+static const struct samsung_ufs_phy_cfg fsd_pre_pwr_hs_cfg[] = {
+	END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B atfer PMC */
+static const struct samsung_ufs_phy_cfg fsd_post_pwr_hs_cfg[] = {
+	END_UFS_PHY_CFG
+};
+
+static const struct samsung_ufs_phy_cfg *fsd_ufs_phy_cfgs[CFG_TAG_MAX] = {
+	[CFG_PRE_INIT]		= fsd_pre_init_cfg,
+	[CFG_PRE_PWR_HS]	= fsd_pre_pwr_hs_cfg,
+	[CFG_POST_PWR_HS]	= fsd_post_pwr_hs_cfg,
+};
+
+const struct samsung_ufs_phy_drvdata fsd_ufs_phy = {
+	.cfg = fsd_ufs_phy_cfgs,
+	.isol = {
+		.offset = FSD_EMBEDDED_COMBO_PHY_CTRL,
+		.mask = FSD_EMBEDDED_COMBO_PHY_CTRL_MASK,
+		.en = FSD_EMBEDDED_COMBO_PHY_CTRL_EN,
+	},
+	.has_symbol_clk = 0,
+	.cdr_lock_status_offset = FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
+};
+
+#endif /* _PHY_FSD_UFS_H_ */
diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
index 8e5ae228daa7..935c5c7a6d1e 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.c
+++ b/drivers/phy/samsung/phy-samsung-ufs.c
@@ -351,6 +351,9 @@ static const struct of_device_id samsung_ufs_phy_match[] = {
 	}, {
 		.compatible = "samsung,exynosautov9-ufs-phy",
 		.data = &exynosautov9_ufs_phy,
+	}, {
+		.compatible = "tesla,fsd-ufs-phy",
+		.data = &fsd_ufs_phy,
 	},
 	{},
 };
diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
index 965c79bbc278..74b40ef8e1d8 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.h
+++ b/drivers/phy/samsung/phy-samsung-ufs.h
@@ -142,5 +142,6 @@ static inline void samsung_ufs_phy_ctrl_isol(
 
 extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy;
 extern const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy;
+extern const struct samsung_ufs_phy_drvdata fsd_ufs_phy;
 
 #endif /* _PHY_SAMSUNG_UFS_ */
-- 
2.25.1

[PATCH 3/6] phy: samsung-ufs: add support for FSD ufs phy driver

[Alim Akhtar]

Adds support for Tesla FSD ufs phy driver. This SoC has
different cdr lock status offset.

Cc: linux-fsd@tesla.com
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/phy/samsung/Makefile          |  1 +
 drivers/phy/samsung/phy-fsd-ufs.c     | 63 +++++++++++++++++++++++++++
 drivers/phy/samsung/phy-samsung-ufs.c |  3 ++
 drivers/phy/samsung/phy-samsung-ufs.h |  1 +
 4 files changed, 68 insertions(+)
 create mode 100644 drivers/phy/samsung/phy-fsd-ufs.c

diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
index 65e4cc59403f..afb34a153e34 100644
--- a/drivers/phy/samsung/Makefile
+++ b/drivers/phy/samsung/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_SAMSUNG_UFS)		+= phy-exynos-ufs.o
 phy-exynos-ufs-y			+= phy-samsung-ufs.o
 phy-exynos-ufs-y			+= phy-exynos7-ufs.o
 phy-exynos-ufs-y			+= phy-exynosautov9-ufs.o
+phy-exynos-ufs-y			+= phy-fsd-ufs.o
 obj-$(CONFIG_PHY_SAMSUNG_USB2)		+= phy-exynos-usb2.o
 phy-exynos-usb2-y			+= phy-samsung-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2)	+= phy-exynos4210-usb2.o
diff --git a/drivers/phy/samsung/phy-fsd-ufs.c b/drivers/phy/samsung/phy-fsd-ufs.c
new file mode 100644
index 000000000000..a03656006093
--- /dev/null
+++ b/drivers/phy/samsung/phy-fsd-ufs.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * UFS PHY driver data for FSD SoC
+ *
+ * Copyright (C) 2022 Samsung Electronics Co., Ltd.
+ *
+ */
+#ifndef _PHY_FSD_UFS_H_
+#define _PHY_FSD_UFS_H_
+
+#include "phy-samsung-ufs.h"
+
+#define FSD_EMBEDDED_COMBO_PHY_CTRL	0x724
+#define FSD_EMBEDDED_COMBO_PHY_CTRL_MASK	0x1
+#define FSD_EMBEDDED_COMBO_PHY_CTRL_EN	BIT(0)
+#define FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS	0x6e
+
+static const struct samsung_ufs_phy_cfg fsd_pre_init_cfg[] = {
+	PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
+	PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
+	PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
+	PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
+	END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B */
+static const struct samsung_ufs_phy_cfg fsd_pre_pwr_hs_cfg[] = {
+	END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B atfer PMC */
+static const struct samsung_ufs_phy_cfg fsd_post_pwr_hs_cfg[] = {
+	END_UFS_PHY_CFG
+};
+
+static const struct samsung_ufs_phy_cfg *fsd_ufs_phy_cfgs[CFG_TAG_MAX] = {
+	[CFG_PRE_INIT]		= fsd_pre_init_cfg,
+	[CFG_PRE_PWR_HS]	= fsd_pre_pwr_hs_cfg,
+	[CFG_POST_PWR_HS]	= fsd_post_pwr_hs_cfg,
+};
+
+const struct samsung_ufs_phy_drvdata fsd_ufs_phy = {
+	.cfg = fsd_ufs_phy_cfgs,
+	.isol = {
+		.offset = FSD_EMBEDDED_COMBO_PHY_CTRL,
+		.mask = FSD_EMBEDDED_COMBO_PHY_CTRL_MASK,
+		.en = FSD_EMBEDDED_COMBO_PHY_CTRL_EN,
+	},
+	.has_symbol_clk = 0,
+	.cdr_lock_status_offset = FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
+};
+
+#endif /* _PHY_FSD_UFS_H_ */
diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
index 8e5ae228daa7..935c5c7a6d1e 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.c
+++ b/drivers/phy/samsung/phy-samsung-ufs.c
@@ -351,6 +351,9 @@ static const struct of_device_id samsung_ufs_phy_match[] = {
 	}, {
 		.compatible = "samsung,exynosautov9-ufs-phy",
 		.data = &exynosautov9_ufs_phy,
+	}, {
+		.compatible = "tesla,fsd-ufs-phy",
+		.data = &fsd_ufs_phy,
 	},
 	{},
 };
diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
index 965c79bbc278..74b40ef8e1d8 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.h
+++ b/drivers/phy/samsung/phy-samsung-ufs.h
@@ -142,5 +142,6 @@ static inline void samsung_ufs_phy_ctrl_isol(
 
 extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy;
 extern const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy;
+extern const struct samsung_ufs_phy_drvdata fsd_ufs_phy;
 
 #endif /* _PHY_SAMSUNG_UFS_ */
-- 
2.25.1


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[PATCH 3/6] phy: samsung-ufs: add support for FSD ufs phy driver

[Alim Akhtar]

Adds support for Tesla FSD ufs phy driver. This SoC has
different cdr lock status offset.

Cc: linux-fsd@tesla.com
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/phy/samsung/Makefile          |  1 +
 drivers/phy/samsung/phy-fsd-ufs.c     | 63 +++++++++++++++++++++++++++
 drivers/phy/samsung/phy-samsung-ufs.c |  3 ++
 drivers/phy/samsung/phy-samsung-ufs.h |  1 +
 4 files changed, 68 insertions(+)
 create mode 100644 drivers/phy/samsung/phy-fsd-ufs.c

diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
index 65e4cc59403f..afb34a153e34 100644
--- a/drivers/phy/samsung/Makefile
+++ b/drivers/phy/samsung/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_SAMSUNG_UFS)		+= phy-exynos-ufs.o
 phy-exynos-ufs-y			+= phy-samsung-ufs.o
 phy-exynos-ufs-y			+= phy-exynos7-ufs.o
 phy-exynos-ufs-y			+= phy-exynosautov9-ufs.o
+phy-exynos-ufs-y			+= phy-fsd-ufs.o
 obj-$(CONFIG_PHY_SAMSUNG_USB2)		+= phy-exynos-usb2.o
 phy-exynos-usb2-y			+= phy-samsung-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2)	+= phy-exynos4210-usb2.o
diff --git a/drivers/phy/samsung/phy-fsd-ufs.c b/drivers/phy/samsung/phy-fsd-ufs.c
new file mode 100644
index 000000000000..a03656006093
--- /dev/null
+++ b/drivers/phy/samsung/phy-fsd-ufs.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * UFS PHY driver data for FSD SoC
+ *
+ * Copyright (C) 2022 Samsung Electronics Co., Ltd.
+ *
+ */
+#ifndef _PHY_FSD_UFS_H_
+#define _PHY_FSD_UFS_H_
+
+#include "phy-samsung-ufs.h"
+
+#define FSD_EMBEDDED_COMBO_PHY_CTRL	0x724
+#define FSD_EMBEDDED_COMBO_PHY_CTRL_MASK	0x1
+#define FSD_EMBEDDED_COMBO_PHY_CTRL_EN	BIT(0)
+#define FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS	0x6e
+
+static const struct samsung_ufs_phy_cfg fsd_pre_init_cfg[] = {
+	PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
+	PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
+	PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
+	PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
+	END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B */
+static const struct samsung_ufs_phy_cfg fsd_pre_pwr_hs_cfg[] = {
+	END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B atfer PMC */
+static const struct samsung_ufs_phy_cfg fsd_post_pwr_hs_cfg[] = {
+	END_UFS_PHY_CFG
+};
+
+static const struct samsung_ufs_phy_cfg *fsd_ufs_phy_cfgs[CFG_TAG_MAX] = {
+	[CFG_PRE_INIT]		= fsd_pre_init_cfg,
+	[CFG_PRE_PWR_HS]	= fsd_pre_pwr_hs_cfg,
+	[CFG_POST_PWR_HS]	= fsd_post_pwr_hs_cfg,
+};
+
+const struct samsung_ufs_phy_drvdata fsd_ufs_phy = {
+	.cfg = fsd_ufs_phy_cfgs,
+	.isol = {
+		.offset = FSD_EMBEDDED_COMBO_PHY_CTRL,
+		.mask = FSD_EMBEDDED_COMBO_PHY_CTRL_MASK,
+		.en = FSD_EMBEDDED_COMBO_PHY_CTRL_EN,
+	},
+	.has_symbol_clk = 0,
+	.cdr_lock_status_offset = FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
+};
+
+#endif /* _PHY_FSD_UFS_H_ */
diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
index 8e5ae228daa7..935c5c7a6d1e 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.c
+++ b/drivers/phy/samsung/phy-samsung-ufs.c
@@ -351,6 +351,9 @@ static const struct of_device_id samsung_ufs_phy_match[] = {
 	}, {
 		.compatible = "samsung,exynosautov9-ufs-phy",
 		.data = &exynosautov9_ufs_phy,
+	}, {
+		.compatible = "tesla,fsd-ufs-phy",
+		.data = &fsd_ufs_phy,
 	},
 	{},
 };
diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
index 965c79bbc278..74b40ef8e1d8 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.h
+++ b/drivers/phy/samsung/phy-samsung-ufs.h
@@ -142,5 +142,6 @@ static inline void samsung_ufs_phy_ctrl_isol(
 
 extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy;
 extern const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy;
+extern const struct samsung_ufs_phy_drvdata fsd_ufs_phy;
 
 #endif /* _PHY_SAMSUNG_UFS_ */
-- 
2.25.1


_______________________________________________
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[PATCH 4/6] dt-bindings: ufs: exynos-ufs: add fsd compatible

[Alim Akhtar]

Adds tesla,fsd-ufs compatible for Tesla FSD SoC.

Cc: linux-fsd@tesla.com
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
index c949eb617313..2c715eec48b8 100644
--- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
@@ -21,6 +21,7 @@ properties:
       - samsung,exynos7-ufs
       - samsung,exynosautov9-ufs
       - samsung,exynosautov9-ufs-vh
+      - tesla,fsd-ufs
 
   reg:
     items:
-- 
2.25.1

[PATCH 4/6] dt-bindings: ufs: exynos-ufs: add fsd compatible

[Alim Akhtar]

Adds tesla,fsd-ufs compatible for Tesla FSD SoC.

Cc: linux-fsd@tesla.com
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
index c949eb617313..2c715eec48b8 100644
--- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
@@ -21,6 +21,7 @@ properties:
       - samsung,exynos7-ufs
       - samsung,exynosautov9-ufs
       - samsung,exynosautov9-ufs-vh
+      - tesla,fsd-ufs
 
   reg:
     items:
-- 
2.25.1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

[PATCH 4/6] dt-bindings: ufs: exynos-ufs: add fsd compatible

[Alim Akhtar]

Adds tesla,fsd-ufs compatible for Tesla FSD SoC.

Cc: linux-fsd@tesla.com
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
index c949eb617313..2c715eec48b8 100644
--- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
@@ -21,6 +21,7 @@ properties:
       - samsung,exynos7-ufs
       - samsung,exynosautov9-ufs
       - samsung,exynosautov9-ufs-vh
+      - tesla,fsd-ufs
 
   reg:
     items:
-- 
2.25.1


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 5/6] ufs: host: ufs-exynos: add support for fsd ufs hci

[Alim Akhtar]

Adds support of UFS HCI which is found in Tesla
FSD SoC. FSD also have an addition bit for MPHY
APB clock which was not there (was reserved) for
previous exynos SoC.

Cc: linux-fsd@tesla.com
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/ufs/host/ufs-exynos.c | 143 +++++++++++++++++++++++++++++++++-
 1 file changed, 142 insertions(+), 1 deletion(-)

diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index a81d8cbd542f..b3efdc4caca2 100644
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -52,11 +52,12 @@
 #define HCI_ERR_EN_DME_LAYER	0x88
 #define HCI_CLKSTOP_CTRL	0xB0
 #define REFCLKOUT_STOP		BIT(4)
+#define MPHY_APBCLK_STOP        BIT(3)
 #define REFCLK_STOP		BIT(2)
 #define UNIPRO_MCLK_STOP	BIT(1)
 #define UNIPRO_PCLK_STOP	BIT(0)
 #define CLK_STOP_MASK		(REFCLKOUT_STOP | REFCLK_STOP |\
-				 UNIPRO_MCLK_STOP |\
+				 UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\
 				 UNIPRO_PCLK_STOP)
 #define HCI_MISC		0xB4
 #define REFCLK_CTRL_EN		BIT(7)
@@ -386,6 +387,104 @@ static int exynos7_ufs_post_pwr_change(struct exynos_ufs *ufs,
 	return 0;
 }
 
+static inline int fsd_ufs_pre_link(struct exynos_ufs *ufs)
+{
+	int i;
+	struct ufs_hba *hba = ufs->hba;
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9514), 1000000000L / ufs->mclk_rate);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
+
+	for_each_ufs_tx_lane(ufs, i) {
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i), 1000000000L / ufs->mclk_rate);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F);
+	}
+
+	for_each_ufs_rx_lane(ufs, i) {
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i), 1000000000L / ufs->mclk_rate);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0);
+	}
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9536), 0x4E20);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9564), 0x2e820183);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x155E), 0x0);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x3000), 0x0);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x3001), 0x1);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x4021), 0x1);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x4020), 0x1);
+
+	return 0;
+}
+
+static inline int fsd_ufs_post_link(struct exynos_ufs *ufs)
+{
+	int i;
+	struct ufs_hba *hba = ufs->hba;
+	u32 hw_cap_min_tactivate;
+	u32 peer_rx_min_actv_time_cap;
+	u32 max_rx_hibern8_time_cap;
+
+	ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4),
+			&hw_cap_min_tactivate); /* HW Capability of MIN_TACTIVATE */
+	ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A8),
+			&peer_rx_min_actv_time_cap);    /* PA_TActivate */
+	ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A7),
+			&max_rx_hibern8_time_cap);      /* PA_Hibern8Time */
+
+	if (peer_rx_min_actv_time_cap >= hw_cap_min_tactivate)
+		ufshcd_dme_peer_set(hba, UIC_ARG_MIB(0x15A8),
+					peer_rx_min_actv_time_cap + 1);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A7), max_rx_hibern8_time_cap + 1);
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x01);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A4), 0xFA);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x00);
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
+
+	for_each_ufs_rx_lane(ufs, i) {
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC);
+	}
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
+
+	return 0;
+}
+
+static inline int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs,
+					struct ufs_pa_layer_attr *pwr)
+{
+	struct ufs_hba *hba = ufs->hba;
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x1569), 0x1);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x1584), 0x1);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2041), 8064);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2042), 28224);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2043), 20160);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B0), 12000);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B1), 32000);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B2), 16000);
+
+	unipro_writel(ufs, 8064, 0x7888);
+	unipro_writel(ufs, 28224, 0x788C);
+	unipro_writel(ufs, 20160, 0x7890);
+	unipro_writel(ufs, 12000, 0x78B8);
+	unipro_writel(ufs, 32000, 0x78BC);
+	unipro_writel(ufs, 16000, 0x78C0);
+
+	return 0;
+}
+
 /*
  * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w
  * Control should be disabled in the below cases
@@ -1595,6 +1694,46 @@ static struct exynos_ufs_drv_data exynos_ufs_drvs = {
 	.post_pwr_change	= exynos7_ufs_post_pwr_change,
 };
 
+static struct exynos_ufs_uic_attr fsd_uic_attr = {
+	.tx_trailingclks		= 0x10,
+	.tx_dif_p_nsec			= 3000000,	/* unit: ns */
+	.tx_dif_n_nsec			= 1000000,	/* unit: ns */
+	.tx_high_z_cnt_nsec		= 20000,	/* unit: ns */
+	.tx_base_unit_nsec		= 100000,	/* unit: ns */
+	.tx_gran_unit_nsec		= 4000,		/* unit: ns */
+	.tx_sleep_cnt			= 1000,		/* unit: ns */
+	.tx_min_activatetime		= 0xa,
+	.rx_filler_enable		= 0x2,
+	.rx_dif_p_nsec			= 1000000,	/* unit: ns */
+	.rx_hibern8_wait_nsec		= 4000000,	/* unit: ns */
+	.rx_base_unit_nsec		= 100000,	/* unit: ns */
+	.rx_gran_unit_nsec		= 4000,		/* unit: ns */
+	.rx_sleep_cnt			= 1280,		/* unit: ns */
+	.rx_stall_cnt			= 320,		/* unit: ns */
+	.rx_hs_g1_sync_len_cap		= SYNC_LEN_COARSE(0xf),
+	.rx_hs_g2_sync_len_cap		= SYNC_LEN_COARSE(0xf),
+	.rx_hs_g3_sync_len_cap		= SYNC_LEN_COARSE(0xf),
+	.rx_hs_g1_prep_sync_len_cap	= PREP_LEN(0xf),
+	.rx_hs_g2_prep_sync_len_cap	= PREP_LEN(0xf),
+	.rx_hs_g3_prep_sync_len_cap	= PREP_LEN(0xf),
+	.pa_dbg_option_suite		= 0x2E820183,
+};
+
+struct exynos_ufs_drv_data fsd_ufs_drvs = {
+	.uic_attr               = &fsd_uic_attr,
+	.quirks                 = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
+				  UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
+				  UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
+				  UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR,
+	.opts                   = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
+				  EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
+				  EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
+				  EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
+	.pre_link               = fsd_ufs_pre_link,
+	.post_link              = fsd_ufs_post_link,
+	.pre_pwr_change         = fsd_ufs_pre_pwr_change,
+};
+
 static const struct of_device_id exynos_ufs_of_match[] = {
 	{ .compatible = "samsung,exynos7-ufs",
 	  .data	      = &exynos_ufs_drvs },
@@ -1602,6 +1741,8 @@ static const struct of_device_id exynos_ufs_of_match[] = {
 	  .data	      = &exynosauto_ufs_drvs },
 	{ .compatible = "samsung,exynosautov9-ufs-vh",
 	  .data	      = &exynosauto_ufs_vh_drvs },
+	{ .compatible = "tesla,fsd-ufs",
+	  .data       = &fsd_ufs_drvs },
 	{},
 };
 
-- 
2.25.1

[PATCH 5/6] ufs: host: ufs-exynos: add support for fsd ufs hci

[Alim Akhtar]

Adds support of UFS HCI which is found in Tesla
FSD SoC. FSD also have an addition bit for MPHY
APB clock which was not there (was reserved) for
previous exynos SoC.

Cc: linux-fsd@tesla.com
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/ufs/host/ufs-exynos.c | 143 +++++++++++++++++++++++++++++++++-
 1 file changed, 142 insertions(+), 1 deletion(-)

diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index a81d8cbd542f..b3efdc4caca2 100644
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -52,11 +52,12 @@
 #define HCI_ERR_EN_DME_LAYER	0x88
 #define HCI_CLKSTOP_CTRL	0xB0
 #define REFCLKOUT_STOP		BIT(4)
+#define MPHY_APBCLK_STOP        BIT(3)
 #define REFCLK_STOP		BIT(2)
 #define UNIPRO_MCLK_STOP	BIT(1)
 #define UNIPRO_PCLK_STOP	BIT(0)
 #define CLK_STOP_MASK		(REFCLKOUT_STOP | REFCLK_STOP |\
-				 UNIPRO_MCLK_STOP |\
+				 UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\
 				 UNIPRO_PCLK_STOP)
 #define HCI_MISC		0xB4
 #define REFCLK_CTRL_EN		BIT(7)
@@ -386,6 +387,104 @@ static int exynos7_ufs_post_pwr_change(struct exynos_ufs *ufs,
 	return 0;
 }
 
+static inline int fsd_ufs_pre_link(struct exynos_ufs *ufs)
+{
+	int i;
+	struct ufs_hba *hba = ufs->hba;
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9514), 1000000000L / ufs->mclk_rate);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
+
+	for_each_ufs_tx_lane(ufs, i) {
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i), 1000000000L / ufs->mclk_rate);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F);
+	}
+
+	for_each_ufs_rx_lane(ufs, i) {
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i), 1000000000L / ufs->mclk_rate);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0);
+	}
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9536), 0x4E20);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9564), 0x2e820183);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x155E), 0x0);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x3000), 0x0);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x3001), 0x1);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x4021), 0x1);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x4020), 0x1);
+
+	return 0;
+}
+
+static inline int fsd_ufs_post_link(struct exynos_ufs *ufs)
+{
+	int i;
+	struct ufs_hba *hba = ufs->hba;
+	u32 hw_cap_min_tactivate;
+	u32 peer_rx_min_actv_time_cap;
+	u32 max_rx_hibern8_time_cap;
+
+	ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4),
+			&hw_cap_min_tactivate); /* HW Capability of MIN_TACTIVATE */
+	ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A8),
+			&peer_rx_min_actv_time_cap);    /* PA_TActivate */
+	ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A7),
+			&max_rx_hibern8_time_cap);      /* PA_Hibern8Time */
+
+	if (peer_rx_min_actv_time_cap >= hw_cap_min_tactivate)
+		ufshcd_dme_peer_set(hba, UIC_ARG_MIB(0x15A8),
+					peer_rx_min_actv_time_cap + 1);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A7), max_rx_hibern8_time_cap + 1);
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x01);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A4), 0xFA);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x00);
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
+
+	for_each_ufs_rx_lane(ufs, i) {
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC);
+	}
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
+
+	return 0;
+}
+
+static inline int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs,
+					struct ufs_pa_layer_attr *pwr)
+{
+	struct ufs_hba *hba = ufs->hba;
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x1569), 0x1);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x1584), 0x1);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2041), 8064);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2042), 28224);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2043), 20160);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B0), 12000);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B1), 32000);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B2), 16000);
+
+	unipro_writel(ufs, 8064, 0x7888);
+	unipro_writel(ufs, 28224, 0x788C);
+	unipro_writel(ufs, 20160, 0x7890);
+	unipro_writel(ufs, 12000, 0x78B8);
+	unipro_writel(ufs, 32000, 0x78BC);
+	unipro_writel(ufs, 16000, 0x78C0);
+
+	return 0;
+}
+
 /*
  * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w
  * Control should be disabled in the below cases
@@ -1595,6 +1694,46 @@ static struct exynos_ufs_drv_data exynos_ufs_drvs = {
 	.post_pwr_change	= exynos7_ufs_post_pwr_change,
 };
 
+static struct exynos_ufs_uic_attr fsd_uic_attr = {
+	.tx_trailingclks		= 0x10,
+	.tx_dif_p_nsec			= 3000000,	/* unit: ns */
+	.tx_dif_n_nsec			= 1000000,	/* unit: ns */
+	.tx_high_z_cnt_nsec		= 20000,	/* unit: ns */
+	.tx_base_unit_nsec		= 100000,	/* unit: ns */
+	.tx_gran_unit_nsec		= 4000,		/* unit: ns */
+	.tx_sleep_cnt			= 1000,		/* unit: ns */
+	.tx_min_activatetime		= 0xa,
+	.rx_filler_enable		= 0x2,
+	.rx_dif_p_nsec			= 1000000,	/* unit: ns */
+	.rx_hibern8_wait_nsec		= 4000000,	/* unit: ns */
+	.rx_base_unit_nsec		= 100000,	/* unit: ns */
+	.rx_gran_unit_nsec		= 4000,		/* unit: ns */
+	.rx_sleep_cnt			= 1280,		/* unit: ns */
+	.rx_stall_cnt			= 320,		/* unit: ns */
+	.rx_hs_g1_sync_len_cap		= SYNC_LEN_COARSE(0xf),
+	.rx_hs_g2_sync_len_cap		= SYNC_LEN_COARSE(0xf),
+	.rx_hs_g3_sync_len_cap		= SYNC_LEN_COARSE(0xf),
+	.rx_hs_g1_prep_sync_len_cap	= PREP_LEN(0xf),
+	.rx_hs_g2_prep_sync_len_cap	= PREP_LEN(0xf),
+	.rx_hs_g3_prep_sync_len_cap	= PREP_LEN(0xf),
+	.pa_dbg_option_suite		= 0x2E820183,
+};
+
+struct exynos_ufs_drv_data fsd_ufs_drvs = {
+	.uic_attr               = &fsd_uic_attr,
+	.quirks                 = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
+				  UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
+				  UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
+				  UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR,
+	.opts                   = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
+				  EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
+				  EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
+				  EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
+	.pre_link               = fsd_ufs_pre_link,
+	.post_link              = fsd_ufs_post_link,
+	.pre_pwr_change         = fsd_ufs_pre_pwr_change,
+};
+
 static const struct of_device_id exynos_ufs_of_match[] = {
 	{ .compatible = "samsung,exynos7-ufs",
 	  .data	      = &exynos_ufs_drvs },
@@ -1602,6 +1741,8 @@ static const struct of_device_id exynos_ufs_of_match[] = {
 	  .data	      = &exynosauto_ufs_drvs },
 	{ .compatible = "samsung,exynosautov9-ufs-vh",
 	  .data	      = &exynosauto_ufs_vh_drvs },
+	{ .compatible = "tesla,fsd-ufs",
+	  .data       = &fsd_ufs_drvs },
 	{},
 };
 
-- 
2.25.1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

[PATCH 5/6] ufs: host: ufs-exynos: add support for fsd ufs hci

[Alim Akhtar]

Adds support of UFS HCI which is found in Tesla
FSD SoC. FSD also have an addition bit for MPHY
APB clock which was not there (was reserved) for
previous exynos SoC.

Cc: linux-fsd@tesla.com
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/ufs/host/ufs-exynos.c | 143 +++++++++++++++++++++++++++++++++-
 1 file changed, 142 insertions(+), 1 deletion(-)

diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index a81d8cbd542f..b3efdc4caca2 100644
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -52,11 +52,12 @@
 #define HCI_ERR_EN_DME_LAYER	0x88
 #define HCI_CLKSTOP_CTRL	0xB0
 #define REFCLKOUT_STOP		BIT(4)
+#define MPHY_APBCLK_STOP        BIT(3)
 #define REFCLK_STOP		BIT(2)
 #define UNIPRO_MCLK_STOP	BIT(1)
 #define UNIPRO_PCLK_STOP	BIT(0)
 #define CLK_STOP_MASK		(REFCLKOUT_STOP | REFCLK_STOP |\
-				 UNIPRO_MCLK_STOP |\
+				 UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\
 				 UNIPRO_PCLK_STOP)
 #define HCI_MISC		0xB4
 #define REFCLK_CTRL_EN		BIT(7)
@@ -386,6 +387,104 @@ static int exynos7_ufs_post_pwr_change(struct exynos_ufs *ufs,
 	return 0;
 }
 
+static inline int fsd_ufs_pre_link(struct exynos_ufs *ufs)
+{
+	int i;
+	struct ufs_hba *hba = ufs->hba;
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9514), 1000000000L / ufs->mclk_rate);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
+
+	for_each_ufs_tx_lane(ufs, i) {
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i), 1000000000L / ufs->mclk_rate);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F);
+	}
+
+	for_each_ufs_rx_lane(ufs, i) {
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i), 1000000000L / ufs->mclk_rate);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0);
+	}
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9536), 0x4E20);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9564), 0x2e820183);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x155E), 0x0);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x3000), 0x0);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x3001), 0x1);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x4021), 0x1);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x4020), 0x1);
+
+	return 0;
+}
+
+static inline int fsd_ufs_post_link(struct exynos_ufs *ufs)
+{
+	int i;
+	struct ufs_hba *hba = ufs->hba;
+	u32 hw_cap_min_tactivate;
+	u32 peer_rx_min_actv_time_cap;
+	u32 max_rx_hibern8_time_cap;
+
+	ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4),
+			&hw_cap_min_tactivate); /* HW Capability of MIN_TACTIVATE */
+	ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A8),
+			&peer_rx_min_actv_time_cap);    /* PA_TActivate */
+	ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A7),
+			&max_rx_hibern8_time_cap);      /* PA_Hibern8Time */
+
+	if (peer_rx_min_actv_time_cap >= hw_cap_min_tactivate)
+		ufshcd_dme_peer_set(hba, UIC_ARG_MIB(0x15A8),
+					peer_rx_min_actv_time_cap + 1);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A7), max_rx_hibern8_time_cap + 1);
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x01);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A4), 0xFA);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x00);
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
+
+	for_each_ufs_rx_lane(ufs, i) {
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC);
+	}
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
+
+	return 0;
+}
+
+static inline int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs,
+					struct ufs_pa_layer_attr *pwr)
+{
+	struct ufs_hba *hba = ufs->hba;
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x1569), 0x1);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x1584), 0x1);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2041), 8064);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2042), 28224);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2043), 20160);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B0), 12000);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B1), 32000);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B2), 16000);
+
+	unipro_writel(ufs, 8064, 0x7888);
+	unipro_writel(ufs, 28224, 0x788C);
+	unipro_writel(ufs, 20160, 0x7890);
+	unipro_writel(ufs, 12000, 0x78B8);
+	unipro_writel(ufs, 32000, 0x78BC);
+	unipro_writel(ufs, 16000, 0x78C0);
+
+	return 0;
+}
+
 /*
  * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w
  * Control should be disabled in the below cases
@@ -1595,6 +1694,46 @@ static struct exynos_ufs_drv_data exynos_ufs_drvs = {
 	.post_pwr_change	= exynos7_ufs_post_pwr_change,
 };
 
+static struct exynos_ufs_uic_attr fsd_uic_attr = {
+	.tx_trailingclks		= 0x10,
+	.tx_dif_p_nsec			= 3000000,	/* unit: ns */
+	.tx_dif_n_nsec			= 1000000,	/* unit: ns */
+	.tx_high_z_cnt_nsec		= 20000,	/* unit: ns */
+	.tx_base_unit_nsec		= 100000,	/* unit: ns */
+	.tx_gran_unit_nsec		= 4000,		/* unit: ns */
+	.tx_sleep_cnt			= 1000,		/* unit: ns */
+	.tx_min_activatetime		= 0xa,
+	.rx_filler_enable		= 0x2,
+	.rx_dif_p_nsec			= 1000000,	/* unit: ns */
+	.rx_hibern8_wait_nsec		= 4000000,	/* unit: ns */
+	.rx_base_unit_nsec		= 100000,	/* unit: ns */
+	.rx_gran_unit_nsec		= 4000,		/* unit: ns */
+	.rx_sleep_cnt			= 1280,		/* unit: ns */
+	.rx_stall_cnt			= 320,		/* unit: ns */
+	.rx_hs_g1_sync_len_cap		= SYNC_LEN_COARSE(0xf),
+	.rx_hs_g2_sync_len_cap		= SYNC_LEN_COARSE(0xf),
+	.rx_hs_g3_sync_len_cap		= SYNC_LEN_COARSE(0xf),
+	.rx_hs_g1_prep_sync_len_cap	= PREP_LEN(0xf),
+	.rx_hs_g2_prep_sync_len_cap	= PREP_LEN(0xf),
+	.rx_hs_g3_prep_sync_len_cap	= PREP_LEN(0xf),
+	.pa_dbg_option_suite		= 0x2E820183,
+};
+
+struct exynos_ufs_drv_data fsd_ufs_drvs = {
+	.uic_attr               = &fsd_uic_attr,
+	.quirks                 = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
+				  UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
+				  UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
+				  UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR,
+	.opts                   = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
+				  EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
+				  EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
+				  EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
+	.pre_link               = fsd_ufs_pre_link,
+	.post_link              = fsd_ufs_post_link,
+	.pre_pwr_change         = fsd_ufs_pre_pwr_change,
+};
+
 static const struct of_device_id exynos_ufs_of_match[] = {
 	{ .compatible = "samsung,exynos7-ufs",
 	  .data	      = &exynos_ufs_drvs },
@@ -1602,6 +1741,8 @@ static const struct of_device_id exynos_ufs_of_match[] = {
 	  .data	      = &exynosauto_ufs_drvs },
 	{ .compatible = "samsung,exynosautov9-ufs-vh",
 	  .data	      = &exynosauto_ufs_vh_drvs },
+	{ .compatible = "tesla,fsd-ufs",
+	  .data       = &fsd_ufs_drvs },
 	{},
 };
 
-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 6/6] arm64: dts: fsd: add ufs device node

[Alim Akhtar]

Adds FSD ufs device node and enable the same
for fsd board. This also adds the required
pin configuration for the same.

Cc: linux-fsd@tesla.com
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 arch/arm64/boot/dts/tesla/fsd-evb.dts      |  4 +++
 arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 14 +++++++++++
 arch/arm64/boot/dts/tesla/fsd.dtsi         | 29 ++++++++++++++++++++++
 3 files changed, 47 insertions(+)

diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts
index 5af560c1b5e6..1db6ddf03f01 100644
--- a/arch/arm64/boot/dts/tesla/fsd-evb.dts
+++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts
@@ -37,3 +37,7 @@ &fin_pll {
 &serial_0 {
 	status = "okay";
 };
+
+&ufs {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
index d4d0cb005712..387a41e251d5 100644
--- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
@@ -50,6 +50,20 @@ gpf5: gpf5-gpio-bank {
 		interrupt-controller;
 		#interrupt-cells = <2>;
 	};
+
+	ufs_rst_n: ufs-rst-n-pins {
+		samsung,pins = "gpf5-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
+	};
+
+	ufs_refclk_out: ufs-refclk-out-pins {
+		samsung,pins = "gpf5-1";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
+	};
 };
 
 &pinctrl_peric {
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index af39655331de..a5972e9a2585 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -740,6 +740,35 @@ timer@10040000 {
 			clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>;
 			clock-names = "fin_pll", "mct";
 		};
+
+		ufs: ufs@15120000 {
+			compatible = "tesla,fsd-ufs";
+			reg = <0x0  0x15120000 0x0 0x200>,  /* 0: HCI standard */
+				<0x0 0x15121100 0x0 0x200>,  /* 1: Vendor specified */
+				<0x0 0x15110000 0x0 0x8000>,  /* 2: UNIPRO */
+				<0x0 0x15130000 0x0 0x100>;  /* 3: UFS protector */
+			reg-names = "hci", "vs_hci", "unipro", "ufsp";
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_fsys0 UFS0_TOP0_HCLK_BUS>,
+				<&clock_fsys0 UFS0_TOP0_CLK_UNIPRO>;
+			clock-names = "core_clk", "sclk_unipro_main";
+			freq-table-hz = <0 0>, <0 0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
+			phys = <&ufs_phy>;
+			phy-names = "ufs-phy";
+			status = "disabled";
+		};
+
+		ufs_phy: ufs-phy@15124000 {
+			compatible = "tesla,fsd-ufs-phy";
+			reg = <0x0 0x15124000 0x0 0x800>;
+			reg-names = "phy-pma";
+			samsung,pmu-syscon = <&pmu_system_controller>;
+			#phy-cells = <0>;
+			clocks = <&clock_fsys0 UFS0_MPHY_REFCLK_IXTAL26>;
+			clock-names = "ref_clk";
+		};
 	};
 };
 
-- 
2.25.1

[PATCH 6/6] arm64: dts: fsd: add ufs device node

[Alim Akhtar]

Adds FSD ufs device node and enable the same
for fsd board. This also adds the required
pin configuration for the same.

Cc: linux-fsd@tesla.com
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 arch/arm64/boot/dts/tesla/fsd-evb.dts      |  4 +++
 arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 14 +++++++++++
 arch/arm64/boot/dts/tesla/fsd.dtsi         | 29 ++++++++++++++++++++++
 3 files changed, 47 insertions(+)

diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts
index 5af560c1b5e6..1db6ddf03f01 100644
--- a/arch/arm64/boot/dts/tesla/fsd-evb.dts
+++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts
@@ -37,3 +37,7 @@ &fin_pll {
 &serial_0 {
 	status = "okay";
 };
+
+&ufs {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
index d4d0cb005712..387a41e251d5 100644
--- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
@@ -50,6 +50,20 @@ gpf5: gpf5-gpio-bank {
 		interrupt-controller;
 		#interrupt-cells = <2>;
 	};
+
+	ufs_rst_n: ufs-rst-n-pins {
+		samsung,pins = "gpf5-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
+	};
+
+	ufs_refclk_out: ufs-refclk-out-pins {
+		samsung,pins = "gpf5-1";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
+	};
 };
 
 &pinctrl_peric {
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index af39655331de..a5972e9a2585 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -740,6 +740,35 @@ timer@10040000 {
 			clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>;
 			clock-names = "fin_pll", "mct";
 		};
+
+		ufs: ufs@15120000 {
+			compatible = "tesla,fsd-ufs";
+			reg = <0x0  0x15120000 0x0 0x200>,  /* 0: HCI standard */
+				<0x0 0x15121100 0x0 0x200>,  /* 1: Vendor specified */
+				<0x0 0x15110000 0x0 0x8000>,  /* 2: UNIPRO */
+				<0x0 0x15130000 0x0 0x100>;  /* 3: UFS protector */
+			reg-names = "hci", "vs_hci", "unipro", "ufsp";
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_fsys0 UFS0_TOP0_HCLK_BUS>,
+				<&clock_fsys0 UFS0_TOP0_CLK_UNIPRO>;
+			clock-names = "core_clk", "sclk_unipro_main";
+			freq-table-hz = <0 0>, <0 0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
+			phys = <&ufs_phy>;
+			phy-names = "ufs-phy";
+			status = "disabled";
+		};
+
+		ufs_phy: ufs-phy@15124000 {
+			compatible = "tesla,fsd-ufs-phy";
+			reg = <0x0 0x15124000 0x0 0x800>;
+			reg-names = "phy-pma";
+			samsung,pmu-syscon = <&pmu_system_controller>;
+			#phy-cells = <0>;
+			clocks = <&clock_fsys0 UFS0_MPHY_REFCLK_IXTAL26>;
+			clock-names = "ref_clk";
+		};
 	};
 };
 
-- 
2.25.1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

[PATCH 6/6] arm64: dts: fsd: add ufs device node

[Alim Akhtar]

Adds FSD ufs device node and enable the same
for fsd board. This also adds the required
pin configuration for the same.

Cc: linux-fsd@tesla.com
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 arch/arm64/boot/dts/tesla/fsd-evb.dts      |  4 +++
 arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 14 +++++++++++
 arch/arm64/boot/dts/tesla/fsd.dtsi         | 29 ++++++++++++++++++++++
 3 files changed, 47 insertions(+)

diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts
index 5af560c1b5e6..1db6ddf03f01 100644
--- a/arch/arm64/boot/dts/tesla/fsd-evb.dts
+++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts
@@ -37,3 +37,7 @@ &fin_pll {
 &serial_0 {
 	status = "okay";
 };
+
+&ufs {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
index d4d0cb005712..387a41e251d5 100644
--- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
@@ -50,6 +50,20 @@ gpf5: gpf5-gpio-bank {
 		interrupt-controller;
 		#interrupt-cells = <2>;
 	};
+
+	ufs_rst_n: ufs-rst-n-pins {
+		samsung,pins = "gpf5-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
+	};
+
+	ufs_refclk_out: ufs-refclk-out-pins {
+		samsung,pins = "gpf5-1";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
+	};
 };
 
 &pinctrl_peric {
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index af39655331de..a5972e9a2585 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -740,6 +740,35 @@ timer@10040000 {
 			clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>;
 			clock-names = "fin_pll", "mct";
 		};
+
+		ufs: ufs@15120000 {
+			compatible = "tesla,fsd-ufs";
+			reg = <0x0  0x15120000 0x0 0x200>,  /* 0: HCI standard */
+				<0x0 0x15121100 0x0 0x200>,  /* 1: Vendor specified */
+				<0x0 0x15110000 0x0 0x8000>,  /* 2: UNIPRO */
+				<0x0 0x15130000 0x0 0x100>;  /* 3: UFS protector */
+			reg-names = "hci", "vs_hci", "unipro", "ufsp";
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_fsys0 UFS0_TOP0_HCLK_BUS>,
+				<&clock_fsys0 UFS0_TOP0_CLK_UNIPRO>;
+			clock-names = "core_clk", "sclk_unipro_main";
+			freq-table-hz = <0 0>, <0 0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
+			phys = <&ufs_phy>;
+			phy-names = "ufs-phy";
+			status = "disabled";
+		};
+
+		ufs_phy: ufs-phy@15124000 {
+			compatible = "tesla,fsd-ufs-phy";
+			reg = <0x0 0x15124000 0x0 0x800>;
+			reg-names = "phy-pma";
+			samsung,pmu-syscon = <&pmu_system_controller>;
+			#phy-cells = <0>;
+			clocks = <&clock_fsys0 UFS0_MPHY_REFCLK_IXTAL26>;
+			clock-names = "ref_clk";
+		};
 	};
 };
 
-- 
2.25.1


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Re: [PATCH 1/6] dt-bindings: phy: Add FSD UFS PHY bindings

[Bart Van Assche]

On 5/30/22 18:22, Alim Akhtar wrote:
> Adds tesla,fsd-ufs-phy compatible for Tesla FSD SoC

What does FSD stand for? Please clarify this in the patch description.

Thanks,

Bart.

Re: [PATCH 1/6] dt-bindings: phy: Add FSD UFS PHY bindings

[Bart Van Assche]

On 5/30/22 18:22, Alim Akhtar wrote:
> Adds tesla,fsd-ufs-phy compatible for Tesla FSD SoC

What does FSD stand for? Please clarify this in the patch description.

Thanks,

Bart.

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Re: [PATCH 1/6] dt-bindings: phy: Add FSD UFS PHY bindings

[Bart Van Assche]

On 5/30/22 18:22, Alim Akhtar wrote:
> Adds tesla,fsd-ufs-phy compatible for Tesla FSD SoC

What does FSD stand for? Please clarify this in the patch description.

Thanks,

Bart.

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Re: [PATCH 3/6] phy: samsung-ufs: add support for FSD ufs phy driver

[Bart Van Assche]

On 5/30/22 18:22, Alim Akhtar wrote:
> diff --git a/drivers/phy/samsung/phy-fsd-ufs.c b/drivers/phy/samsung/phy-fsd-ufs.c
> new file mode 100644
> index 000000000000..a03656006093
> --- /dev/null
> +++ b/drivers/phy/samsung/phy-fsd-ufs.c
> @@ -0,0 +1,63 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * UFS PHY driver data for FSD SoC
> + *
> + * Copyright (C) 2022 Samsung Electronics Co., Ltd.
> + *
> + */
> +#ifndef _PHY_FSD_UFS_H_
> +#define _PHY_FSD_UFS_H_

Please do not use header file guards in a .c file.

Thanks,

Bart.

Re: [PATCH 3/6] phy: samsung-ufs: add support for FSD ufs phy driver

[Bart Van Assche]

On 5/30/22 18:22, Alim Akhtar wrote:
> diff --git a/drivers/phy/samsung/phy-fsd-ufs.c b/drivers/phy/samsung/phy-fsd-ufs.c
> new file mode 100644
> index 000000000000..a03656006093
> --- /dev/null
> +++ b/drivers/phy/samsung/phy-fsd-ufs.c
> @@ -0,0 +1,63 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * UFS PHY driver data for FSD SoC
> + *
> + * Copyright (C) 2022 Samsung Electronics Co., Ltd.
> + *
> + */
> +#ifndef _PHY_FSD_UFS_H_
> +#define _PHY_FSD_UFS_H_

Please do not use header file guards in a .c file.

Thanks,

Bart.

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Re: [PATCH 3/6] phy: samsung-ufs: add support for FSD ufs phy driver

[Bart Van Assche]

On 5/30/22 18:22, Alim Akhtar wrote:
> diff --git a/drivers/phy/samsung/phy-fsd-ufs.c b/drivers/phy/samsung/phy-fsd-ufs.c
> new file mode 100644
> index 000000000000..a03656006093
> --- /dev/null
> +++ b/drivers/phy/samsung/phy-fsd-ufs.c
> @@ -0,0 +1,63 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * UFS PHY driver data for FSD SoC
> + *
> + * Copyright (C) 2022 Samsung Electronics Co., Ltd.
> + *
> + */
> +#ifndef _PHY_FSD_UFS_H_
> +#define _PHY_FSD_UFS_H_

Please do not use header file guards in a .c file.

Thanks,

Bart.

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RE: [PATCH 5/6] ufs: host: ufs-exynos: add support for fsd ufs hci

[Chanho Park]

Hi,

> -----Original Message-----
> From: Alim Akhtar <alim.akhtar@samsung.com>
> Sent: Tuesday, May 31, 2022 10:22 AM
> To: linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> linux-scsi@vger.kernel.org; linux-phy@lists.infradead.org
> Cc: devicetree@vger.kernel.org; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; vkoul@kernel.org; avri.altman@wdc.com;
> bvanassche@acm.org; martin.petersen@oracle.com; chanho61.park@samsung.com;
> pankaj.dubey@samsung.com; Alim Akhtar <alim.akhtar@samsung.com>; linux-
> fsd@tesla.com; Bharat Uppal <bharat.uppal@samsung.com>
> Subject: [PATCH 5/6] ufs: host: ufs-exynos: add support for fsd ufs hci
> 
> Adds support of UFS HCI which is found in Tesla FSD SoC. FSD also have an
> addition bit for MPHY APB clock which was not there (was reserved) for
> previous exynos SoC.
> 
> Cc: linux-fsd@tesla.com
> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/ufs/host/ufs-exynos.c | 143 +++++++++++++++++++++++++++++++++-
>  1 file changed, 142 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
> index a81d8cbd542f..b3efdc4caca2 100644
> --- a/drivers/ufs/host/ufs-exynos.c
> +++ b/drivers/ufs/host/ufs-exynos.c
> @@ -52,11 +52,12 @@
>  #define HCI_ERR_EN_DME_LAYER	0x88
>  #define HCI_CLKSTOP_CTRL	0xB0
>  #define REFCLKOUT_STOP		BIT(4)
> +#define MPHY_APBCLK_STOP        BIT(3)
>  #define REFCLK_STOP		BIT(2)
>  #define UNIPRO_MCLK_STOP	BIT(1)
>  #define UNIPRO_PCLK_STOP	BIT(0)
>  #define CLK_STOP_MASK		(REFCLKOUT_STOP | REFCLK_STOP |\
> -				 UNIPRO_MCLK_STOP |\
> +				 UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\

Please make this change into a separate patch of this series.

>  				 UNIPRO_PCLK_STOP)
>  #define HCI_MISC		0xB4
>  #define REFCLK_CTRL_EN		BIT(7)
> @@ -386,6 +387,104 @@ static int exynos7_ufs_post_pwr_change(struct
> exynos_ufs *ufs,
>  	return 0;
>  }
> 
> +static inline int fsd_ufs_pre_link(struct exynos_ufs *ufs) {
> +	int i;
> +	struct ufs_hba *hba = ufs->hba;
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9514), 1000000000L / ufs-
> >mclk_rate);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
> +
> +	for_each_ufs_tx_lane(ufs, i) {
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i), 1000000000L /
> ufs->mclk_rate);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F);
> +	}
> +
> +	for_each_ufs_rx_lane(ufs, i) {
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i), 1000000000L /
> ufs->mclk_rate);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0);
> +	}
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9536), 0x4E20);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9564), 0x2e820183);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x155E), 0x0);

Use PA_LOCAL_TX_LCC_ENABLE instead of 0x155E. I think you can find more values from unipro.h.
Please try to use as much as possible :)

> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x3000), 0x0);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x3001), 0x1);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x4021), 0x1);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x4020), 0x1);

They can be set from exynos_ufs_establish_connt.

> +
> +	return 0;
> +}
> +
> +static inline int fsd_ufs_post_link(struct exynos_ufs *ufs) {
> +	int i;
> +	struct ufs_hba *hba = ufs->hba;
> +	u32 hw_cap_min_tactivate;
> +	u32 peer_rx_min_actv_time_cap;
> +	u32 max_rx_hibern8_time_cap;
> +
> +	ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4),
> +			&hw_cap_min_tactivate); /* HW Capability of
> MIN_TACTIVATE */
> +	ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A8),
> +			&peer_rx_min_actv_time_cap);    /* PA_TActivate */
> +	ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A7),
> +			&max_rx_hibern8_time_cap);      /* PA_Hibern8Time */
> +
> +	if (peer_rx_min_actv_time_cap >= hw_cap_min_tactivate)
> +		ufshcd_dme_peer_set(hba, UIC_ARG_MIB(0x15A8),
> +					peer_rx_min_actv_time_cap + 1);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A7), max_rx_hibern8_time_cap +
> 1);
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x01);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A4), 0xFA);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x00);
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
> +
> +	for_each_ufs_rx_lane(ufs, i) {
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC);
> +	}
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
> +
> +	return 0;
> +}
> +
> +static inline int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs,
> +					struct ufs_pa_layer_attr *pwr)
> +{
> +	struct ufs_hba *hba = ufs->hba;
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x1569), 0x1);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x1584), 0x1);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2041), 8064);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2042), 28224);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2043), 20160);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B0), 12000);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B1), 32000);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B2), 16000);
> +
> +	unipro_writel(ufs, 8064, 0x7888);
> +	unipro_writel(ufs, 28224, 0x788C);
> +	unipro_writel(ufs, 20160, 0x7890);
> +	unipro_writel(ufs, 12000, 0x78B8);
> +	unipro_writel(ufs, 32000, 0x78BC);
> +	unipro_writel(ufs, 16000, 0x78C0);
> +
> +	return 0;
> +}
> +
>  /*
>   * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w
>   * Control should be disabled in the below cases @@ -1595,6 +1694,46 @@
> static struct exynos_ufs_drv_data exynos_ufs_drvs = {
>  	.post_pwr_change	= exynos7_ufs_post_pwr_change,
>  };
> 
> +static struct exynos_ufs_uic_attr fsd_uic_attr = {
> +	.tx_trailingclks		= 0x10,
> +	.tx_dif_p_nsec			= 3000000,	/* unit: ns */
> +	.tx_dif_n_nsec			= 1000000,	/* unit: ns */
> +	.tx_high_z_cnt_nsec		= 20000,	/* unit: ns */
> +	.tx_base_unit_nsec		= 100000,	/* unit: ns */
> +	.tx_gran_unit_nsec		= 4000,		/* unit: ns */
> +	.tx_sleep_cnt			= 1000,		/* unit: ns */
> +	.tx_min_activatetime		= 0xa,
> +	.rx_filler_enable		= 0x2,
> +	.rx_dif_p_nsec			= 1000000,	/* unit: ns */
> +	.rx_hibern8_wait_nsec		= 4000000,	/* unit: ns */
> +	.rx_base_unit_nsec		= 100000,	/* unit: ns */
> +	.rx_gran_unit_nsec		= 4000,		/* unit: ns */
> +	.rx_sleep_cnt			= 1280,		/* unit: ns */
> +	.rx_stall_cnt			= 320,		/* unit: ns */
> +	.rx_hs_g1_sync_len_cap		= SYNC_LEN_COARSE(0xf),
> +	.rx_hs_g2_sync_len_cap		= SYNC_LEN_COARSE(0xf),
> +	.rx_hs_g3_sync_len_cap		= SYNC_LEN_COARSE(0xf),
> +	.rx_hs_g1_prep_sync_len_cap	= PREP_LEN(0xf),
> +	.rx_hs_g2_prep_sync_len_cap	= PREP_LEN(0xf),
> +	.rx_hs_g3_prep_sync_len_cap	= PREP_LEN(0xf),
> +	.pa_dbg_option_suite		= 0x2E820183,
> +};
> +
> +struct exynos_ufs_drv_data fsd_ufs_drvs = {
> +	.uic_attr               = &fsd_uic_attr,
> +	.quirks                 = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
> +				  UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
> +				  UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
> +				  UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR,
> +	.opts                   = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
> +				  EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
> +				  EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
> +				  EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
> +	.pre_link               = fsd_ufs_pre_link,
> +	.post_link              = fsd_ufs_post_link,
> +	.pre_pwr_change         = fsd_ufs_pre_pwr_change,
> +};
> +
>  static const struct of_device_id exynos_ufs_of_match[] = {
>  	{ .compatible = "samsung,exynos7-ufs",
>  	  .data	      = &exynos_ufs_drvs },
> @@ -1602,6 +1741,8 @@ static const struct of_device_id
> exynos_ufs_of_match[] = {
>  	  .data	      = &exynosauto_ufs_drvs },
>  	{ .compatible = "samsung,exynosautov9-ufs-vh",
>  	  .data	      = &exynosauto_ufs_vh_drvs },
> +	{ .compatible = "tesla,fsd-ufs",
> +	  .data       = &fsd_ufs_drvs },
>  	{},
>  };
> 
> --
> 2.25.1

RE: [PATCH 5/6] ufs: host: ufs-exynos: add support for fsd ufs hci

[Chanho Park]

Hi,

> -----Original Message-----
> From: Alim Akhtar <alim.akhtar@samsung.com>
> Sent: Tuesday, May 31, 2022 10:22 AM
> To: linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> linux-scsi@vger.kernel.org; linux-phy@lists.infradead.org
> Cc: devicetree@vger.kernel.org; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; vkoul@kernel.org; avri.altman@wdc.com;
> bvanassche@acm.org; martin.petersen@oracle.com; chanho61.park@samsung.com;
> pankaj.dubey@samsung.com; Alim Akhtar <alim.akhtar@samsung.com>; linux-
> fsd@tesla.com; Bharat Uppal <bharat.uppal@samsung.com>
> Subject: [PATCH 5/6] ufs: host: ufs-exynos: add support for fsd ufs hci
> 
> Adds support of UFS HCI which is found in Tesla FSD SoC. FSD also have an
> addition bit for MPHY APB clock which was not there (was reserved) for
> previous exynos SoC.
> 
> Cc: linux-fsd@tesla.com
> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/ufs/host/ufs-exynos.c | 143 +++++++++++++++++++++++++++++++++-
>  1 file changed, 142 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
> index a81d8cbd542f..b3efdc4caca2 100644
> --- a/drivers/ufs/host/ufs-exynos.c
> +++ b/drivers/ufs/host/ufs-exynos.c
> @@ -52,11 +52,12 @@
>  #define HCI_ERR_EN_DME_LAYER	0x88
>  #define HCI_CLKSTOP_CTRL	0xB0
>  #define REFCLKOUT_STOP		BIT(4)
> +#define MPHY_APBCLK_STOP        BIT(3)
>  #define REFCLK_STOP		BIT(2)
>  #define UNIPRO_MCLK_STOP	BIT(1)
>  #define UNIPRO_PCLK_STOP	BIT(0)
>  #define CLK_STOP_MASK		(REFCLKOUT_STOP | REFCLK_STOP |\
> -				 UNIPRO_MCLK_STOP |\
> +				 UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\

Please make this change into a separate patch of this series.

>  				 UNIPRO_PCLK_STOP)
>  #define HCI_MISC		0xB4
>  #define REFCLK_CTRL_EN		BIT(7)
> @@ -386,6 +387,104 @@ static int exynos7_ufs_post_pwr_change(struct
> exynos_ufs *ufs,
>  	return 0;
>  }
> 
> +static inline int fsd_ufs_pre_link(struct exynos_ufs *ufs) {
> +	int i;
> +	struct ufs_hba *hba = ufs->hba;
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9514), 1000000000L / ufs-
> >mclk_rate);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
> +
> +	for_each_ufs_tx_lane(ufs, i) {
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i), 1000000000L /
> ufs->mclk_rate);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F);
> +	}
> +
> +	for_each_ufs_rx_lane(ufs, i) {
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i), 1000000000L /
> ufs->mclk_rate);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0);
> +	}
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9536), 0x4E20);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9564), 0x2e820183);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x155E), 0x0);

Use PA_LOCAL_TX_LCC_ENABLE instead of 0x155E. I think you can find more values from unipro.h.
Please try to use as much as possible :)

> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x3000), 0x0);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x3001), 0x1);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x4021), 0x1);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x4020), 0x1);

They can be set from exynos_ufs_establish_connt.

> +
> +	return 0;
> +}
> +
> +static inline int fsd_ufs_post_link(struct exynos_ufs *ufs) {
> +	int i;
> +	struct ufs_hba *hba = ufs->hba;
> +	u32 hw_cap_min_tactivate;
> +	u32 peer_rx_min_actv_time_cap;
> +	u32 max_rx_hibern8_time_cap;
> +
> +	ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4),
> +			&hw_cap_min_tactivate); /* HW Capability of
> MIN_TACTIVATE */
> +	ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A8),
> +			&peer_rx_min_actv_time_cap);    /* PA_TActivate */
> +	ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A7),
> +			&max_rx_hibern8_time_cap);      /* PA_Hibern8Time */
> +
> +	if (peer_rx_min_actv_time_cap >= hw_cap_min_tactivate)
> +		ufshcd_dme_peer_set(hba, UIC_ARG_MIB(0x15A8),
> +					peer_rx_min_actv_time_cap + 1);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A7), max_rx_hibern8_time_cap +
> 1);
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x01);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A4), 0xFA);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x00);
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
> +
> +	for_each_ufs_rx_lane(ufs, i) {
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC);
> +	}
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
> +
> +	return 0;
> +}
> +
> +static inline int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs,
> +					struct ufs_pa_layer_attr *pwr)
> +{
> +	struct ufs_hba *hba = ufs->hba;
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x1569), 0x1);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x1584), 0x1);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2041), 8064);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2042), 28224);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2043), 20160);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B0), 12000);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B1), 32000);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B2), 16000);
> +
> +	unipro_writel(ufs, 8064, 0x7888);
> +	unipro_writel(ufs, 28224, 0x788C);
> +	unipro_writel(ufs, 20160, 0x7890);
> +	unipro_writel(ufs, 12000, 0x78B8);
> +	unipro_writel(ufs, 32000, 0x78BC);
> +	unipro_writel(ufs, 16000, 0x78C0);
> +
> +	return 0;
> +}
> +
>  /*
>   * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w
>   * Control should be disabled in the below cases @@ -1595,6 +1694,46 @@
> static struct exynos_ufs_drv_data exynos_ufs_drvs = {
>  	.post_pwr_change	= exynos7_ufs_post_pwr_change,
>  };
> 
> +static struct exynos_ufs_uic_attr fsd_uic_attr = {
> +	.tx_trailingclks		= 0x10,
> +	.tx_dif_p_nsec			= 3000000,	/* unit: ns */
> +	.tx_dif_n_nsec			= 1000000,	/* unit: ns */
> +	.tx_high_z_cnt_nsec		= 20000,	/* unit: ns */
> +	.tx_base_unit_nsec		= 100000,	/* unit: ns */
> +	.tx_gran_unit_nsec		= 4000,		/* unit: ns */
> +	.tx_sleep_cnt			= 1000,		/* unit: ns */
> +	.tx_min_activatetime		= 0xa,
> +	.rx_filler_enable		= 0x2,
> +	.rx_dif_p_nsec			= 1000000,	/* unit: ns */
> +	.rx_hibern8_wait_nsec		= 4000000,	/* unit: ns */
> +	.rx_base_unit_nsec		= 100000,	/* unit: ns */
> +	.rx_gran_unit_nsec		= 4000,		/* unit: ns */
> +	.rx_sleep_cnt			= 1280,		/* unit: ns */
> +	.rx_stall_cnt			= 320,		/* unit: ns */
> +	.rx_hs_g1_sync_len_cap		= SYNC_LEN_COARSE(0xf),
> +	.rx_hs_g2_sync_len_cap		= SYNC_LEN_COARSE(0xf),
> +	.rx_hs_g3_sync_len_cap		= SYNC_LEN_COARSE(0xf),
> +	.rx_hs_g1_prep_sync_len_cap	= PREP_LEN(0xf),
> +	.rx_hs_g2_prep_sync_len_cap	= PREP_LEN(0xf),
> +	.rx_hs_g3_prep_sync_len_cap	= PREP_LEN(0xf),
> +	.pa_dbg_option_suite		= 0x2E820183,
> +};
> +
> +struct exynos_ufs_drv_data fsd_ufs_drvs = {
> +	.uic_attr               = &fsd_uic_attr,
> +	.quirks                 = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
> +				  UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
> +				  UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
> +				  UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR,
> +	.opts                   = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
> +				  EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
> +				  EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
> +				  EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
> +	.pre_link               = fsd_ufs_pre_link,
> +	.post_link              = fsd_ufs_post_link,
> +	.pre_pwr_change         = fsd_ufs_pre_pwr_change,
> +};
> +
>  static const struct of_device_id exynos_ufs_of_match[] = {
>  	{ .compatible = "samsung,exynos7-ufs",
>  	  .data	      = &exynos_ufs_drvs },
> @@ -1602,6 +1741,8 @@ static const struct of_device_id
> exynos_ufs_of_match[] = {
>  	  .data	      = &exynosauto_ufs_drvs },
>  	{ .compatible = "samsung,exynosautov9-ufs-vh",
>  	  .data	      = &exynosauto_ufs_vh_drvs },
> +	{ .compatible = "tesla,fsd-ufs",
> +	  .data       = &fsd_ufs_drvs },
>  	{},
>  };
> 
> --
> 2.25.1



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RE: [PATCH 5/6] ufs: host: ufs-exynos: add support for fsd ufs hci

[Chanho Park]

Hi,

> -----Original Message-----
> From: Alim Akhtar <alim.akhtar@samsung.com>
> Sent: Tuesday, May 31, 2022 10:22 AM
> To: linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> linux-scsi@vger.kernel.org; linux-phy@lists.infradead.org
> Cc: devicetree@vger.kernel.org; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; vkoul@kernel.org; avri.altman@wdc.com;
> bvanassche@acm.org; martin.petersen@oracle.com; chanho61.park@samsung.com;
> pankaj.dubey@samsung.com; Alim Akhtar <alim.akhtar@samsung.com>; linux-
> fsd@tesla.com; Bharat Uppal <bharat.uppal@samsung.com>
> Subject: [PATCH 5/6] ufs: host: ufs-exynos: add support for fsd ufs hci
> 
> Adds support of UFS HCI which is found in Tesla FSD SoC. FSD also have an
> addition bit for MPHY APB clock which was not there (was reserved) for
> previous exynos SoC.
> 
> Cc: linux-fsd@tesla.com
> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/ufs/host/ufs-exynos.c | 143 +++++++++++++++++++++++++++++++++-
>  1 file changed, 142 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
> index a81d8cbd542f..b3efdc4caca2 100644
> --- a/drivers/ufs/host/ufs-exynos.c
> +++ b/drivers/ufs/host/ufs-exynos.c
> @@ -52,11 +52,12 @@
>  #define HCI_ERR_EN_DME_LAYER	0x88
>  #define HCI_CLKSTOP_CTRL	0xB0
>  #define REFCLKOUT_STOP		BIT(4)
> +#define MPHY_APBCLK_STOP        BIT(3)
>  #define REFCLK_STOP		BIT(2)
>  #define UNIPRO_MCLK_STOP	BIT(1)
>  #define UNIPRO_PCLK_STOP	BIT(0)
>  #define CLK_STOP_MASK		(REFCLKOUT_STOP | REFCLK_STOP |\
> -				 UNIPRO_MCLK_STOP |\
> +				 UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\

Please make this change into a separate patch of this series.

>  				 UNIPRO_PCLK_STOP)
>  #define HCI_MISC		0xB4
>  #define REFCLK_CTRL_EN		BIT(7)
> @@ -386,6 +387,104 @@ static int exynos7_ufs_post_pwr_change(struct
> exynos_ufs *ufs,
>  	return 0;
>  }
> 
> +static inline int fsd_ufs_pre_link(struct exynos_ufs *ufs) {
> +	int i;
> +	struct ufs_hba *hba = ufs->hba;
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9514), 1000000000L / ufs-
> >mclk_rate);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
> +
> +	for_each_ufs_tx_lane(ufs, i) {
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i), 1000000000L /
> ufs->mclk_rate);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F);
> +	}
> +
> +	for_each_ufs_rx_lane(ufs, i) {
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i), 1000000000L /
> ufs->mclk_rate);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0);
> +	}
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9536), 0x4E20);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9564), 0x2e820183);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x155E), 0x0);

Use PA_LOCAL_TX_LCC_ENABLE instead of 0x155E. I think you can find more values from unipro.h.
Please try to use as much as possible :)

> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x3000), 0x0);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x3001), 0x1);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x4021), 0x1);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x4020), 0x1);

They can be set from exynos_ufs_establish_connt.

> +
> +	return 0;
> +}
> +
> +static inline int fsd_ufs_post_link(struct exynos_ufs *ufs) {
> +	int i;
> +	struct ufs_hba *hba = ufs->hba;
> +	u32 hw_cap_min_tactivate;
> +	u32 peer_rx_min_actv_time_cap;
> +	u32 max_rx_hibern8_time_cap;
> +
> +	ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4),
> +			&hw_cap_min_tactivate); /* HW Capability of
> MIN_TACTIVATE */
> +	ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A8),
> +			&peer_rx_min_actv_time_cap);    /* PA_TActivate */
> +	ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A7),
> +			&max_rx_hibern8_time_cap);      /* PA_Hibern8Time */
> +
> +	if (peer_rx_min_actv_time_cap >= hw_cap_min_tactivate)
> +		ufshcd_dme_peer_set(hba, UIC_ARG_MIB(0x15A8),
> +					peer_rx_min_actv_time_cap + 1);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A7), max_rx_hibern8_time_cap +
> 1);
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x01);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A4), 0xFA);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x00);
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
> +
> +	for_each_ufs_rx_lane(ufs, i) {
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC);
> +	}
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
> +
> +	return 0;
> +}
> +
> +static inline int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs,
> +					struct ufs_pa_layer_attr *pwr)
> +{
> +	struct ufs_hba *hba = ufs->hba;
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x1569), 0x1);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x1584), 0x1);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2041), 8064);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2042), 28224);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2043), 20160);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B0), 12000);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B1), 32000);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B2), 16000);
> +
> +	unipro_writel(ufs, 8064, 0x7888);
> +	unipro_writel(ufs, 28224, 0x788C);
> +	unipro_writel(ufs, 20160, 0x7890);
> +	unipro_writel(ufs, 12000, 0x78B8);
> +	unipro_writel(ufs, 32000, 0x78BC);
> +	unipro_writel(ufs, 16000, 0x78C0);
> +
> +	return 0;
> +}
> +
>  /*
>   * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w
>   * Control should be disabled in the below cases @@ -1595,6 +1694,46 @@
> static struct exynos_ufs_drv_data exynos_ufs_drvs = {
>  	.post_pwr_change	= exynos7_ufs_post_pwr_change,
>  };
> 
> +static struct exynos_ufs_uic_attr fsd_uic_attr = {
> +	.tx_trailingclks		= 0x10,
> +	.tx_dif_p_nsec			= 3000000,	/* unit: ns */
> +	.tx_dif_n_nsec			= 1000000,	/* unit: ns */
> +	.tx_high_z_cnt_nsec		= 20000,	/* unit: ns */
> +	.tx_base_unit_nsec		= 100000,	/* unit: ns */
> +	.tx_gran_unit_nsec		= 4000,		/* unit: ns */
> +	.tx_sleep_cnt			= 1000,		/* unit: ns */
> +	.tx_min_activatetime		= 0xa,
> +	.rx_filler_enable		= 0x2,
> +	.rx_dif_p_nsec			= 1000000,	/* unit: ns */
> +	.rx_hibern8_wait_nsec		= 4000000,	/* unit: ns */
> +	.rx_base_unit_nsec		= 100000,	/* unit: ns */
> +	.rx_gran_unit_nsec		= 4000,		/* unit: ns */
> +	.rx_sleep_cnt			= 1280,		/* unit: ns */
> +	.rx_stall_cnt			= 320,		/* unit: ns */
> +	.rx_hs_g1_sync_len_cap		= SYNC_LEN_COARSE(0xf),
> +	.rx_hs_g2_sync_len_cap		= SYNC_LEN_COARSE(0xf),
> +	.rx_hs_g3_sync_len_cap		= SYNC_LEN_COARSE(0xf),
> +	.rx_hs_g1_prep_sync_len_cap	= PREP_LEN(0xf),
> +	.rx_hs_g2_prep_sync_len_cap	= PREP_LEN(0xf),
> +	.rx_hs_g3_prep_sync_len_cap	= PREP_LEN(0xf),
> +	.pa_dbg_option_suite		= 0x2E820183,
> +};
> +
> +struct exynos_ufs_drv_data fsd_ufs_drvs = {
> +	.uic_attr               = &fsd_uic_attr,
> +	.quirks                 = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
> +				  UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
> +				  UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
> +				  UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR,
> +	.opts                   = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
> +				  EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
> +				  EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
> +				  EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
> +	.pre_link               = fsd_ufs_pre_link,
> +	.post_link              = fsd_ufs_post_link,
> +	.pre_pwr_change         = fsd_ufs_pre_pwr_change,
> +};
> +
>  static const struct of_device_id exynos_ufs_of_match[] = {
>  	{ .compatible = "samsung,exynos7-ufs",
>  	  .data	      = &exynos_ufs_drvs },
> @@ -1602,6 +1741,8 @@ static const struct of_device_id
> exynos_ufs_of_match[] = {
>  	  .data	      = &exynosauto_ufs_drvs },
>  	{ .compatible = "samsung,exynosautov9-ufs-vh",
>  	  .data	      = &exynosauto_ufs_vh_drvs },
> +	{ .compatible = "tesla,fsd-ufs",
> +	  .data       = &fsd_ufs_drvs },
>  	{},
>  };
> 
> --
> 2.25.1



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Re: [PATCH 1/6] dt-bindings: phy: Add FSD UFS PHY bindings

[Krzysztof Kozlowski]

On 31/05/2022 03:22, Alim Akhtar wrote:
> Adds tesla,fsd-ufs-phy compatible for Tesla FSD SoC

s/Adds/Add/
and a full stop at the end, please.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 1/6] dt-bindings: phy: Add FSD UFS PHY bindings

[Krzysztof Kozlowski]

On 31/05/2022 03:22, Alim Akhtar wrote:
> Adds tesla,fsd-ufs-phy compatible for Tesla FSD SoC

s/Adds/Add/
and a full stop at the end, please.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

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Re: [PATCH 1/6] dt-bindings: phy: Add FSD UFS PHY bindings

[Krzysztof Kozlowski]

On 31/05/2022 03:22, Alim Akhtar wrote:
> Adds tesla,fsd-ufs-phy compatible for Tesla FSD SoC

s/Adds/Add/
and a full stop at the end, please.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

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Re: [PATCH 2/6] phy: samsung-ufs: move cdr offset to drvdata

[Krzysztof Kozlowski]

On 31/05/2022 03:22, Alim Akhtar wrote:
> Move CDR lock offset to drv data so that it can
> be extended for other SoCs which are having CDR
> lock at different register offset.
> 
> Cc: linux-fsd@tesla.com
> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/phy/samsung/phy-exynos7-ufs.c      | 3 +++
>  drivers/phy/samsung/phy-exynosautov9-ufs.c | 2 ++
>  drivers/phy/samsung/phy-samsung-ufs.c      | 3 ++-
>  drivers/phy/samsung/phy-samsung-ufs.h      | 2 +-
>  4 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c b/drivers/phy/samsung/phy-exynos7-ufs.c
> index 7c9008e163db..d1a37273cb1f 100644
> --- a/drivers/phy/samsung/phy-exynos7-ufs.c
> +++ b/drivers/phy/samsung/phy-exynos7-ufs.c
> @@ -11,6 +11,8 @@
>  #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK	0x1
>  #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN	BIT(0)
>  
> +#define PHY_CDR_LOCK_STATUS    0x5e

This should be now renamed to match other defines here, so
EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS


Best regards,
Krzysztof

Re: [PATCH 2/6] phy: samsung-ufs: move cdr offset to drvdata

[Krzysztof Kozlowski]

On 31/05/2022 03:22, Alim Akhtar wrote:
> Move CDR lock offset to drv data so that it can
> be extended for other SoCs which are having CDR
> lock at different register offset.
> 
> Cc: linux-fsd@tesla.com
> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/phy/samsung/phy-exynos7-ufs.c      | 3 +++
>  drivers/phy/samsung/phy-exynosautov9-ufs.c | 2 ++
>  drivers/phy/samsung/phy-samsung-ufs.c      | 3 ++-
>  drivers/phy/samsung/phy-samsung-ufs.h      | 2 +-
>  4 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c b/drivers/phy/samsung/phy-exynos7-ufs.c
> index 7c9008e163db..d1a37273cb1f 100644
> --- a/drivers/phy/samsung/phy-exynos7-ufs.c
> +++ b/drivers/phy/samsung/phy-exynos7-ufs.c
> @@ -11,6 +11,8 @@
>  #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK	0x1
>  #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN	BIT(0)
>  
> +#define PHY_CDR_LOCK_STATUS    0x5e

This should be now renamed to match other defines here, so
EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS


Best regards,
Krzysztof

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Re: [PATCH 2/6] phy: samsung-ufs: move cdr offset to drvdata

[Krzysztof Kozlowski]

On 31/05/2022 03:22, Alim Akhtar wrote:
> Move CDR lock offset to drv data so that it can
> be extended for other SoCs which are having CDR
> lock at different register offset.
> 
> Cc: linux-fsd@tesla.com
> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/phy/samsung/phy-exynos7-ufs.c      | 3 +++
>  drivers/phy/samsung/phy-exynosautov9-ufs.c | 2 ++
>  drivers/phy/samsung/phy-samsung-ufs.c      | 3 ++-
>  drivers/phy/samsung/phy-samsung-ufs.h      | 2 +-
>  4 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c b/drivers/phy/samsung/phy-exynos7-ufs.c
> index 7c9008e163db..d1a37273cb1f 100644
> --- a/drivers/phy/samsung/phy-exynos7-ufs.c
> +++ b/drivers/phy/samsung/phy-exynos7-ufs.c
> @@ -11,6 +11,8 @@
>  #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK	0x1
>  #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN	BIT(0)
>  
> +#define PHY_CDR_LOCK_STATUS    0x5e

This should be now renamed to match other defines here, so
EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS


Best regards,
Krzysztof

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Re: [PATCH 4/6] dt-bindings: ufs: exynos-ufs: add fsd compatible

[Krzysztof Kozlowski]

On 31/05/2022 03:22, Alim Akhtar wrote:
> Adds tesla,fsd-ufs compatible for Tesla FSD SoC.
> 
> Cc: linux-fsd@tesla.com
> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

Re: [PATCH 4/6] dt-bindings: ufs: exynos-ufs: add fsd compatible

[Krzysztof Kozlowski]

On 31/05/2022 03:22, Alim Akhtar wrote:
> Adds tesla,fsd-ufs compatible for Tesla FSD SoC.
> 
> Cc: linux-fsd@tesla.com
> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

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Re: [PATCH 4/6] dt-bindings: ufs: exynos-ufs: add fsd compatible

[Krzysztof Kozlowski]

On 31/05/2022 03:22, Alim Akhtar wrote:
> Adds tesla,fsd-ufs compatible for Tesla FSD SoC.
> 
> Cc: linux-fsd@tesla.com
> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

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Re: [PATCH 5/6] ufs: host: ufs-exynos: add support for fsd ufs hci

[Krzysztof Kozlowski]

On 31/05/2022 03:22, Alim Akhtar wrote:
> Adds support of UFS HCI which is found in Tesla
> FSD SoC. FSD also have an addition bit for MPHY
> APB clock which was not there (was reserved) for
> previous exynos SoC.

Weird wrapping.

> 
> Cc: linux-fsd@tesla.com
> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/ufs/host/ufs-exynos.c | 143 +++++++++++++++++++++++++++++++++-
>  1 file changed, 142 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
> index a81d8cbd542f..b3efdc4caca2 100644
> --- a/drivers/ufs/host/ufs-exynos.c
> +++ b/drivers/ufs/host/ufs-exynos.c
> @@ -52,11 +52,12 @@
>  #define HCI_ERR_EN_DME_LAYER	0x88
>  #define HCI_CLKSTOP_CTRL	0xB0
>  #define REFCLKOUT_STOP		BIT(4)
> +#define MPHY_APBCLK_STOP        BIT(3)

Inconsistent indentation.


Best regards,
Krzysztof

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Re: [PATCH 5/6] ufs: host: ufs-exynos: add support for fsd ufs hci

[Krzysztof Kozlowski]

On 31/05/2022 03:22, Alim Akhtar wrote:
> Adds support of UFS HCI which is found in Tesla
> FSD SoC. FSD also have an addition bit for MPHY
> APB clock which was not there (was reserved) for
> previous exynos SoC.

Weird wrapping.

> 
> Cc: linux-fsd@tesla.com
> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/ufs/host/ufs-exynos.c | 143 +++++++++++++++++++++++++++++++++-
>  1 file changed, 142 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
> index a81d8cbd542f..b3efdc4caca2 100644
> --- a/drivers/ufs/host/ufs-exynos.c
> +++ b/drivers/ufs/host/ufs-exynos.c
> @@ -52,11 +52,12 @@
>  #define HCI_ERR_EN_DME_LAYER	0x88
>  #define HCI_CLKSTOP_CTRL	0xB0
>  #define REFCLKOUT_STOP		BIT(4)
> +#define MPHY_APBCLK_STOP        BIT(3)

Inconsistent indentation.


Best regards,
Krzysztof

Re: [PATCH 5/6] ufs: host: ufs-exynos: add support for fsd ufs hci

[Krzysztof Kozlowski]

On 31/05/2022 03:22, Alim Akhtar wrote:
> Adds support of UFS HCI which is found in Tesla
> FSD SoC. FSD also have an addition bit for MPHY
> APB clock which was not there (was reserved) for
> previous exynos SoC.

Weird wrapping.

> 
> Cc: linux-fsd@tesla.com
> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/ufs/host/ufs-exynos.c | 143 +++++++++++++++++++++++++++++++++-
>  1 file changed, 142 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
> index a81d8cbd542f..b3efdc4caca2 100644
> --- a/drivers/ufs/host/ufs-exynos.c
> +++ b/drivers/ufs/host/ufs-exynos.c
> @@ -52,11 +52,12 @@
>  #define HCI_ERR_EN_DME_LAYER	0x88
>  #define HCI_CLKSTOP_CTRL	0xB0
>  #define REFCLKOUT_STOP		BIT(4)
> +#define MPHY_APBCLK_STOP        BIT(3)

Inconsistent indentation.


Best regards,
Krzysztof

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Re: [PATCH 6/6] arm64: dts: fsd: add ufs device node

[Krzysztof Kozlowski]

On 31/05/2022 03:22, Alim Akhtar wrote:
> Adds FSD ufs device node and enable the same
> for fsd board. This also adds the required
> pin configuration for the same.
> 
> Cc: linux-fsd@tesla.com
> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  arch/arm64/boot/dts/tesla/fsd-evb.dts      |  4 +++
>  arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 14 +++++++++++
>  arch/arm64/boot/dts/tesla/fsd.dtsi         | 29 ++++++++++++++++++++++
>  3 files changed, 47 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts
> index 5af560c1b5e6..1db6ddf03f01 100644
> --- a/arch/arm64/boot/dts/tesla/fsd-evb.dts
> +++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts
> @@ -37,3 +37,7 @@ &fin_pll {
>  &serial_0 {
>  	status = "okay";
>  };
> +
> +&ufs {
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
> index d4d0cb005712..387a41e251d5 100644
> --- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
> +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
> @@ -50,6 +50,20 @@ gpf5: gpf5-gpio-bank {
>  		interrupt-controller;
>  		#interrupt-cells = <2>;
>  	};
> +
> +	ufs_rst_n: ufs-rst-n-pins {
> +		samsung,pins = "gpf5-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
> +	};
> +
> +	ufs_refclk_out: ufs-refclk-out-pins {
> +		samsung,pins = "gpf5-1";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
> +	};
>  };
>  
>  &pinctrl_peric {
> diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
> index af39655331de..a5972e9a2585 100644
> --- a/arch/arm64/boot/dts/tesla/fsd.dtsi
> +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
> @@ -740,6 +740,35 @@ timer@10040000 {
>  			clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>;
>  			clock-names = "fin_pll", "mct";
>  		};
> +
> +		ufs: ufs@15120000 {
> +			compatible = "tesla,fsd-ufs";
> +			reg = <0x0  0x15120000 0x0 0x200>,  /* 0: HCI standard */

Double space after 0x0

> +				<0x0 0x15121100 0x0 0x200>,  /* 1: Vendor specified */

Please align with opening < in line before.

> +				<0x0 0x15110000 0x0 0x8000>,  /* 2: UNIPRO */
> +				<0x0 0x15130000 0x0 0x100>;  /* 3: UFS protector */
> +			reg-names = "hci", "vs_hci", "unipro", "ufsp";
> +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clock_fsys0 UFS0_TOP0_HCLK_BUS>,
> +				<&clock_fsys0 UFS0_TOP0_CLK_UNIPRO>;

Also align.


Best regards,
Krzysztof

Re: [PATCH 6/6] arm64: dts: fsd: add ufs device node

[Krzysztof Kozlowski]

On 31/05/2022 03:22, Alim Akhtar wrote:
> Adds FSD ufs device node and enable the same
> for fsd board. This also adds the required
> pin configuration for the same.
> 
> Cc: linux-fsd@tesla.com
> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  arch/arm64/boot/dts/tesla/fsd-evb.dts      |  4 +++
>  arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 14 +++++++++++
>  arch/arm64/boot/dts/tesla/fsd.dtsi         | 29 ++++++++++++++++++++++
>  3 files changed, 47 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts
> index 5af560c1b5e6..1db6ddf03f01 100644
> --- a/arch/arm64/boot/dts/tesla/fsd-evb.dts
> +++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts
> @@ -37,3 +37,7 @@ &fin_pll {
>  &serial_0 {
>  	status = "okay";
>  };
> +
> +&ufs {
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
> index d4d0cb005712..387a41e251d5 100644
> --- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
> +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
> @@ -50,6 +50,20 @@ gpf5: gpf5-gpio-bank {
>  		interrupt-controller;
>  		#interrupt-cells = <2>;
>  	};
> +
> +	ufs_rst_n: ufs-rst-n-pins {
> +		samsung,pins = "gpf5-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
> +	};
> +
> +	ufs_refclk_out: ufs-refclk-out-pins {
> +		samsung,pins = "gpf5-1";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
> +	};
>  };
>  
>  &pinctrl_peric {
> diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
> index af39655331de..a5972e9a2585 100644
> --- a/arch/arm64/boot/dts/tesla/fsd.dtsi
> +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
> @@ -740,6 +740,35 @@ timer@10040000 {
>  			clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>;
>  			clock-names = "fin_pll", "mct";
>  		};
> +
> +		ufs: ufs@15120000 {
> +			compatible = "tesla,fsd-ufs";
> +			reg = <0x0  0x15120000 0x0 0x200>,  /* 0: HCI standard */

Double space after 0x0

> +				<0x0 0x15121100 0x0 0x200>,  /* 1: Vendor specified */

Please align with opening < in line before.

> +				<0x0 0x15110000 0x0 0x8000>,  /* 2: UNIPRO */
> +				<0x0 0x15130000 0x0 0x100>;  /* 3: UFS protector */
> +			reg-names = "hci", "vs_hci", "unipro", "ufsp";
> +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clock_fsys0 UFS0_TOP0_HCLK_BUS>,
> +				<&clock_fsys0 UFS0_TOP0_CLK_UNIPRO>;

Also align.


Best regards,
Krzysztof

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Re: [PATCH 6/6] arm64: dts: fsd: add ufs device node

[Krzysztof Kozlowski]

On 31/05/2022 03:22, Alim Akhtar wrote:
> Adds FSD ufs device node and enable the same
> for fsd board. This also adds the required
> pin configuration for the same.
> 
> Cc: linux-fsd@tesla.com
> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  arch/arm64/boot/dts/tesla/fsd-evb.dts      |  4 +++
>  arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 14 +++++++++++
>  arch/arm64/boot/dts/tesla/fsd.dtsi         | 29 ++++++++++++++++++++++
>  3 files changed, 47 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts
> index 5af560c1b5e6..1db6ddf03f01 100644
> --- a/arch/arm64/boot/dts/tesla/fsd-evb.dts
> +++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts
> @@ -37,3 +37,7 @@ &fin_pll {
>  &serial_0 {
>  	status = "okay";
>  };
> +
> +&ufs {
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
> index d4d0cb005712..387a41e251d5 100644
> --- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
> +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
> @@ -50,6 +50,20 @@ gpf5: gpf5-gpio-bank {
>  		interrupt-controller;
>  		#interrupt-cells = <2>;
>  	};
> +
> +	ufs_rst_n: ufs-rst-n-pins {
> +		samsung,pins = "gpf5-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
> +	};
> +
> +	ufs_refclk_out: ufs-refclk-out-pins {
> +		samsung,pins = "gpf5-1";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
> +	};
>  };
>  
>  &pinctrl_peric {
> diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
> index af39655331de..a5972e9a2585 100644
> --- a/arch/arm64/boot/dts/tesla/fsd.dtsi
> +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
> @@ -740,6 +740,35 @@ timer@10040000 {
>  			clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>;
>  			clock-names = "fin_pll", "mct";
>  		};
> +
> +		ufs: ufs@15120000 {
> +			compatible = "tesla,fsd-ufs";
> +			reg = <0x0  0x15120000 0x0 0x200>,  /* 0: HCI standard */

Double space after 0x0

> +				<0x0 0x15121100 0x0 0x200>,  /* 1: Vendor specified */

Please align with opening < in line before.

> +				<0x0 0x15110000 0x0 0x8000>,  /* 2: UNIPRO */
> +				<0x0 0x15130000 0x0 0x100>;  /* 3: UFS protector */
> +			reg-names = "hci", "vs_hci", "unipro", "ufsp";
> +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clock_fsys0 UFS0_TOP0_HCLK_BUS>,
> +				<&clock_fsys0 UFS0_TOP0_CLK_UNIPRO>;

Also align.


Best regards,
Krzysztof

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Re: [PATCH 2/6] phy: samsung-ufs: move cdr offset to drvdata

[Krzysztof Kozlowski]

On 31/05/2022 03:22, Alim Akhtar wrote:
> Move CDR lock offset to drv data so that it can
> be extended for other SoCs which are having CDR
> lock at different register offset.

Line wrapping is too early
https://elixir.bootlin.com/linux/v5.18-rc4/source/Documentation/process/submitting-patches.rst#L586


Best regards,
Krzysztof

Re: [PATCH 2/6] phy: samsung-ufs: move cdr offset to drvdata

[Krzysztof Kozlowski]

On 31/05/2022 03:22, Alim Akhtar wrote:
> Move CDR lock offset to drv data so that it can
> be extended for other SoCs which are having CDR
> lock at different register offset.

Line wrapping is too early
https://elixir.bootlin.com/linux/v5.18-rc4/source/Documentation/process/submitting-patches.rst#L586


Best regards,
Krzysztof

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Re: [PATCH 2/6] phy: samsung-ufs: move cdr offset to drvdata

[Krzysztof Kozlowski]

On 31/05/2022 03:22, Alim Akhtar wrote:
> Move CDR lock offset to drv data so that it can
> be extended for other SoCs which are having CDR
> lock at different register offset.

Line wrapping is too early
https://elixir.bootlin.com/linux/v5.18-rc4/source/Documentation/process/submitting-patches.rst#L586


Best regards,
Krzysztof

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RE: [PATCH 1/6] dt-bindings: phy: Add FSD UFS PHY bindings

[Alim Akhtar]

>-----Original Message-----
>From: Bart Van Assche [mailto:bvanassche@acm.org]
>Sent: Tuesday, May 31, 2022 9:14 AM
>To: Alim Akhtar <alim.akhtar@samsung.com>; linux-arm-
>kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
>scsi@vger.kernel.org; linux-phy@lists.infradead.org
>Cc: devicetree@vger.kernel.org; robh+dt@kernel.org;
>krzysztof.kozlowski+dt@linaro.org; vkoul@kernel.org; avri.altman@wdc.com;
>martin.petersen@oracle.com; chanho61.park@samsung.com;
>pankaj.dubey@samsung.com; linux-fsd@tesla.com; Bharat Uppal
><bharat.uppal@samsung.com>
>Subject: Re: [PATCH 1/6] dt-bindings: phy: Add FSD UFS PHY bindings
>
>On 5/30/22 18:22, Alim Akhtar wrote:
>> Adds tesla,fsd-ufs-phy compatible for Tesla FSD SoC
>
>What does FSD stand for? Please clarify this in the patch description.
>
Thanks Bart for review, I will update the commit message with about FSD SoC.

>Thanks,
>
>Bart.

RE: [PATCH 1/6] dt-bindings: phy: Add FSD UFS PHY bindings

[Alim Akhtar]

>-----Original Message-----
>From: Bart Van Assche [mailto:bvanassche@acm.org]
>Sent: Tuesday, May 31, 2022 9:14 AM
>To: Alim Akhtar <alim.akhtar@samsung.com>; linux-arm-
>kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
>scsi@vger.kernel.org; linux-phy@lists.infradead.org
>Cc: devicetree@vger.kernel.org; robh+dt@kernel.org;
>krzysztof.kozlowski+dt@linaro.org; vkoul@kernel.org; avri.altman@wdc.com;
>martin.petersen@oracle.com; chanho61.park@samsung.com;
>pankaj.dubey@samsung.com; linux-fsd@tesla.com; Bharat Uppal
><bharat.uppal@samsung.com>
>Subject: Re: [PATCH 1/6] dt-bindings: phy: Add FSD UFS PHY bindings
>
>On 5/30/22 18:22, Alim Akhtar wrote:
>> Adds tesla,fsd-ufs-phy compatible for Tesla FSD SoC
>
>What does FSD stand for? Please clarify this in the patch description.
>
Thanks Bart for review, I will update the commit message with about FSD SoC.

>Thanks,
>
>Bart.


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RE: [PATCH 1/6] dt-bindings: phy: Add FSD UFS PHY bindings

[Alim Akhtar]

>-----Original Message-----
>From: Bart Van Assche [mailto:bvanassche@acm.org]
>Sent: Tuesday, May 31, 2022 9:14 AM
>To: Alim Akhtar <alim.akhtar@samsung.com>; linux-arm-
>kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
>scsi@vger.kernel.org; linux-phy@lists.infradead.org
>Cc: devicetree@vger.kernel.org; robh+dt@kernel.org;
>krzysztof.kozlowski+dt@linaro.org; vkoul@kernel.org; avri.altman@wdc.com;
>martin.petersen@oracle.com; chanho61.park@samsung.com;
>pankaj.dubey@samsung.com; linux-fsd@tesla.com; Bharat Uppal
><bharat.uppal@samsung.com>
>Subject: Re: [PATCH 1/6] dt-bindings: phy: Add FSD UFS PHY bindings
>
>On 5/30/22 18:22, Alim Akhtar wrote:
>> Adds tesla,fsd-ufs-phy compatible for Tesla FSD SoC
>
>What does FSD stand for? Please clarify this in the patch description.
>
Thanks Bart for review, I will update the commit message with about FSD SoC.

>Thanks,
>
>Bart.


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RE: [PATCH 3/6] phy: samsung-ufs: add support for FSD ufs phy driver

[Alim Akhtar]

>-----Original Message-----
>From: Bart Van Assche [mailto:bvanassche@acm.org]
>Sent: Tuesday, May 31, 2022 9:18 AM
>To: Alim Akhtar <alim.akhtar@samsung.com>; linux-arm-
>kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
>scsi@vger.kernel.org; linux-phy@lists.infradead.org
>Cc: devicetree@vger.kernel.org; robh+dt@kernel.org;
>krzysztof.kozlowski+dt@linaro.org; vkoul@kernel.org; avri.altman@wdc.com;
>martin.petersen@oracle.com; chanho61.park@samsung.com;
>pankaj.dubey@samsung.com; linux-fsd@tesla.com; Bharat Uppal
><bharat.uppal@samsung.com>
>Subject: Re: [PATCH 3/6] phy: samsung-ufs: add support for FSD ufs phy driver
>
>On 5/30/22 18:22, Alim Akhtar wrote:
>> diff --git a/drivers/phy/samsung/phy-fsd-ufs.c b/drivers/phy/samsung/phy-
>fsd-ufs.c
>> new file mode 100644
>> index 000000000000..a03656006093
>> --- /dev/null
>> +++ b/drivers/phy/samsung/phy-fsd-ufs.c
>> @@ -0,0 +1,63 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * UFS PHY driver data for FSD SoC
>> + *
>> + * Copyright (C) 2022 Samsung Electronics Co., Ltd.
>> + *
>> + */
>> +#ifndef _PHY_FSD_UFS_H_
>> +#define _PHY_FSD_UFS_H_
>
>Please do not use header file guards in a .c file.
Noted.
Thanks for point it out.

>
>Thanks,
>
>Bart.

RE: [PATCH 3/6] phy: samsung-ufs: add support for FSD ufs phy driver

[Alim Akhtar]

>-----Original Message-----
>From: Bart Van Assche [mailto:bvanassche@acm.org]
>Sent: Tuesday, May 31, 2022 9:18 AM
>To: Alim Akhtar <alim.akhtar@samsung.com>; linux-arm-
>kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
>scsi@vger.kernel.org; linux-phy@lists.infradead.org
>Cc: devicetree@vger.kernel.org; robh+dt@kernel.org;
>krzysztof.kozlowski+dt@linaro.org; vkoul@kernel.org; avri.altman@wdc.com;
>martin.petersen@oracle.com; chanho61.park@samsung.com;
>pankaj.dubey@samsung.com; linux-fsd@tesla.com; Bharat Uppal
><bharat.uppal@samsung.com>
>Subject: Re: [PATCH 3/6] phy: samsung-ufs: add support for FSD ufs phy driver
>
>On 5/30/22 18:22, Alim Akhtar wrote:
>> diff --git a/drivers/phy/samsung/phy-fsd-ufs.c b/drivers/phy/samsung/phy-
>fsd-ufs.c
>> new file mode 100644
>> index 000000000000..a03656006093
>> --- /dev/null
>> +++ b/drivers/phy/samsung/phy-fsd-ufs.c
>> @@ -0,0 +1,63 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * UFS PHY driver data for FSD SoC
>> + *
>> + * Copyright (C) 2022 Samsung Electronics Co., Ltd.
>> + *
>> + */
>> +#ifndef _PHY_FSD_UFS_H_
>> +#define _PHY_FSD_UFS_H_
>
>Please do not use header file guards in a .c file.
Noted.
Thanks for point it out.

>
>Thanks,
>
>Bart.


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RE: [PATCH 3/6] phy: samsung-ufs: add support for FSD ufs phy driver

[Alim Akhtar]

>-----Original Message-----
>From: Bart Van Assche [mailto:bvanassche@acm.org]
>Sent: Tuesday, May 31, 2022 9:18 AM
>To: Alim Akhtar <alim.akhtar@samsung.com>; linux-arm-
>kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
>scsi@vger.kernel.org; linux-phy@lists.infradead.org
>Cc: devicetree@vger.kernel.org; robh+dt@kernel.org;
>krzysztof.kozlowski+dt@linaro.org; vkoul@kernel.org; avri.altman@wdc.com;
>martin.petersen@oracle.com; chanho61.park@samsung.com;
>pankaj.dubey@samsung.com; linux-fsd@tesla.com; Bharat Uppal
><bharat.uppal@samsung.com>
>Subject: Re: [PATCH 3/6] phy: samsung-ufs: add support for FSD ufs phy driver
>
>On 5/30/22 18:22, Alim Akhtar wrote:
>> diff --git a/drivers/phy/samsung/phy-fsd-ufs.c b/drivers/phy/samsung/phy-
>fsd-ufs.c
>> new file mode 100644
>> index 000000000000..a03656006093
>> --- /dev/null
>> +++ b/drivers/phy/samsung/phy-fsd-ufs.c
>> @@ -0,0 +1,63 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * UFS PHY driver data for FSD SoC
>> + *
>> + * Copyright (C) 2022 Samsung Electronics Co., Ltd.
>> + *
>> + */
>> +#ifndef _PHY_FSD_UFS_H_
>> +#define _PHY_FSD_UFS_H_
>
>Please do not use header file guards in a .c file.
Noted.
Thanks for point it out.

>
>Thanks,
>
>Bart.


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RE: [PATCH 1/6] dt-bindings: phy: Add FSD UFS PHY bindings

[Alim Akhtar]

>-----Original Message-----
>From: Krzysztof Kozlowski [mailto:krzysztof.kozlowski@linaro.org]
>Sent: Tuesday, May 31, 2022 2:47 PM
>To: Alim Akhtar <alim.akhtar@samsung.com>; linux-arm-
>kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
>scsi@vger.kernel.org; linux-phy@lists.infradead.org
>Cc: devicetree@vger.kernel.org; robh+dt@kernel.org;
>krzysztof.kozlowski+dt@linaro.org; vkoul@kernel.org; avri.altman@wdc.com;
>bvanassche@acm.org; martin.petersen@oracle.com;
>chanho61.park@samsung.com; pankaj.dubey@samsung.com; linux-
>fsd@tesla.com; Bharat Uppal <bharat.uppal@samsung.com>
>Subject: Re: [PATCH 1/6] dt-bindings: phy: Add FSD UFS PHY bindings
>
>On 31/05/2022 03:22, Alim Akhtar wrote:
>> Adds tesla,fsd-ufs-phy compatible for Tesla FSD SoC
>
>s/Adds/Add/
>and a full stop at the end, please.
>
Noted

>Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
Thanks

>Best regards,
>Krzysztof

RE: [PATCH 1/6] dt-bindings: phy: Add FSD UFS PHY bindings

[Alim Akhtar]

>-----Original Message-----
>From: Krzysztof Kozlowski [mailto:krzysztof.kozlowski@linaro.org]
>Sent: Tuesday, May 31, 2022 2:47 PM
>To: Alim Akhtar <alim.akhtar@samsung.com>; linux-arm-
>kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
>scsi@vger.kernel.org; linux-phy@lists.infradead.org
>Cc: devicetree@vger.kernel.org; robh+dt@kernel.org;
>krzysztof.kozlowski+dt@linaro.org; vkoul@kernel.org; avri.altman@wdc.com;
>bvanassche@acm.org; martin.petersen@oracle.com;
>chanho61.park@samsung.com; pankaj.dubey@samsung.com; linux-
>fsd@tesla.com; Bharat Uppal <bharat.uppal@samsung.com>
>Subject: Re: [PATCH 1/6] dt-bindings: phy: Add FSD UFS PHY bindings
>
>On 31/05/2022 03:22, Alim Akhtar wrote:
>> Adds tesla,fsd-ufs-phy compatible for Tesla FSD SoC
>
>s/Adds/Add/
>and a full stop at the end, please.
>
Noted

>Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
Thanks

>Best regards,
>Krzysztof


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RE: [PATCH 1/6] dt-bindings: phy: Add FSD UFS PHY bindings

[Alim Akhtar]

>-----Original Message-----
>From: Krzysztof Kozlowski [mailto:krzysztof.kozlowski@linaro.org]
>Sent: Tuesday, May 31, 2022 2:47 PM
>To: Alim Akhtar <alim.akhtar@samsung.com>; linux-arm-
>kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
>scsi@vger.kernel.org; linux-phy@lists.infradead.org
>Cc: devicetree@vger.kernel.org; robh+dt@kernel.org;
>krzysztof.kozlowski+dt@linaro.org; vkoul@kernel.org; avri.altman@wdc.com;
>bvanassche@acm.org; martin.petersen@oracle.com;
>chanho61.park@samsung.com; pankaj.dubey@samsung.com; linux-
>fsd@tesla.com; Bharat Uppal <bharat.uppal@samsung.com>
>Subject: Re: [PATCH 1/6] dt-bindings: phy: Add FSD UFS PHY bindings
>
>On 31/05/2022 03:22, Alim Akhtar wrote:
>> Adds tesla,fsd-ufs-phy compatible for Tesla FSD SoC
>
>s/Adds/Add/
>and a full stop at the end, please.
>
Noted

>Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
Thanks

>Best regards,
>Krzysztof


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RE: [PATCH 2/6] phy: samsung-ufs: move cdr offset to drvdata

[Alim Akhtar]

>-----Original Message-----
>From: Krzysztof Kozlowski [mailto:krzysztof.kozlowski@linaro.org]
>Sent: Tuesday, May 31, 2022 3:26 PM
>To: Alim Akhtar <alim.akhtar@samsung.com>; linux-arm-
>kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
>scsi@vger.kernel.org; linux-phy@lists.infradead.org
>Cc: devicetree@vger.kernel.org; robh+dt@kernel.org;
>krzysztof.kozlowski+dt@linaro.org; vkoul@kernel.org; avri.altman@wdc.com;
>bvanassche@acm.org; martin.petersen@oracle.com;
>chanho61.park@samsung.com; pankaj.dubey@samsung.com; linux-
>fsd@tesla.com; Bharat Uppal <bharat.uppal@samsung.com>
>Subject: Re: [PATCH 2/6] phy: samsung-ufs: move cdr offset to drvdata
>
>On 31/05/2022 03:22, Alim Akhtar wrote:
>> Move CDR lock offset to drv data so that it can be extended for other
>> SoCs which are having CDR lock at different register offset.
>>
>> Cc: linux-fsd@tesla.com
>> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>> ---
>>  drivers/phy/samsung/phy-exynos7-ufs.c      | 3 +++
>>  drivers/phy/samsung/phy-exynosautov9-ufs.c | 2 ++
>>  drivers/phy/samsung/phy-samsung-ufs.c      | 3 ++-
>>  drivers/phy/samsung/phy-samsung-ufs.h      | 2 +-
>>  4 files changed, 8 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c
>> b/drivers/phy/samsung/phy-exynos7-ufs.c
>> index 7c9008e163db..d1a37273cb1f 100644
>> --- a/drivers/phy/samsung/phy-exynos7-ufs.c
>> +++ b/drivers/phy/samsung/phy-exynos7-ufs.c
>> @@ -11,6 +11,8 @@
>>  #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK	0x1
>>  #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN	BIT(0)
>>
>> +#define PHY_CDR_LOCK_STATUS    0x5e
>
>This should be now renamed to match other defines here, so
>EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS
>
Sure, will update in next version
>
>Best regards,
>Krzysztof

RE: [PATCH 2/6] phy: samsung-ufs: move cdr offset to drvdata

[Alim Akhtar]

>-----Original Message-----
>From: Krzysztof Kozlowski [mailto:krzysztof.kozlowski@linaro.org]
>Sent: Tuesday, May 31, 2022 3:26 PM
>To: Alim Akhtar <alim.akhtar@samsung.com>; linux-arm-
>kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
>scsi@vger.kernel.org; linux-phy@lists.infradead.org
>Cc: devicetree@vger.kernel.org; robh+dt@kernel.org;
>krzysztof.kozlowski+dt@linaro.org; vkoul@kernel.org; avri.altman@wdc.com;
>bvanassche@acm.org; martin.petersen@oracle.com;
>chanho61.park@samsung.com; pankaj.dubey@samsung.com; linux-
>fsd@tesla.com; Bharat Uppal <bharat.uppal@samsung.com>
>Subject: Re: [PATCH 2/6] phy: samsung-ufs: move cdr offset to drvdata
>
>On 31/05/2022 03:22, Alim Akhtar wrote:
>> Move CDR lock offset to drv data so that it can be extended for other
>> SoCs which are having CDR lock at different register offset.
>>
>> Cc: linux-fsd@tesla.com
>> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>> ---
>>  drivers/phy/samsung/phy-exynos7-ufs.c      | 3 +++
>>  drivers/phy/samsung/phy-exynosautov9-ufs.c | 2 ++
>>  drivers/phy/samsung/phy-samsung-ufs.c      | 3 ++-
>>  drivers/phy/samsung/phy-samsung-ufs.h      | 2 +-
>>  4 files changed, 8 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c
>> b/drivers/phy/samsung/phy-exynos7-ufs.c
>> index 7c9008e163db..d1a37273cb1f 100644
>> --- a/drivers/phy/samsung/phy-exynos7-ufs.c
>> +++ b/drivers/phy/samsung/phy-exynos7-ufs.c
>> @@ -11,6 +11,8 @@
>>  #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK	0x1
>>  #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN	BIT(0)
>>
>> +#define PHY_CDR_LOCK_STATUS    0x5e
>
>This should be now renamed to match other defines here, so
>EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS
>
Sure, will update in next version
>
>Best regards,
>Krzysztof


-- 
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

RE: [PATCH 2/6] phy: samsung-ufs: move cdr offset to drvdata

[Alim Akhtar]

>-----Original Message-----
>From: Krzysztof Kozlowski [mailto:krzysztof.kozlowski@linaro.org]
>Sent: Tuesday, May 31, 2022 3:26 PM
>To: Alim Akhtar <alim.akhtar@samsung.com>; linux-arm-
>kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
>scsi@vger.kernel.org; linux-phy@lists.infradead.org
>Cc: devicetree@vger.kernel.org; robh+dt@kernel.org;
>krzysztof.kozlowski+dt@linaro.org; vkoul@kernel.org; avri.altman@wdc.com;
>bvanassche@acm.org; martin.petersen@oracle.com;
>chanho61.park@samsung.com; pankaj.dubey@samsung.com; linux-
>fsd@tesla.com; Bharat Uppal <bharat.uppal@samsung.com>
>Subject: Re: [PATCH 2/6] phy: samsung-ufs: move cdr offset to drvdata
>
>On 31/05/2022 03:22, Alim Akhtar wrote:
>> Move CDR lock offset to drv data so that it can be extended for other
>> SoCs which are having CDR lock at different register offset.
>>
>> Cc: linux-fsd@tesla.com
>> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>> ---
>>  drivers/phy/samsung/phy-exynos7-ufs.c      | 3 +++
>>  drivers/phy/samsung/phy-exynosautov9-ufs.c | 2 ++
>>  drivers/phy/samsung/phy-samsung-ufs.c      | 3 ++-
>>  drivers/phy/samsung/phy-samsung-ufs.h      | 2 +-
>>  4 files changed, 8 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c
>> b/drivers/phy/samsung/phy-exynos7-ufs.c
>> index 7c9008e163db..d1a37273cb1f 100644
>> --- a/drivers/phy/samsung/phy-exynos7-ufs.c
>> +++ b/drivers/phy/samsung/phy-exynos7-ufs.c
>> @@ -11,6 +11,8 @@
>>  #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK	0x1
>>  #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN	BIT(0)
>>
>> +#define PHY_CDR_LOCK_STATUS    0x5e
>
>This should be now renamed to match other defines here, so
>EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS
>
Sure, will update in next version
>
>Best regards,
>Krzysztof


_______________________________________________
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RE: [PATCH 5/6] ufs: host: ufs-exynos: add support for fsd ufs hci

[Alim Akhtar]

Hi Chanho
Thanks for the review.

>-----Original Message-----
>From: Chanho Park [mailto:chanho61.park@samsung.com]
>Sent: Tuesday, May 31, 2022 1:07 PM
>To: 'Alim Akhtar' <alim.akhtar@samsung.com>; linux-arm-
>kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
>scsi@vger.kernel.org; linux-phy@lists.infradead.org
>Cc: devicetree@vger.kernel.org; robh+dt@kernel.org;
>krzysztof.kozlowski+dt@linaro.org; vkoul@kernel.org; avri.altman@wdc.com;
>bvanassche@acm.org; martin.petersen@oracle.com;
>pankaj.dubey@samsung.com; linux-fsd@tesla.com; 'Bharat Uppal'
><bharat.uppal@samsung.com>
>Subject: RE: [PATCH 5/6] ufs: host: ufs-exynos: add support for fsd ufs hci
>
>Hi,
>
>> -----Original Message-----
>> From: Alim Akhtar <alim.akhtar@samsung.com>
>> Sent: Tuesday, May 31, 2022 10:22 AM
>> To: linux-arm-kernel@lists.infradead.org;
>> linux-kernel@vger.kernel.org; linux-scsi@vger.kernel.org;
>> linux-phy@lists.infradead.org
>> Cc: devicetree@vger.kernel.org; robh+dt@kernel.org;
>> krzysztof.kozlowski+dt@linaro.org; vkoul@kernel.org;
>> avri.altman@wdc.com; bvanassche@acm.org;
>martin.petersen@oracle.com;
>> chanho61.park@samsung.com; pankaj.dubey@samsung.com; Alim Akhtar
>> <alim.akhtar@samsung.com>; linux- fsd@tesla.com; Bharat Uppal
>> <bharat.uppal@samsung.com>
>> Subject: [PATCH 5/6] ufs: host: ufs-exynos: add support for fsd ufs
>> hci
>>
>> Adds support of UFS HCI which is found in Tesla FSD SoC. FSD also have
>> an addition bit for MPHY APB clock which was not there (was reserved)
>> for previous exynos SoC.
>>
>> Cc: linux-fsd@tesla.com
>> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>> ---
>>  drivers/ufs/host/ufs-exynos.c | 143
>> +++++++++++++++++++++++++++++++++-
>>  1 file changed, 142 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/ufs/host/ufs-exynos.c
>> b/drivers/ufs/host/ufs-exynos.c index a81d8cbd542f..b3efdc4caca2
>> 100644
>> --- a/drivers/ufs/host/ufs-exynos.c
>> +++ b/drivers/ufs/host/ufs-exynos.c
>> @@ -52,11 +52,12 @@
>>  #define HCI_ERR_EN_DME_LAYER	0x88
>>  #define HCI_CLKSTOP_CTRL	0xB0
>>  #define REFCLKOUT_STOP		BIT(4)
>> +#define MPHY_APBCLK_STOP        BIT(3)
>>  #define REFCLK_STOP		BIT(2)
>>  #define UNIPRO_MCLK_STOP	BIT(1)
>>  #define UNIPRO_PCLK_STOP	BIT(0)
>>  #define CLK_STOP_MASK		(REFCLKOUT_STOP | REFCLK_STOP |\
>> -				 UNIPRO_MCLK_STOP |\
>> +				 UNIPRO_MCLK_STOP |
>MPHY_APBCLK_STOP|\
>
>Please make this change into a separate patch of this series.
>
Sure, will separate it out.

>>  				 UNIPRO_PCLK_STOP)
>>  #define HCI_MISC		0xB4
>>  #define REFCLK_CTRL_EN		BIT(7)
>> @@ -386,6 +387,104 @@ static int exynos7_ufs_post_pwr_change(struct
>> exynos_ufs *ufs,
>>  	return 0;
>>  }
>>
>> +static inline int fsd_ufs_pre_link(struct exynos_ufs *ufs) {
>> +	int i;
>> +	struct ufs_hba *hba = ufs->hba;
>> +
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9514), 1000000000L / ufs-
>> >mclk_rate);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
>> +
>> +	for_each_ufs_tx_lane(ufs, i) {
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i),
>1000000000L /
>> ufs->mclk_rate);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F);
>> +	}
>> +
>> +	for_each_ufs_rx_lane(ufs, i) {
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i),
>1000000000L /
>> ufs->mclk_rate);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0);
>> +	}
>> +
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9536), 0x4E20);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9564), 0x2e820183);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x155E), 0x0);
>
>Use PA_LOCAL_TX_LCC_ENABLE instead of 0x155E. I think you can find more
>values from unipro.h.
>Please try to use as much as possible :)
>
Noted

>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x3000), 0x0);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x3001), 0x1);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x4021), 0x1);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x4020), 0x1);
>
>They can be set from exynos_ufs_establish_connt.
>
Ok, 

>> +
>> +	return 0;
>> +}
>> +
>> +static inline int fsd_ufs_post_link(struct exynos_ufs *ufs) {
>> +	int i;
>> +	struct ufs_hba *hba = ufs->hba;
>> +	u32 hw_cap_min_tactivate;
>> +	u32 peer_rx_min_actv_time_cap;
>> +	u32 max_rx_hibern8_time_cap;
>> +
>> +	ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4),
>> +			&hw_cap_min_tactivate); /* HW Capability of
>> MIN_TACTIVATE */
>> +	ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A8),
>> +			&peer_rx_min_actv_time_cap);    /* PA_TActivate */
>> +	ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A7),
>> +			&max_rx_hibern8_time_cap);      /* PA_Hibern8Time
>*/
>> +
>> +	if (peer_rx_min_actv_time_cap >= hw_cap_min_tactivate)
>> +		ufshcd_dme_peer_set(hba, UIC_ARG_MIB(0x15A8),
>> +					peer_rx_min_actv_time_cap + 1);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A7),
>max_rx_hibern8_time_cap +
>> 1);
>> +
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x01);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A4), 0xFA);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x00);
>> +
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
>> +
>> +	for_each_ufs_rx_lane(ufs, i) {
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC);
>> +	}
>> +
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
>> +
>> +	return 0;
>> +}
>> +
>> +static inline int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs,
>> +					struct ufs_pa_layer_attr *pwr)
>> +{
>> +	struct ufs_hba *hba = ufs->hba;
>> +
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x1569), 0x1);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x1584), 0x1);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2041), 8064);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2042), 28224);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2043), 20160);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B0), 12000);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B1), 32000);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B2), 16000);
>> +
>> +	unipro_writel(ufs, 8064, 0x7888);
>> +	unipro_writel(ufs, 28224, 0x788C);
>> +	unipro_writel(ufs, 20160, 0x7890);
>> +	unipro_writel(ufs, 12000, 0x78B8);
>> +	unipro_writel(ufs, 32000, 0x78BC);
>> +	unipro_writel(ufs, 16000, 0x78C0);
>> +
>> +	return 0;
>> +}
>> +
>>  /*
>>   * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w
>>   * Control should be disabled in the below cases @@ -1595,6 +1694,46
>> @@ static struct exynos_ufs_drv_data exynos_ufs_drvs = {
>>  	.post_pwr_change	= exynos7_ufs_post_pwr_change,
>>  };
>>
>> +static struct exynos_ufs_uic_attr fsd_uic_attr = {
>> +	.tx_trailingclks		= 0x10,
>> +	.tx_dif_p_nsec			= 3000000,	/* unit: ns */
>> +	.tx_dif_n_nsec			= 1000000,	/* unit: ns */
>> +	.tx_high_z_cnt_nsec		= 20000,	/* unit: ns */
>> +	.tx_base_unit_nsec		= 100000,	/* unit: ns */
>> +	.tx_gran_unit_nsec		= 4000,		/* unit: ns */
>> +	.tx_sleep_cnt			= 1000,		/* unit: ns */
>> +	.tx_min_activatetime		= 0xa,
>> +	.rx_filler_enable		= 0x2,
>> +	.rx_dif_p_nsec			= 1000000,	/* unit: ns */
>> +	.rx_hibern8_wait_nsec		= 4000000,	/* unit: ns */
>> +	.rx_base_unit_nsec		= 100000,	/* unit: ns */
>> +	.rx_gran_unit_nsec		= 4000,		/* unit: ns */
>> +	.rx_sleep_cnt			= 1280,		/* unit: ns */
>> +	.rx_stall_cnt			= 320,		/* unit: ns */
>> +	.rx_hs_g1_sync_len_cap		= SYNC_LEN_COARSE(0xf),
>> +	.rx_hs_g2_sync_len_cap		= SYNC_LEN_COARSE(0xf),
>> +	.rx_hs_g3_sync_len_cap		= SYNC_LEN_COARSE(0xf),
>> +	.rx_hs_g1_prep_sync_len_cap	= PREP_LEN(0xf),
>> +	.rx_hs_g2_prep_sync_len_cap	= PREP_LEN(0xf),
>> +	.rx_hs_g3_prep_sync_len_cap	= PREP_LEN(0xf),
>> +	.pa_dbg_option_suite		= 0x2E820183,
>> +};
>> +
>> +struct exynos_ufs_drv_data fsd_ufs_drvs = {
>> +	.uic_attr               = &fsd_uic_attr,
>> +	.quirks                 = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
>> +				  UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
>> +
>UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
>> +				  UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR,
>> +	.opts                   = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
>> +
>EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
>> +				  EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR
>|
>> +				  EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
>> +	.pre_link               = fsd_ufs_pre_link,
>> +	.post_link              = fsd_ufs_post_link,
>> +	.pre_pwr_change         = fsd_ufs_pre_pwr_change,
>> +};
>> +
>>  static const struct of_device_id exynos_ufs_of_match[] = {
>>  	{ .compatible = "samsung,exynos7-ufs",
>>  	  .data	      = &exynos_ufs_drvs },
>> @@ -1602,6 +1741,8 @@ static const struct of_device_id
>> exynos_ufs_of_match[] = {
>>  	  .data	      = &exynosauto_ufs_drvs },
>>  	{ .compatible = "samsung,exynosautov9-ufs-vh",
>>  	  .data	      = &exynosauto_ufs_vh_drvs },
>> +	{ .compatible = "tesla,fsd-ufs",
>> +	  .data       = &fsd_ufs_drvs },
>>  	{},
>>  };
>>
>> --
>> 2.25.1
>

RE: [PATCH 5/6] ufs: host: ufs-exynos: add support for fsd ufs hci

[Alim Akhtar]

Hi Chanho
Thanks for the review.

>-----Original Message-----
>From: Chanho Park [mailto:chanho61.park@samsung.com]
>Sent: Tuesday, May 31, 2022 1:07 PM
>To: 'Alim Akhtar' <alim.akhtar@samsung.com>; linux-arm-
>kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
>scsi@vger.kernel.org; linux-phy@lists.infradead.org
>Cc: devicetree@vger.kernel.org; robh+dt@kernel.org;
>krzysztof.kozlowski+dt@linaro.org; vkoul@kernel.org; avri.altman@wdc.com;
>bvanassche@acm.org; martin.petersen@oracle.com;
>pankaj.dubey@samsung.com; linux-fsd@tesla.com; 'Bharat Uppal'
><bharat.uppal@samsung.com>
>Subject: RE: [PATCH 5/6] ufs: host: ufs-exynos: add support for fsd ufs hci
>
>Hi,
>
>> -----Original Message-----
>> From: Alim Akhtar <alim.akhtar@samsung.com>
>> Sent: Tuesday, May 31, 2022 10:22 AM
>> To: linux-arm-kernel@lists.infradead.org;
>> linux-kernel@vger.kernel.org; linux-scsi@vger.kernel.org;
>> linux-phy@lists.infradead.org
>> Cc: devicetree@vger.kernel.org; robh+dt@kernel.org;
>> krzysztof.kozlowski+dt@linaro.org; vkoul@kernel.org;
>> avri.altman@wdc.com; bvanassche@acm.org;
>martin.petersen@oracle.com;
>> chanho61.park@samsung.com; pankaj.dubey@samsung.com; Alim Akhtar
>> <alim.akhtar@samsung.com>; linux- fsd@tesla.com; Bharat Uppal
>> <bharat.uppal@samsung.com>
>> Subject: [PATCH 5/6] ufs: host: ufs-exynos: add support for fsd ufs
>> hci
>>
>> Adds support of UFS HCI which is found in Tesla FSD SoC. FSD also have
>> an addition bit for MPHY APB clock which was not there (was reserved)
>> for previous exynos SoC.
>>
>> Cc: linux-fsd@tesla.com
>> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>> ---
>>  drivers/ufs/host/ufs-exynos.c | 143
>> +++++++++++++++++++++++++++++++++-
>>  1 file changed, 142 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/ufs/host/ufs-exynos.c
>> b/drivers/ufs/host/ufs-exynos.c index a81d8cbd542f..b3efdc4caca2
>> 100644
>> --- a/drivers/ufs/host/ufs-exynos.c
>> +++ b/drivers/ufs/host/ufs-exynos.c
>> @@ -52,11 +52,12 @@
>>  #define HCI_ERR_EN_DME_LAYER	0x88
>>  #define HCI_CLKSTOP_CTRL	0xB0
>>  #define REFCLKOUT_STOP		BIT(4)
>> +#define MPHY_APBCLK_STOP        BIT(3)
>>  #define REFCLK_STOP		BIT(2)
>>  #define UNIPRO_MCLK_STOP	BIT(1)
>>  #define UNIPRO_PCLK_STOP	BIT(0)
>>  #define CLK_STOP_MASK		(REFCLKOUT_STOP | REFCLK_STOP |\
>> -				 UNIPRO_MCLK_STOP |\
>> +				 UNIPRO_MCLK_STOP |
>MPHY_APBCLK_STOP|\
>
>Please make this change into a separate patch of this series.
>
Sure, will separate it out.

>>  				 UNIPRO_PCLK_STOP)
>>  #define HCI_MISC		0xB4
>>  #define REFCLK_CTRL_EN		BIT(7)
>> @@ -386,6 +387,104 @@ static int exynos7_ufs_post_pwr_change(struct
>> exynos_ufs *ufs,
>>  	return 0;
>>  }
>>
>> +static inline int fsd_ufs_pre_link(struct exynos_ufs *ufs) {
>> +	int i;
>> +	struct ufs_hba *hba = ufs->hba;
>> +
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9514), 1000000000L / ufs-
>> >mclk_rate);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
>> +
>> +	for_each_ufs_tx_lane(ufs, i) {
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i),
>1000000000L /
>> ufs->mclk_rate);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F);
>> +	}
>> +
>> +	for_each_ufs_rx_lane(ufs, i) {
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i),
>1000000000L /
>> ufs->mclk_rate);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0);
>> +	}
>> +
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9536), 0x4E20);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9564), 0x2e820183);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x155E), 0x0);
>
>Use PA_LOCAL_TX_LCC_ENABLE instead of 0x155E. I think you can find more
>values from unipro.h.
>Please try to use as much as possible :)
>
Noted

>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x3000), 0x0);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x3001), 0x1);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x4021), 0x1);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x4020), 0x1);
>
>They can be set from exynos_ufs_establish_connt.
>
Ok, 

>> +
>> +	return 0;
>> +}
>> +
>> +static inline int fsd_ufs_post_link(struct exynos_ufs *ufs) {
>> +	int i;
>> +	struct ufs_hba *hba = ufs->hba;
>> +	u32 hw_cap_min_tactivate;
>> +	u32 peer_rx_min_actv_time_cap;
>> +	u32 max_rx_hibern8_time_cap;
>> +
>> +	ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4),
>> +			&hw_cap_min_tactivate); /* HW Capability of
>> MIN_TACTIVATE */
>> +	ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A8),
>> +			&peer_rx_min_actv_time_cap);    /* PA_TActivate */
>> +	ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A7),
>> +			&max_rx_hibern8_time_cap);      /* PA_Hibern8Time
>*/
>> +
>> +	if (peer_rx_min_actv_time_cap >= hw_cap_min_tactivate)
>> +		ufshcd_dme_peer_set(hba, UIC_ARG_MIB(0x15A8),
>> +					peer_rx_min_actv_time_cap + 1);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A7),
>max_rx_hibern8_time_cap +
>> 1);
>> +
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x01);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A4), 0xFA);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x00);
>> +
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
>> +
>> +	for_each_ufs_rx_lane(ufs, i) {
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC);
>> +	}
>> +
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
>> +
>> +	return 0;
>> +}
>> +
>> +static inline int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs,
>> +					struct ufs_pa_layer_attr *pwr)
>> +{
>> +	struct ufs_hba *hba = ufs->hba;
>> +
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x1569), 0x1);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x1584), 0x1);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2041), 8064);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2042), 28224);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2043), 20160);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B0), 12000);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B1), 32000);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B2), 16000);
>> +
>> +	unipro_writel(ufs, 8064, 0x7888);
>> +	unipro_writel(ufs, 28224, 0x788C);
>> +	unipro_writel(ufs, 20160, 0x7890);
>> +	unipro_writel(ufs, 12000, 0x78B8);
>> +	unipro_writel(ufs, 32000, 0x78BC);
>> +	unipro_writel(ufs, 16000, 0x78C0);
>> +
>> +	return 0;
>> +}
>> +
>>  /*
>>   * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w
>>   * Control should be disabled in the below cases @@ -1595,6 +1694,46
>> @@ static struct exynos_ufs_drv_data exynos_ufs_drvs = {
>>  	.post_pwr_change	= exynos7_ufs_post_pwr_change,
>>  };
>>
>> +static struct exynos_ufs_uic_attr fsd_uic_attr = {
>> +	.tx_trailingclks		= 0x10,
>> +	.tx_dif_p_nsec			= 3000000,	/* unit: ns */
>> +	.tx_dif_n_nsec			= 1000000,	/* unit: ns */
>> +	.tx_high_z_cnt_nsec		= 20000,	/* unit: ns */
>> +	.tx_base_unit_nsec		= 100000,	/* unit: ns */
>> +	.tx_gran_unit_nsec		= 4000,		/* unit: ns */
>> +	.tx_sleep_cnt			= 1000,		/* unit: ns */
>> +	.tx_min_activatetime		= 0xa,
>> +	.rx_filler_enable		= 0x2,
>> +	.rx_dif_p_nsec			= 1000000,	/* unit: ns */
>> +	.rx_hibern8_wait_nsec		= 4000000,	/* unit: ns */
>> +	.rx_base_unit_nsec		= 100000,	/* unit: ns */
>> +	.rx_gran_unit_nsec		= 4000,		/* unit: ns */
>> +	.rx_sleep_cnt			= 1280,		/* unit: ns */
>> +	.rx_stall_cnt			= 320,		/* unit: ns */
>> +	.rx_hs_g1_sync_len_cap		= SYNC_LEN_COARSE(0xf),
>> +	.rx_hs_g2_sync_len_cap		= SYNC_LEN_COARSE(0xf),
>> +	.rx_hs_g3_sync_len_cap		= SYNC_LEN_COARSE(0xf),
>> +	.rx_hs_g1_prep_sync_len_cap	= PREP_LEN(0xf),
>> +	.rx_hs_g2_prep_sync_len_cap	= PREP_LEN(0xf),
>> +	.rx_hs_g3_prep_sync_len_cap	= PREP_LEN(0xf),
>> +	.pa_dbg_option_suite		= 0x2E820183,
>> +};
>> +
>> +struct exynos_ufs_drv_data fsd_ufs_drvs = {
>> +	.uic_attr               = &fsd_uic_attr,
>> +	.quirks                 = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
>> +				  UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
>> +
>UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
>> +				  UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR,
>> +	.opts                   = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
>> +
>EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
>> +				  EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR
>|
>> +				  EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
>> +	.pre_link               = fsd_ufs_pre_link,
>> +	.post_link              = fsd_ufs_post_link,
>> +	.pre_pwr_change         = fsd_ufs_pre_pwr_change,
>> +};
>> +
>>  static const struct of_device_id exynos_ufs_of_match[] = {
>>  	{ .compatible = "samsung,exynos7-ufs",
>>  	  .data	      = &exynos_ufs_drvs },
>> @@ -1602,6 +1741,8 @@ static const struct of_device_id
>> exynos_ufs_of_match[] = {
>>  	  .data	      = &exynosauto_ufs_drvs },
>>  	{ .compatible = "samsung,exynosautov9-ufs-vh",
>>  	  .data	      = &exynosauto_ufs_vh_drvs },
>> +	{ .compatible = "tesla,fsd-ufs",
>> +	  .data       = &fsd_ufs_drvs },
>>  	{},
>>  };
>>
>> --
>> 2.25.1
>



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RE: [PATCH 5/6] ufs: host: ufs-exynos: add support for fsd ufs hci

[Alim Akhtar]

Hi Chanho
Thanks for the review.

>-----Original Message-----
>From: Chanho Park [mailto:chanho61.park@samsung.com]
>Sent: Tuesday, May 31, 2022 1:07 PM
>To: 'Alim Akhtar' <alim.akhtar@samsung.com>; linux-arm-
>kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
>scsi@vger.kernel.org; linux-phy@lists.infradead.org
>Cc: devicetree@vger.kernel.org; robh+dt@kernel.org;
>krzysztof.kozlowski+dt@linaro.org; vkoul@kernel.org; avri.altman@wdc.com;
>bvanassche@acm.org; martin.petersen@oracle.com;
>pankaj.dubey@samsung.com; linux-fsd@tesla.com; 'Bharat Uppal'
><bharat.uppal@samsung.com>
>Subject: RE: [PATCH 5/6] ufs: host: ufs-exynos: add support for fsd ufs hci
>
>Hi,
>
>> -----Original Message-----
>> From: Alim Akhtar <alim.akhtar@samsung.com>
>> Sent: Tuesday, May 31, 2022 10:22 AM
>> To: linux-arm-kernel@lists.infradead.org;
>> linux-kernel@vger.kernel.org; linux-scsi@vger.kernel.org;
>> linux-phy@lists.infradead.org
>> Cc: devicetree@vger.kernel.org; robh+dt@kernel.org;
>> krzysztof.kozlowski+dt@linaro.org; vkoul@kernel.org;
>> avri.altman@wdc.com; bvanassche@acm.org;
>martin.petersen@oracle.com;
>> chanho61.park@samsung.com; pankaj.dubey@samsung.com; Alim Akhtar
>> <alim.akhtar@samsung.com>; linux- fsd@tesla.com; Bharat Uppal
>> <bharat.uppal@samsung.com>
>> Subject: [PATCH 5/6] ufs: host: ufs-exynos: add support for fsd ufs
>> hci
>>
>> Adds support of UFS HCI which is found in Tesla FSD SoC. FSD also have
>> an addition bit for MPHY APB clock which was not there (was reserved)
>> for previous exynos SoC.
>>
>> Cc: linux-fsd@tesla.com
>> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>> ---
>>  drivers/ufs/host/ufs-exynos.c | 143
>> +++++++++++++++++++++++++++++++++-
>>  1 file changed, 142 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/ufs/host/ufs-exynos.c
>> b/drivers/ufs/host/ufs-exynos.c index a81d8cbd542f..b3efdc4caca2
>> 100644
>> --- a/drivers/ufs/host/ufs-exynos.c
>> +++ b/drivers/ufs/host/ufs-exynos.c
>> @@ -52,11 +52,12 @@
>>  #define HCI_ERR_EN_DME_LAYER	0x88
>>  #define HCI_CLKSTOP_CTRL	0xB0
>>  #define REFCLKOUT_STOP		BIT(4)
>> +#define MPHY_APBCLK_STOP        BIT(3)
>>  #define REFCLK_STOP		BIT(2)
>>  #define UNIPRO_MCLK_STOP	BIT(1)
>>  #define UNIPRO_PCLK_STOP	BIT(0)
>>  #define CLK_STOP_MASK		(REFCLKOUT_STOP | REFCLK_STOP |\
>> -				 UNIPRO_MCLK_STOP |\
>> +				 UNIPRO_MCLK_STOP |
>MPHY_APBCLK_STOP|\
>
>Please make this change into a separate patch of this series.
>
Sure, will separate it out.

>>  				 UNIPRO_PCLK_STOP)
>>  #define HCI_MISC		0xB4
>>  #define REFCLK_CTRL_EN		BIT(7)
>> @@ -386,6 +387,104 @@ static int exynos7_ufs_post_pwr_change(struct
>> exynos_ufs *ufs,
>>  	return 0;
>>  }
>>
>> +static inline int fsd_ufs_pre_link(struct exynos_ufs *ufs) {
>> +	int i;
>> +	struct ufs_hba *hba = ufs->hba;
>> +
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9514), 1000000000L / ufs-
>> >mclk_rate);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
>> +
>> +	for_each_ufs_tx_lane(ufs, i) {
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i),
>1000000000L /
>> ufs->mclk_rate);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F);
>> +	}
>> +
>> +	for_each_ufs_rx_lane(ufs, i) {
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i),
>1000000000L /
>> ufs->mclk_rate);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0);
>> +	}
>> +
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9536), 0x4E20);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9564), 0x2e820183);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x155E), 0x0);
>
>Use PA_LOCAL_TX_LCC_ENABLE instead of 0x155E. I think you can find more
>values from unipro.h.
>Please try to use as much as possible :)
>
Noted

>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x3000), 0x0);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x3001), 0x1);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x4021), 0x1);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x4020), 0x1);
>
>They can be set from exynos_ufs_establish_connt.
>
Ok, 

>> +
>> +	return 0;
>> +}
>> +
>> +static inline int fsd_ufs_post_link(struct exynos_ufs *ufs) {
>> +	int i;
>> +	struct ufs_hba *hba = ufs->hba;
>> +	u32 hw_cap_min_tactivate;
>> +	u32 peer_rx_min_actv_time_cap;
>> +	u32 max_rx_hibern8_time_cap;
>> +
>> +	ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4),
>> +			&hw_cap_min_tactivate); /* HW Capability of
>> MIN_TACTIVATE */
>> +	ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A8),
>> +			&peer_rx_min_actv_time_cap);    /* PA_TActivate */
>> +	ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A7),
>> +			&max_rx_hibern8_time_cap);      /* PA_Hibern8Time
>*/
>> +
>> +	if (peer_rx_min_actv_time_cap >= hw_cap_min_tactivate)
>> +		ufshcd_dme_peer_set(hba, UIC_ARG_MIB(0x15A8),
>> +					peer_rx_min_actv_time_cap + 1);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A7),
>max_rx_hibern8_time_cap +
>> 1);
>> +
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x01);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A4), 0xFA);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x00);
>> +
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
>> +
>> +	for_each_ufs_rx_lane(ufs, i) {
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02);
>> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC);
>> +	}
>> +
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
>> +
>> +	return 0;
>> +}
>> +
>> +static inline int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs,
>> +					struct ufs_pa_layer_attr *pwr)
>> +{
>> +	struct ufs_hba *hba = ufs->hba;
>> +
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x1569), 0x1);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x1584), 0x1);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2041), 8064);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2042), 28224);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2043), 20160);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B0), 12000);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B1), 32000);
>> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B2), 16000);
>> +
>> +	unipro_writel(ufs, 8064, 0x7888);
>> +	unipro_writel(ufs, 28224, 0x788C);
>> +	unipro_writel(ufs, 20160, 0x7890);
>> +	unipro_writel(ufs, 12000, 0x78B8);
>> +	unipro_writel(ufs, 32000, 0x78BC);
>> +	unipro_writel(ufs, 16000, 0x78C0);
>> +
>> +	return 0;
>> +}
>> +
>>  /*
>>   * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w
>>   * Control should be disabled in the below cases @@ -1595,6 +1694,46
>> @@ static struct exynos_ufs_drv_data exynos_ufs_drvs = {
>>  	.post_pwr_change	= exynos7_ufs_post_pwr_change,
>>  };
>>
>> +static struct exynos_ufs_uic_attr fsd_uic_attr = {
>> +	.tx_trailingclks		= 0x10,
>> +	.tx_dif_p_nsec			= 3000000,	/* unit: ns */
>> +	.tx_dif_n_nsec			= 1000000,	/* unit: ns */
>> +	.tx_high_z_cnt_nsec		= 20000,	/* unit: ns */
>> +	.tx_base_unit_nsec		= 100000,	/* unit: ns */
>> +	.tx_gran_unit_nsec		= 4000,		/* unit: ns */
>> +	.tx_sleep_cnt			= 1000,		/* unit: ns */
>> +	.tx_min_activatetime		= 0xa,
>> +	.rx_filler_enable		= 0x2,
>> +	.rx_dif_p_nsec			= 1000000,	/* unit: ns */
>> +	.rx_hibern8_wait_nsec		= 4000000,	/* unit: ns */
>> +	.rx_base_unit_nsec		= 100000,	/* unit: ns */
>> +	.rx_gran_unit_nsec		= 4000,		/* unit: ns */
>> +	.rx_sleep_cnt			= 1280,		/* unit: ns */
>> +	.rx_stall_cnt			= 320,		/* unit: ns */
>> +	.rx_hs_g1_sync_len_cap		= SYNC_LEN_COARSE(0xf),
>> +	.rx_hs_g2_sync_len_cap		= SYNC_LEN_COARSE(0xf),
>> +	.rx_hs_g3_sync_len_cap		= SYNC_LEN_COARSE(0xf),
>> +	.rx_hs_g1_prep_sync_len_cap	= PREP_LEN(0xf),
>> +	.rx_hs_g2_prep_sync_len_cap	= PREP_LEN(0xf),
>> +	.rx_hs_g3_prep_sync_len_cap	= PREP_LEN(0xf),
>> +	.pa_dbg_option_suite		= 0x2E820183,
>> +};
>> +
>> +struct exynos_ufs_drv_data fsd_ufs_drvs = {
>> +	.uic_attr               = &fsd_uic_attr,
>> +	.quirks                 = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
>> +				  UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
>> +
>UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
>> +				  UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR,
>> +	.opts                   = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
>> +
>EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
>> +				  EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR
>|
>> +				  EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
>> +	.pre_link               = fsd_ufs_pre_link,
>> +	.post_link              = fsd_ufs_post_link,
>> +	.pre_pwr_change         = fsd_ufs_pre_pwr_change,
>> +};
>> +
>>  static const struct of_device_id exynos_ufs_of_match[] = {
>>  	{ .compatible = "samsung,exynos7-ufs",
>>  	  .data	      = &exynos_ufs_drvs },
>> @@ -1602,6 +1741,8 @@ static const struct of_device_id
>> exynos_ufs_of_match[] = {
>>  	  .data	      = &exynosauto_ufs_drvs },
>>  	{ .compatible = "samsung,exynosautov9-ufs-vh",
>>  	  .data	      = &exynosauto_ufs_vh_drvs },
>> +	{ .compatible = "tesla,fsd-ufs",
>> +	  .data       = &fsd_ufs_drvs },
>>  	{},
>>  };
>>
>> --
>> 2.25.1
>



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