* [PATCH] phy: samsung: exynosautov9-ufs: correct TSRV register configurations
[not found] <CGME20220531082658epcas2p1a6f22a304ce8031c39c97daa90372715@epcas2p1.samsung.com>
@ 2022-05-31 8:26 ` Chanho Park
0 siblings, 0 replies; 8+ messages in thread
From: Chanho Park @ 2022-05-31 8:26 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Krzysztof Kozlowski, Alim Akhtar
Cc: linux-phy, linux-arm-kernel, Chanho Park
For exynos auto v9's UFS MPHY, We should use 0x50 offset of TSRV register
configurations. So, it must be
s/PHY_TRSV_REG_CFG/PHY_TRSV_REG_CFG/g
Fixes: d64519249e1d ("phy: samsung-ufs: support exynosauto ufs phy driver")
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
drivers/phy/samsung/phy-exynosautov9-ufs.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/samsung/phy-exynosautov9-ufs.c b/drivers/phy/samsung/phy-exynosautov9-ufs.c
index 36398a15c2db..d043dfdb598a 100644
--- a/drivers/phy/samsung/phy-exynosautov9-ufs.c
+++ b/drivers/phy/samsung/phy-exynosautov9-ufs.c
@@ -31,22 +31,22 @@ static const struct samsung_ufs_phy_cfg exynosautov9_pre_init_cfg[] = {
PHY_COMN_REG_CFG(0x023, 0xc0, PWR_MODE_ANY),
PHY_COMN_REG_CFG(0x023, 0x00, PWR_MODE_ANY),
- PHY_TRSV_REG_CFG(0x042, 0x5d, PWR_MODE_ANY),
- PHY_TRSV_REG_CFG(0x043, 0x80, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_AUTOV9(0x042, 0x5d, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_AUTOV9(0x043, 0x80, PWR_MODE_ANY),
END_UFS_PHY_CFG,
};
/* Calibration for HS mode series A/B */
static const struct samsung_ufs_phy_cfg exynosautov9_pre_pwr_hs_cfg[] = {
- PHY_TRSV_REG_CFG(0x032, 0xbc, PWR_MODE_HS_ANY),
- PHY_TRSV_REG_CFG(0x03c, 0x7f, PWR_MODE_HS_ANY),
- PHY_TRSV_REG_CFG(0x048, 0xc0, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG_AUTOV9(0x032, 0xbc, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG_AUTOV9(0x03c, 0x7f, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG_AUTOV9(0x048, 0xc0, PWR_MODE_HS_ANY),
- PHY_TRSV_REG_CFG(0x04a, 0x00, PWR_MODE_HS_G3_SER_B),
- PHY_TRSV_REG_CFG(0x04b, 0x10, PWR_MODE_HS_G1_SER_B |
- PWR_MODE_HS_G3_SER_B),
- PHY_TRSV_REG_CFG(0x04d, 0x63, PWR_MODE_HS_G3_SER_B),
+ PHY_TRSV_REG_CFG_AUTOV9(0x04a, 0x00, PWR_MODE_HS_G3_SER_B),
+ PHY_TRSV_REG_CFG_AUTOV9(0x04b, 0x10, PWR_MODE_HS_G1_SER_B |
+ PWR_MODE_HS_G3_SER_B),
+ PHY_TRSV_REG_CFG_AUTOV9(0x04d, 0x63, PWR_MODE_HS_G3_SER_B),
END_UFS_PHY_CFG,
};
--
2.36.1
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH] phy: samsung: exynosautov9-ufs: correct TSRV register configurations
@ 2022-05-31 8:26 ` Chanho Park
0 siblings, 0 replies; 8+ messages in thread
From: Chanho Park @ 2022-05-31 8:26 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Krzysztof Kozlowski, Alim Akhtar
Cc: linux-phy, linux-arm-kernel, Chanho Park
For exynos auto v9's UFS MPHY, We should use 0x50 offset of TSRV register
configurations. So, it must be
s/PHY_TRSV_REG_CFG/PHY_TRSV_REG_CFG/g
Fixes: d64519249e1d ("phy: samsung-ufs: support exynosauto ufs phy driver")
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
drivers/phy/samsung/phy-exynosautov9-ufs.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/samsung/phy-exynosautov9-ufs.c b/drivers/phy/samsung/phy-exynosautov9-ufs.c
index 36398a15c2db..d043dfdb598a 100644
--- a/drivers/phy/samsung/phy-exynosautov9-ufs.c
+++ b/drivers/phy/samsung/phy-exynosautov9-ufs.c
@@ -31,22 +31,22 @@ static const struct samsung_ufs_phy_cfg exynosautov9_pre_init_cfg[] = {
PHY_COMN_REG_CFG(0x023, 0xc0, PWR_MODE_ANY),
PHY_COMN_REG_CFG(0x023, 0x00, PWR_MODE_ANY),
- PHY_TRSV_REG_CFG(0x042, 0x5d, PWR_MODE_ANY),
- PHY_TRSV_REG_CFG(0x043, 0x80, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_AUTOV9(0x042, 0x5d, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_AUTOV9(0x043, 0x80, PWR_MODE_ANY),
END_UFS_PHY_CFG,
};
/* Calibration for HS mode series A/B */
static const struct samsung_ufs_phy_cfg exynosautov9_pre_pwr_hs_cfg[] = {
- PHY_TRSV_REG_CFG(0x032, 0xbc, PWR_MODE_HS_ANY),
- PHY_TRSV_REG_CFG(0x03c, 0x7f, PWR_MODE_HS_ANY),
- PHY_TRSV_REG_CFG(0x048, 0xc0, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG_AUTOV9(0x032, 0xbc, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG_AUTOV9(0x03c, 0x7f, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG_AUTOV9(0x048, 0xc0, PWR_MODE_HS_ANY),
- PHY_TRSV_REG_CFG(0x04a, 0x00, PWR_MODE_HS_G3_SER_B),
- PHY_TRSV_REG_CFG(0x04b, 0x10, PWR_MODE_HS_G1_SER_B |
- PWR_MODE_HS_G3_SER_B),
- PHY_TRSV_REG_CFG(0x04d, 0x63, PWR_MODE_HS_G3_SER_B),
+ PHY_TRSV_REG_CFG_AUTOV9(0x04a, 0x00, PWR_MODE_HS_G3_SER_B),
+ PHY_TRSV_REG_CFG_AUTOV9(0x04b, 0x10, PWR_MODE_HS_G1_SER_B |
+ PWR_MODE_HS_G3_SER_B),
+ PHY_TRSV_REG_CFG_AUTOV9(0x04d, 0x63, PWR_MODE_HS_G3_SER_B),
END_UFS_PHY_CFG,
};
--
2.36.1
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] phy: samsung: exynosautov9-ufs: correct TSRV register configurations
2022-05-31 8:26 ` Chanho Park
@ 2022-05-31 9:07 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-31 9:07 UTC (permalink / raw)
To: Chanho Park, Kishon Vijay Abraham I, Vinod Koul, Alim Akhtar
Cc: linux-phy, linux-arm-kernel
On 31/05/2022 10:26, Chanho Park wrote:
> For exynos auto v9's UFS MPHY, We should use 0x50 offset of TSRV register
> configurations. So, it must be
>
> s/PHY_TRSV_REG_CFG/PHY_TRSV_REG_CFG/g
>
> Fixes: d64519249e1d ("phy: samsung-ufs: support exynosauto ufs phy driver")
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
--
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] phy: samsung: exynosautov9-ufs: correct TSRV register configurations
@ 2022-05-31 9:07 ` Krzysztof Kozlowski
0 siblings, 0 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-31 9:07 UTC (permalink / raw)
To: Chanho Park, Kishon Vijay Abraham I, Vinod Koul, Alim Akhtar
Cc: linux-phy, linux-arm-kernel
On 31/05/2022 10:26, Chanho Park wrote:
> For exynos auto v9's UFS MPHY, We should use 0x50 offset of TSRV register
> configurations. So, it must be
>
> s/PHY_TRSV_REG_CFG/PHY_TRSV_REG_CFG/g
>
> Fixes: d64519249e1d ("phy: samsung-ufs: support exynosauto ufs phy driver")
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH] phy: samsung: exynosautov9-ufs: correct TSRV register configurations
2022-05-31 8:26 ` Chanho Park
@ 2022-06-03 1:27 ` Alim Akhtar
-1 siblings, 0 replies; 8+ messages in thread
From: Alim Akhtar @ 2022-06-03 1:27 UTC (permalink / raw)
To: 'Chanho Park', 'Kishon Vijay Abraham I',
'Vinod Koul', 'Krzysztof Kozlowski'
Cc: linux-phy, linux-arm-kernel
>-----Original Message-----
>From: Chanho Park [mailto:chanho61.park@samsung.com]
>Sent: Tuesday, May 31, 2022 1:57 PM
>To: Kishon Vijay Abraham I <kishon@ti.com>; Vinod Koul
><vkoul@kernel.org>; Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>;
>Alim Akhtar <alim.akhtar@samsung.com>
>Cc: linux-phy@lists.infradead.org; linux-arm-kernel@lists.infradead.org;
>Chanho Park <chanho61.park@samsung.com>
>Subject: [PATCH] phy: samsung: exynosautov9-ufs: correct TSRV register
>configurations
>
>For exynos auto v9's UFS MPHY, We should use 0x50 offset of TSRV register
>configurations. So, it must be
>
>s/PHY_TRSV_REG_CFG/PHY_TRSV_REG_CFG/g
>
You mean
s/PHY_TRSV_REG_CFG/PHY_TRSV_REG_CFG_AUTOV9/g
>Fixes: d64519249e1d ("phy: samsung-ufs: support exynosauto ufs phy driver")
>Signed-off-by: Chanho Park <chanho61.park@samsung.com>
>---
> drivers/phy/samsung/phy-exynosautov9-ufs.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
>diff --git a/drivers/phy/samsung/phy-exynosautov9-ufs.c
>b/drivers/phy/samsung/phy-exynosautov9-ufs.c
>index 36398a15c2db..d043dfdb598a 100644
>--- a/drivers/phy/samsung/phy-exynosautov9-ufs.c
>+++ b/drivers/phy/samsung/phy-exynosautov9-ufs.c
>@@ -31,22 +31,22 @@ static const struct samsung_ufs_phy_cfg
>exynosautov9_pre_init_cfg[] = {
> PHY_COMN_REG_CFG(0x023, 0xc0, PWR_MODE_ANY),
> PHY_COMN_REG_CFG(0x023, 0x00, PWR_MODE_ANY),
>
>- PHY_TRSV_REG_CFG(0x042, 0x5d, PWR_MODE_ANY),
>- PHY_TRSV_REG_CFG(0x043, 0x80, PWR_MODE_ANY),
>+ PHY_TRSV_REG_CFG_AUTOV9(0x042, 0x5d, PWR_MODE_ANY),
>+ PHY_TRSV_REG_CFG_AUTOV9(0x043, 0x80, PWR_MODE_ANY),
>
> END_UFS_PHY_CFG,
> };
>
> /* Calibration for HS mode series A/B */ static const struct
>samsung_ufs_phy_cfg exynosautov9_pre_pwr_hs_cfg[] = {
>- PHY_TRSV_REG_CFG(0x032, 0xbc, PWR_MODE_HS_ANY),
>- PHY_TRSV_REG_CFG(0x03c, 0x7f, PWR_MODE_HS_ANY),
>- PHY_TRSV_REG_CFG(0x048, 0xc0, PWR_MODE_HS_ANY),
>+ PHY_TRSV_REG_CFG_AUTOV9(0x032, 0xbc, PWR_MODE_HS_ANY),
>+ PHY_TRSV_REG_CFG_AUTOV9(0x03c, 0x7f, PWR_MODE_HS_ANY),
>+ PHY_TRSV_REG_CFG_AUTOV9(0x048, 0xc0, PWR_MODE_HS_ANY),
>
>- PHY_TRSV_REG_CFG(0x04a, 0x00, PWR_MODE_HS_G3_SER_B),
>- PHY_TRSV_REG_CFG(0x04b, 0x10, PWR_MODE_HS_G1_SER_B |
>- PWR_MODE_HS_G3_SER_B),
>- PHY_TRSV_REG_CFG(0x04d, 0x63, PWR_MODE_HS_G3_SER_B),
>+ PHY_TRSV_REG_CFG_AUTOV9(0x04a, 0x00,
>PWR_MODE_HS_G3_SER_B),
>+ PHY_TRSV_REG_CFG_AUTOV9(0x04b, 0x10,
>PWR_MODE_HS_G1_SER_B |
>+ PWR_MODE_HS_G3_SER_B),
>+ PHY_TRSV_REG_CFG_AUTOV9(0x04d, 0x63,
>PWR_MODE_HS_G3_SER_B),
>
> END_UFS_PHY_CFG,
> };
>--
>2.36.1
--
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^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH] phy: samsung: exynosautov9-ufs: correct TSRV register configurations
@ 2022-06-03 1:27 ` Alim Akhtar
0 siblings, 0 replies; 8+ messages in thread
From: Alim Akhtar @ 2022-06-03 1:27 UTC (permalink / raw)
To: 'Chanho Park', 'Kishon Vijay Abraham I',
'Vinod Koul', 'Krzysztof Kozlowski'
Cc: linux-phy, linux-arm-kernel
>-----Original Message-----
>From: Chanho Park [mailto:chanho61.park@samsung.com]
>Sent: Tuesday, May 31, 2022 1:57 PM
>To: Kishon Vijay Abraham I <kishon@ti.com>; Vinod Koul
><vkoul@kernel.org>; Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>;
>Alim Akhtar <alim.akhtar@samsung.com>
>Cc: linux-phy@lists.infradead.org; linux-arm-kernel@lists.infradead.org;
>Chanho Park <chanho61.park@samsung.com>
>Subject: [PATCH] phy: samsung: exynosautov9-ufs: correct TSRV register
>configurations
>
>For exynos auto v9's UFS MPHY, We should use 0x50 offset of TSRV register
>configurations. So, it must be
>
>s/PHY_TRSV_REG_CFG/PHY_TRSV_REG_CFG/g
>
You mean
s/PHY_TRSV_REG_CFG/PHY_TRSV_REG_CFG_AUTOV9/g
>Fixes: d64519249e1d ("phy: samsung-ufs: support exynosauto ufs phy driver")
>Signed-off-by: Chanho Park <chanho61.park@samsung.com>
>---
> drivers/phy/samsung/phy-exynosautov9-ufs.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
>diff --git a/drivers/phy/samsung/phy-exynosautov9-ufs.c
>b/drivers/phy/samsung/phy-exynosautov9-ufs.c
>index 36398a15c2db..d043dfdb598a 100644
>--- a/drivers/phy/samsung/phy-exynosautov9-ufs.c
>+++ b/drivers/phy/samsung/phy-exynosautov9-ufs.c
>@@ -31,22 +31,22 @@ static const struct samsung_ufs_phy_cfg
>exynosautov9_pre_init_cfg[] = {
> PHY_COMN_REG_CFG(0x023, 0xc0, PWR_MODE_ANY),
> PHY_COMN_REG_CFG(0x023, 0x00, PWR_MODE_ANY),
>
>- PHY_TRSV_REG_CFG(0x042, 0x5d, PWR_MODE_ANY),
>- PHY_TRSV_REG_CFG(0x043, 0x80, PWR_MODE_ANY),
>+ PHY_TRSV_REG_CFG_AUTOV9(0x042, 0x5d, PWR_MODE_ANY),
>+ PHY_TRSV_REG_CFG_AUTOV9(0x043, 0x80, PWR_MODE_ANY),
>
> END_UFS_PHY_CFG,
> };
>
> /* Calibration for HS mode series A/B */ static const struct
>samsung_ufs_phy_cfg exynosautov9_pre_pwr_hs_cfg[] = {
>- PHY_TRSV_REG_CFG(0x032, 0xbc, PWR_MODE_HS_ANY),
>- PHY_TRSV_REG_CFG(0x03c, 0x7f, PWR_MODE_HS_ANY),
>- PHY_TRSV_REG_CFG(0x048, 0xc0, PWR_MODE_HS_ANY),
>+ PHY_TRSV_REG_CFG_AUTOV9(0x032, 0xbc, PWR_MODE_HS_ANY),
>+ PHY_TRSV_REG_CFG_AUTOV9(0x03c, 0x7f, PWR_MODE_HS_ANY),
>+ PHY_TRSV_REG_CFG_AUTOV9(0x048, 0xc0, PWR_MODE_HS_ANY),
>
>- PHY_TRSV_REG_CFG(0x04a, 0x00, PWR_MODE_HS_G3_SER_B),
>- PHY_TRSV_REG_CFG(0x04b, 0x10, PWR_MODE_HS_G1_SER_B |
>- PWR_MODE_HS_G3_SER_B),
>- PHY_TRSV_REG_CFG(0x04d, 0x63, PWR_MODE_HS_G3_SER_B),
>+ PHY_TRSV_REG_CFG_AUTOV9(0x04a, 0x00,
>PWR_MODE_HS_G3_SER_B),
>+ PHY_TRSV_REG_CFG_AUTOV9(0x04b, 0x10,
>PWR_MODE_HS_G1_SER_B |
>+ PWR_MODE_HS_G3_SER_B),
>+ PHY_TRSV_REG_CFG_AUTOV9(0x04d, 0x63,
>PWR_MODE_HS_G3_SER_B),
>
> END_UFS_PHY_CFG,
> };
>--
>2.36.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH] phy: samsung: exynosautov9-ufs: correct TSRV register configurations
2022-06-03 1:27 ` Alim Akhtar
@ 2022-06-03 4:56 ` Chanho Park
-1 siblings, 0 replies; 8+ messages in thread
From: Chanho Park @ 2022-06-03 4:56 UTC (permalink / raw)
To: 'Alim Akhtar', 'Kishon Vijay Abraham I',
'Vinod Koul', 'Krzysztof Kozlowski'
Cc: linux-phy, linux-arm-kernel
> >s/PHY_TRSV_REG_CFG/PHY_TRSV_REG_CFG/g
> >
>
>
> You mean
>
> s/PHY_TRSV_REG_CFG/PHY_TRSV_REG_CFG_AUTOV9/g
You're right. This needs to be modified...
Best Regards,
Chanho Park
--
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^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH] phy: samsung: exynosautov9-ufs: correct TSRV register configurations
@ 2022-06-03 4:56 ` Chanho Park
0 siblings, 0 replies; 8+ messages in thread
From: Chanho Park @ 2022-06-03 4:56 UTC (permalink / raw)
To: 'Alim Akhtar', 'Kishon Vijay Abraham I',
'Vinod Koul', 'Krzysztof Kozlowski'
Cc: linux-phy, linux-arm-kernel
> >s/PHY_TRSV_REG_CFG/PHY_TRSV_REG_CFG/g
> >
>
>
> You mean
>
> s/PHY_TRSV_REG_CFG/PHY_TRSV_REG_CFG_AUTOV9/g
You're right. This needs to be modified...
Best Regards,
Chanho Park
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-06-03 4:58 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <CGME20220531082658epcas2p1a6f22a304ce8031c39c97daa90372715@epcas2p1.samsung.com>
2022-05-31 8:26 ` [PATCH] phy: samsung: exynosautov9-ufs: correct TSRV register configurations Chanho Park
2022-05-31 8:26 ` Chanho Park
2022-05-31 9:07 ` Krzysztof Kozlowski
2022-05-31 9:07 ` Krzysztof Kozlowski
2022-06-03 1:27 ` Alim Akhtar
2022-06-03 1:27 ` Alim Akhtar
2022-06-03 4:56 ` Chanho Park
2022-06-03 4:56 ` Chanho Park
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