* [PATCH] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not
@ 2017-07-13 10:35 ` Jisheng Zhang
0 siblings, 0 replies; 9+ messages in thread
From: Jisheng Zhang @ 2017-07-13 10:35 UTC (permalink / raw)
To: jingoohan1, Joao.Pinto, bhelgaas
Cc: linux-pci, linux-kernel, linux-arm-kernel, Jisheng Zhang
The ATU CTRL2 register is 32 bit, besides the enable bit, other bits
may also be set. To check whether the ATU is enabled or not, we should
test the enable it.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
drivers/pci/dwc/pcie-designware.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index 0e03af279259..6bf0b409050a 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
*/
for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
- if (val == PCIE_ATU_ENABLE)
+ if (val & PCIE_ATU_ENABLE)
return;
usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
--
2.13.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not
@ 2017-07-13 10:35 ` Jisheng Zhang
0 siblings, 0 replies; 9+ messages in thread
From: Jisheng Zhang @ 2017-07-13 10:35 UTC (permalink / raw)
To: jingoohan1, Joao.Pinto, bhelgaas
Cc: Jisheng Zhang, linux-pci, linux-kernel, linux-arm-kernel
The ATU CTRL2 register is 32 bit, besides the enable bit, other bits
may also be set. To check whether the ATU is enabled or not, we should
test the enable it.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
drivers/pci/dwc/pcie-designware.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index 0e03af279259..6bf0b409050a 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
*/
for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
- if (val == PCIE_ATU_ENABLE)
+ if (val & PCIE_ATU_ENABLE)
return;
usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
--
2.13.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not
@ 2017-07-13 10:35 ` Jisheng Zhang
0 siblings, 0 replies; 9+ messages in thread
From: Jisheng Zhang @ 2017-07-13 10:35 UTC (permalink / raw)
To: linux-arm-kernel
The ATU CTRL2 register is 32 bit, besides the enable bit, other bits
may also be set. To check whether the ATU is enabled or not, we should
test the enable it.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
drivers/pci/dwc/pcie-designware.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index 0e03af279259..6bf0b409050a 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
*/
for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
- if (val == PCIE_ATU_ENABLE)
+ if (val & PCIE_ATU_ENABLE)
return;
usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
--
2.13.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not
2017-07-13 10:35 ` Jisheng Zhang
(?)
@ 2017-07-17 9:27 ` Joao Pinto
-1 siblings, 0 replies; 9+ messages in thread
From: Joao Pinto @ 2017-07-17 9:27 UTC (permalink / raw)
To: Jisheng Zhang, jingoohan1, Joao.Pinto, bhelgaas
Cc: linux-pci, linux-kernel, linux-arm-kernel
Hi,
Às 11:35 AM de 7/13/2017, Jisheng Zhang escreveu:
> The ATU CTRL2 register is 32 bit, besides the enable bit, other bits
> may also be set. To check whether the ATU is enabled or not, we should
> test the enable it.
>
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> ---
> drivers/pci/dwc/pcie-designware.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
> index 0e03af279259..6bf0b409050a 100644
> --- a/drivers/pci/dwc/pcie-designware.c
> +++ b/drivers/pci/dwc/pcie-designware.c
> @@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> */
> for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
> val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
> - if (val == PCIE_ATU_ENABLE)
> + if (val & PCIE_ATU_ENABLE)
> return;
>
> usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
>
Make sense, turn it more accurate. Thanks!
Acked-by: Joao Pinto <jpinto@synopsys.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not
@ 2017-07-17 9:27 ` Joao Pinto
0 siblings, 0 replies; 9+ messages in thread
From: Joao Pinto @ 2017-07-17 9:27 UTC (permalink / raw)
To: Jisheng Zhang, jingoohan1, Joao.Pinto, bhelgaas
Cc: linux-pci, linux-kernel, linux-arm-kernel
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not
@ 2017-07-17 9:27 ` Joao Pinto
0 siblings, 0 replies; 9+ messages in thread
From: Joao Pinto @ 2017-07-17 9:27 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
?s 11:35 AM de 7/13/2017, Jisheng Zhang escreveu:
> The ATU CTRL2 register is 32 bit, besides the enable bit, other bits
> may also be set. To check whether the ATU is enabled or not, we should
> test the enable it.
>
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> ---
> drivers/pci/dwc/pcie-designware.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
> index 0e03af279259..6bf0b409050a 100644
> --- a/drivers/pci/dwc/pcie-designware.c
> +++ b/drivers/pci/dwc/pcie-designware.c
> @@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> */
> for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
> val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
> - if (val == PCIE_ATU_ENABLE)
> + if (val & PCIE_ATU_ENABLE)
> return;
>
> usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
>
Make sense, turn it more accurate. Thanks!
Acked-by: Joao Pinto <jpinto@synopsys.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not
2017-07-17 9:27 ` Joao Pinto
(?)
@ 2017-07-17 19:32 ` Jingoo Han
-1 siblings, 0 replies; 9+ messages in thread
From: Jingoo Han @ 2017-07-17 19:32 UTC (permalink / raw)
To: 'Joao Pinto', 'Jisheng Zhang', bhelgaas
Cc: linux-pci, linux-kernel, linux-arm-kernel
On Monday, July 17, 2017 5:28 AM, Joao Pinto wrote:
>
> Hi,
>
> Às 11:35 AM de 7/13/2017, Jisheng Zhang escreveu:
> > The ATU CTRL2 register is 32 bit, besides the enable bit, other bits
> > may also be set. To check whether the ATU is enabled or not, we should
> > test the enable it.
To Jisheng Zhang,
typo s/it/bit
"test the enable it." ---> "test the enable bit."
Please fix this typo, and send it again.
Type is confusing.
Best regards,
Jingoo Han
> >
> > Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> > ---
> > drivers/pci/dwc/pcie-designware.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-
> designware.c
> > index 0e03af279259..6bf0b409050a 100644
> > --- a/drivers/pci/dwc/pcie-designware.c
> > +++ b/drivers/pci/dwc/pcie-designware.c
> > @@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> int index, int type,
> > */
> > for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++)
> {
> > val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
> > - if (val == PCIE_ATU_ENABLE)
> > + if (val & PCIE_ATU_ENABLE)
> > return;
> >
> > usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
> >
> Make sense, turn it more accurate. Thanks!
>
> Acked-by: Joao Pinto <jpinto@synopsys.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not
@ 2017-07-17 19:32 ` Jingoo Han
0 siblings, 0 replies; 9+ messages in thread
From: Jingoo Han @ 2017-07-17 19:32 UTC (permalink / raw)
To: 'Joao Pinto', 'Jisheng Zhang', bhelgaas
Cc: linux-pci, linux-kernel, linux-arm-kernel
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not
@ 2017-07-17 19:32 ` Jingoo Han
0 siblings, 0 replies; 9+ messages in thread
From: Jingoo Han @ 2017-07-17 19:32 UTC (permalink / raw)
To: linux-arm-kernel
On Monday, July 17, 2017 5:28 AM, Joao Pinto wrote:
>
> Hi,
>
> ?s 11:35 AM de 7/13/2017, Jisheng Zhang escreveu:
> > The ATU CTRL2 register is 32 bit, besides the enable bit, other bits
> > may also be set. To check whether the ATU is enabled or not, we should
> > test the enable it.
To Jisheng Zhang,
typo s/it/bit
"test the enable it." ---> "test the enable bit."
Please fix this typo, and send it again.
Type is confusing.
Best regards,
Jingoo Han
> >
> > Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> > ---
> > drivers/pci/dwc/pcie-designware.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-
> designware.c
> > index 0e03af279259..6bf0b409050a 100644
> > --- a/drivers/pci/dwc/pcie-designware.c
> > +++ b/drivers/pci/dwc/pcie-designware.c
> > @@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> int index, int type,
> > */
> > for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++)
> {
> > val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
> > - if (val == PCIE_ATU_ENABLE)
> > + if (val & PCIE_ATU_ENABLE)
> > return;
> >
> > usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
> >
> Make sense, turn it more accurate. Thanks!
>
> Acked-by: Joao Pinto <jpinto@synopsys.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2017-07-17 19:32 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-07-13 10:35 [PATCH] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not Jisheng Zhang
2017-07-13 10:35 ` Jisheng Zhang
2017-07-13 10:35 ` Jisheng Zhang
2017-07-17 9:27 ` Joao Pinto
2017-07-17 9:27 ` Joao Pinto
2017-07-17 9:27 ` Joao Pinto
2017-07-17 19:32 ` Jingoo Han
2017-07-17 19:32 ` Jingoo Han
2017-07-17 19:32 ` Jingoo Han
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