From: Richard Henderson <rth@twiddle.net>
To: Michael Rolnik <mrolnik@gmail.com>,
Richard Henderson <richard.henderson@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH RFC v20 4/8] target-avr: Add instruction decoding
Date: Mon, 3 Jun 2019 16:48:34 -0500 [thread overview]
Message-ID: <0034b373-5c4d-ddf8-f4ae-33fab6a695f6@twiddle.net> (raw)
In-Reply-To: <CAK4993i6gM4v_dmOUbhHZOpDxXxKTueqRd-6COVk+z5U7VXK6w@mail.gmail.com>
On 6/3/19 3:13 PM, Michael Rolnik wrote:
> Richard,
> I don't understand what I should do. Do you want me to merge decode files?
Yes, using the mechanisms previously described.
r~
>
> On Fri, May 31, 2019 at 5:45 PM Richard Henderson <richard.henderson@linaro.org
> <mailto:richard.henderson@linaro.org>> wrote:
>
> On 5/30/19 2:07 PM, Michael Rolnik wrote:
> > This includes:
> > - encoding of all 16 bit instructions
> > - encoding of all 32 bit instructions
> >
> > Signed-off-by: Michael Rolnik <mrolnik@gmail.com <mailto:mrolnik@gmail.com>>
> > ---
> > target/avr/insn16.decode | 160 +++++++++++++++++++++++++++++++++++++++
> > target/avr/insn32.decode | 10 +++
> > 2 files changed, 170 insertions(+)
> > create mode 100644 target/avr/insn16.decode
> > create mode 100644 target/avr/insn32.decode
>
> Two things:
>
> (1) decodetree can handle variable-width ISA now.
>
> It's slightly ugly in that the %field numbering is little-endian and thus
> varies for each insn size. But the in-flight patch set for target/rx shows
> that it works.
>
> That said, I don't think you need that because,
>
> (2) The four instructions that are 32-bits do not have
> any opcode bits in the second 16-bits.
>
> E.g.
>
> # The 22-bit immediate is partially in the opcode word,
> # and partially in the next. Use append_16 to build the
> # complete 22-bit value.
> %imm_call 4:5 0:1 !function=append_16
> CALL 1001 010. .... 111. imm=%imm_call
> JMP 1001 010. .... 110. imm=%imm_call
>
> # The 16-bit immediate is completely in the next word.
> # Fields cannot be defined with no bits, so we cannot play
> # the same trick and append to a zero-bit value.
> # Defer reading the immediate until trans_{LDS,STS}.
> @ldst_s .... ... rd:5 .... imm=0
> LDS 1001 000 ..... 0000 @ldst_s
> STS 1001 001 ..... 0000 @ldst_s
>
>
> static uint16_t next_word(DisasContext *ctx)
> {
> return cpu_lduw_code(ctx->env, ctx->npc++ * 2);
> }
>
> static int append_16(DisasContext *ctx, int x)
> {
> return x << 16 | next_word(ctx);
> }
>
> static bool trans_LDS(DisasContext *ctx, arg_ldst_s *a)
> {
> a->imm = next_word(ctx);
> // other stuff
> }
>
> I realize that next_word as written does not fit in to how you currently
> process instructions in the loop, but I also think that's a mistake. I'll
> respond to that in its place in the next patch.
>
> That said, next_word *could* be written to use ctx->inst[0].opcode.
>
>
> r~
>
>
>
> --
> Best Regards,
> Michael Rolnik
next prev parent reply other threads:[~2019-06-03 21:50 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-30 19:07 [Qemu-devel] [PATCH RFC v20 0/8] QEMU AVR 8 bit cores Michael Rolnik
2019-05-30 19:07 ` [Qemu-devel] [PATCH RFC v20 1/8] target/avr: Add outward facing interfaces and core CPU logic Michael Rolnik
2019-05-31 8:02 ` Igor Mammedov
2019-05-31 8:15 ` Michael Rolnik
2019-05-31 9:56 ` Igor Mammedov
2019-05-30 19:07 ` [Qemu-devel] [PATCH RFC v20 2/8] target/avr: Add instruction helpers Michael Rolnik
2019-05-31 13:50 ` Richard Henderson
2019-05-30 19:07 ` [Qemu-devel] [PATCH RFC v20 3/8] target/avr: Add mechanism to check for active debugger connection Michael Rolnik
2019-05-31 13:54 ` Richard Henderson
2019-06-01 21:12 ` Michael Rolnik
2019-06-03 15:44 ` Richard Henderson
2019-06-03 16:29 ` Michael Rolnik
2019-06-03 16:36 ` Richard Henderson
2019-06-03 17:04 ` Michael Rolnik
2019-06-05 7:20 ` Michael Rolnik
2019-06-05 14:36 ` Richard Henderson
2019-06-05 15:19 ` Michael Rolnik
2019-06-05 16:06 ` Richard Henderson
2019-06-05 16:10 ` Alex Bennée
2019-06-05 17:57 ` Michael Rolnik
2019-05-30 19:07 ` [Qemu-devel] [PATCH RFC v20 4/8] target-avr: Add instruction decoding Michael Rolnik
2019-05-31 14:45 ` Richard Henderson
2019-06-03 20:13 ` Michael Rolnik
2019-06-03 21:48 ` Richard Henderson [this message]
2019-05-30 19:07 ` [Qemu-devel] [PATCH RFC v20 5/8] target/avr: Add instruction translation Michael Rolnik
2019-05-31 15:31 ` Richard Henderson
2019-06-02 3:44 ` Michael Rolnik
2019-06-03 15:31 ` Richard Henderson
2019-06-03 15:34 ` Michael Rolnik
2019-05-30 19:07 ` [Qemu-devel] [PATCH RFC v20 6/8] target/avr: Add limited support for USART and 16 bit timer peripherals Michael Rolnik
2019-05-30 19:07 ` [Qemu-devel] [PATCH RFC v20 7/8] target/avr: Add example board configuration Michael Rolnik
2019-05-31 8:06 ` Igor Mammedov
2019-05-30 19:07 ` [Qemu-devel] [PATCH RFC v20 8/8] target/avr: Register AVR support with the rest of QEMU, the build system, and the MAINTAINERS file Michael Rolnik
2019-05-31 14:50 ` Eric Blake
2019-06-01 21:20 ` Michael Rolnik
2019-06-03 19:47 ` Eric Blake
2019-06-03 19:53 ` Michael Rolnik
2019-05-30 20:16 ` [Qemu-devel] [PATCH RFC v20 0/8] QEMU AVR 8 bit cores no-reply
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