[PATCH 0/5] ARM: Add SPDIF support for EXYNOS4

[PATCH 0/5] ARM: Add SPDIF support for EXYNOS4

[Naveen Krishna Chatradhi]

EXYNOS4 supports S/PDIF transmitter simillar to the one in S5PV210.

This patchset adds the clock support, fixes improper gpio configs
and enables the device for SMDKV310.

 o To Kukjin Kim, Sangbeom Kim and Seungwhan Youn,
[PATCH 1/5] ARM: EXYNOS4: Add EPLL clock operations
[PATCH 2/5] ARM: EXYNOS4: Add sclk_spdif clocks
[PATCH 3/5] ARM: EXYNOS4: fix improper gpio configuration
[PATCH 4/5] ARM: EXYNOS4: Add SPDIF for SMDKV310

 o To Seungwhan Youn, Jassi Brar, Mark Brown and Liam Girdwood,
[PATCH 5/5] ASoC: SMDKV310: Enable SPDIF device

Best Regards,
Naveen Krishna Chatradhi

[PATCH 0/5] ARM: Add SPDIF support for EXYNOS4

[Naveen Krishna Chatradhi]

EXYNOS4 supports S/PDIF transmitter simillar to the one in S5PV210.

This patchset adds the clock support, fixes improper gpio configs
and enables the device for SMDKV310.

 o To Kukjin Kim, Sangbeom Kim and Seungwhan Youn,
[PATCH 1/5] ARM: EXYNOS4: Add EPLL clock operations
[PATCH 2/5] ARM: EXYNOS4: Add sclk_spdif clocks
[PATCH 3/5] ARM: EXYNOS4: fix improper gpio configuration
[PATCH 4/5] ARM: EXYNOS4: Add SPDIF for SMDKV310

 o To Seungwhan Youn, Jassi Brar, Mark Brown and Liam Girdwood,
[PATCH 5/5] ASoC: SMDKV310: Enable SPDIF device

Best Regards,
Naveen Krishna Chatradhi

[PATCH 1/5] ARM: EXYNOS4: Add EPLL clock operations

[Naveen Krishna Chatradhi]

This patch adds EPLL specific clock get_rate/set_rate
operations on EXYNOS4.

Note: Initial code from S5PV210
http://permalink.gmane.org/gmane.linux.alsa.devel/77519

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
 arch/arm/mach-exynos4/clock.c |   78 +++++++++++++++++++++++++++++++++++++++++
 1 files changed, 78 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index b1b93b9..7aa4aef 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -1276,6 +1276,82 @@ static struct clksrc_clk *sysclks[] = {
 	&clk_sclk_audio2,
 };
 
+static u32 epll_div[][6] = {
+	{  48000000, 0, 48, 3, 3, 0 },
+	{  96000000, 0, 48, 3, 2, 0 },
+	{ 144000000, 1, 72, 3, 2, 0 },
+	{ 192000000, 0, 48, 3, 1, 0 },
+	{ 288000000, 1, 72, 3, 1, 0 },
+	{  32750000, 1, 65, 3, 4, 35127 },
+	{  32768000, 1, 65, 3, 4, 35127 },
+	{  45158400, 0, 45, 3, 3, 10355 },
+	{  45000000, 0, 45, 3, 3, 10355 },
+	{  45158000, 0, 45, 3, 3, 10355 },
+	{  49125000, 0, 49, 3, 3, 9961 },
+	{  49152000, 0, 49, 3, 3, 9961 },
+	{  67737600, 1, 67, 3, 3, 48366 },
+	{  67738000, 1, 67, 3, 3, 48366 },
+	{  73800000, 1, 73, 3, 3, 47710 },
+	{  73728000, 1, 73, 3, 3, 47710 },
+	{  36000000, 1, 32, 3, 4, 0 },
+	{  60000000, 1, 60, 3, 3, 0 },
+	{  72000000, 1, 72, 3, 3, 0 },
+	{  80000000, 1, 80, 3, 3, 0 },
+	{  84000000, 0, 42, 3, 2, 0 },
+	{  50000000, 0, 50, 3, 3, 0 },
+};
+
+static int exynos4_epll_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned int epll_con, epll_con_k;
+	unsigned int i;
+
+	/* Return if nothing changed */
+	if (clk->rate == rate)
+		return 0;
+
+	epll_con = __raw_readl(S5P_EPLL_CON);
+	epll_con_k = __raw_readl(S5P_EPLL_CON1);
+
+	epll_con_k &= ~PLL46XX_KDIV_MASK;
+	epll_con &= ~(1 << 27 |
+			PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
+			PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
+			PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+
+	for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
+		if (epll_div[i][0] == rate) {
+			epll_con_k |= epll_div[i][5] << 0;
+			epll_con |= (epll_div[i][1] << 27 |
+					epll_div[i][2] << PLL46XX_MDIV_SHIFT |
+					epll_div[i][3] << PLL46XX_PDIV_SHIFT |
+					epll_div[i][4] << PLL46XX_SDIV_SHIFT);
+			break;
+		}
+	}
+
+	if (i == ARRAY_SIZE(epll_div)) {
+		printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
+				__func__);
+		return -EINVAL;
+	}
+
+	__raw_writel(epll_con, S5P_EPLL_CON);
+	__raw_writel(epll_con_k, S5P_EPLL_CON1);
+
+	printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
+			clk->rate, rate);
+
+	clk->rate = rate;
+
+	return 0;
+}
+
+static struct clk_ops exynos4_epll_ops = {
+	.set_rate = exynos4_epll_set_rate,
+	.get_rate = s5p_epll_get_rate,
+};
+
 static int xtal_rate;
 
 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
@@ -1354,6 +1430,8 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
 	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 		s3c_set_clksrc(&clksrcs[ptr], true);
 
+	clk_fout_epll.ops = &exynos4_epll_ops;
+
 	clk_audiocdclk0.rate = PCM_EXTCLK0;
 	clk_set_parent(&clk_sclk_audio0.clk, &clk_audiocdclk0);
 }
-- 
1.7.2.3

[PATCH 1/5] ARM: EXYNOS4: Add EPLL clock operations

[Naveen Krishna Chatradhi]

This patch adds EPLL specific clock get_rate/set_rate
operations on EXYNOS4.

Note: Initial code from S5PV210
http://permalink.gmane.org/gmane.linux.alsa.devel/77519

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
 arch/arm/mach-exynos4/clock.c |   78 +++++++++++++++++++++++++++++++++++++++++
 1 files changed, 78 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index b1b93b9..7aa4aef 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -1276,6 +1276,82 @@ static struct clksrc_clk *sysclks[] = {
 	&clk_sclk_audio2,
 };
 
+static u32 epll_div[][6] = {
+	{  48000000, 0, 48, 3, 3, 0 },
+	{  96000000, 0, 48, 3, 2, 0 },
+	{ 144000000, 1, 72, 3, 2, 0 },
+	{ 192000000, 0, 48, 3, 1, 0 },
+	{ 288000000, 1, 72, 3, 1, 0 },
+	{  32750000, 1, 65, 3, 4, 35127 },
+	{  32768000, 1, 65, 3, 4, 35127 },
+	{  45158400, 0, 45, 3, 3, 10355 },
+	{  45000000, 0, 45, 3, 3, 10355 },
+	{  45158000, 0, 45, 3, 3, 10355 },
+	{  49125000, 0, 49, 3, 3, 9961 },
+	{  49152000, 0, 49, 3, 3, 9961 },
+	{  67737600, 1, 67, 3, 3, 48366 },
+	{  67738000, 1, 67, 3, 3, 48366 },
+	{  73800000, 1, 73, 3, 3, 47710 },
+	{  73728000, 1, 73, 3, 3, 47710 },
+	{  36000000, 1, 32, 3, 4, 0 },
+	{  60000000, 1, 60, 3, 3, 0 },
+	{  72000000, 1, 72, 3, 3, 0 },
+	{  80000000, 1, 80, 3, 3, 0 },
+	{  84000000, 0, 42, 3, 2, 0 },
+	{  50000000, 0, 50, 3, 3, 0 },
+};
+
+static int exynos4_epll_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned int epll_con, epll_con_k;
+	unsigned int i;
+
+	/* Return if nothing changed */
+	if (clk->rate == rate)
+		return 0;
+
+	epll_con = __raw_readl(S5P_EPLL_CON);
+	epll_con_k = __raw_readl(S5P_EPLL_CON1);
+
+	epll_con_k &= ~PLL46XX_KDIV_MASK;
+	epll_con &= ~(1 << 27 |
+			PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
+			PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
+			PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+
+	for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
+		if (epll_div[i][0] == rate) {
+			epll_con_k |= epll_div[i][5] << 0;
+			epll_con |= (epll_div[i][1] << 27 |
+					epll_div[i][2] << PLL46XX_MDIV_SHIFT |
+					epll_div[i][3] << PLL46XX_PDIV_SHIFT |
+					epll_div[i][4] << PLL46XX_SDIV_SHIFT);
+			break;
+		}
+	}
+
+	if (i == ARRAY_SIZE(epll_div)) {
+		printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
+				__func__);
+		return -EINVAL;
+	}
+
+	__raw_writel(epll_con, S5P_EPLL_CON);
+	__raw_writel(epll_con_k, S5P_EPLL_CON1);
+
+	printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
+			clk->rate, rate);
+
+	clk->rate = rate;
+
+	return 0;
+}
+
+static struct clk_ops exynos4_epll_ops = {
+	.set_rate = exynos4_epll_set_rate,
+	.get_rate = s5p_epll_get_rate,
+};
+
 static int xtal_rate;
 
 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
@@ -1354,6 +1430,8 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
 	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 		s3c_set_clksrc(&clksrcs[ptr], true);
 
+	clk_fout_epll.ops = &exynos4_epll_ops;
+
 	clk_audiocdclk0.rate = PCM_EXTCLK0;
 	clk_set_parent(&clk_sclk_audio0.clk, &clk_audiocdclk0);
 }
-- 
1.7.2.3

[PATCH 2/5] ARM: EXYNOS4: Add sclk_spdif clocks

[Naveen Krishna Chatradhi]

Add the sclk_spdif clock is of type 'struct clksrc_clk' clock.
Also, add clk_spdifcdclk clocks of type 'struct clk' clock.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
 arch/arm/mach-exynos4/clock.c |   70 +++++++++++++++++++++++++++++++++++++++++
 1 files changed, 70 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 7aa4aef..57ca356 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -73,6 +73,11 @@ static struct clk clk_audiocdclk2 = {
 	.id		= 2,
 };
 
+static struct clk clk_spdifcdclk = {
+	.name		= "spdifcdclk",
+	.id		= -1,
+};
+
 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
 {
 	return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
@@ -592,6 +597,11 @@ static struct clk init_clocks_off[] = {
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 21),
 	}, {
+		.name		= "spdif",
+		.id		= -1,
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 26),
+	}, {
 		.name		= "ac97",
 		.id		= -1,
 		.enable		= exynos4_clk_ip_peril_ctrl,
@@ -858,6 +868,65 @@ static struct clk init_clocks[] = {
 	}
 };
 
+static int exynos4_spdif_set_rate(struct clk *clk, unsigned long rate)
+{
+	struct clk *pclk;
+	int ret;
+
+	pclk = clk_get_parent(clk);
+	if (IS_ERR(pclk))
+		return -EINVAL;
+
+	ret = pclk->ops->set_rate(pclk, rate);
+	clk_put(pclk);
+
+	return ret;
+}
+
+static unsigned long exynos4_spdif_get_rate(struct clk *clk)
+{
+	struct clk *pclk;
+	int rate;
+
+	pclk = clk_get_parent(clk);
+	if (IS_ERR(pclk))
+		return -EINVAL;
+
+	rate = pclk->ops->get_rate(clk);
+	clk_put(pclk);
+
+	return rate;
+}
+
+static struct clk_ops exynos4_sclk_spdif_ops = {
+	.set_rate	= exynos4_spdif_set_rate,
+	.get_rate	= exynos4_spdif_get_rate,
+};
+
+static struct clk *clkset_sclk_spdif_list[] = {
+	[0] = &clk_sclk_audio0.clk,
+	[1] = &clk_sclk_audio1.clk,
+	[2] = &clk_sclk_audio2.clk,
+	[3] = &clk_spdifcdclk,
+};
+
+static struct clksrc_sources clkset_sclk_spdif = {
+	.sources	= clkset_sclk_spdif_list,
+	.nr_sources	= ARRAY_SIZE(clkset_sclk_spdif_list),
+};
+
+static struct clksrc_clk clk_sclk_spdif = {
+	.clk	= {
+		.name		= "sclk_spdif",
+		.id		= -1,
+		.enable		= exynos4_clksrc_mask_peril1_ctrl,
+		.ctrlbit	= (1 << 8),
+		.ops		= &exynos4_sclk_spdif_ops,
+	},
+		.sources = &clkset_sclk_spdif,
+		.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 8, .size = 2 },
+};
+
 static struct clk *clkset_group_list[] = {
 	[0] = &clk_ext_xtal_mux,
 	[1] = &clk_xusbxti,
@@ -1274,6 +1343,7 @@ static struct clksrc_clk *sysclks[] = {
 	&clk_sclk_audio0,
 	&clk_sclk_audio1,
 	&clk_sclk_audio2,
+	&clk_sclk_spdif,
 };
 
 static u32 epll_div[][6] = {
-- 
1.7.2.3

[PATCH 2/5] ARM: EXYNOS4: Add sclk_spdif clocks

[Naveen Krishna Chatradhi]

Add the sclk_spdif clock is of type 'struct clksrc_clk' clock.
Also, add clk_spdifcdclk clocks of type 'struct clk' clock.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
 arch/arm/mach-exynos4/clock.c |   70 +++++++++++++++++++++++++++++++++++++++++
 1 files changed, 70 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 7aa4aef..57ca356 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -73,6 +73,11 @@ static struct clk clk_audiocdclk2 = {
 	.id		= 2,
 };
 
+static struct clk clk_spdifcdclk = {
+	.name		= "spdifcdclk",
+	.id		= -1,
+};
+
 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
 {
 	return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
@@ -592,6 +597,11 @@ static struct clk init_clocks_off[] = {
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 21),
 	}, {
+		.name		= "spdif",
+		.id		= -1,
+		.enable		= exynos4_clk_ip_peril_ctrl,
+		.ctrlbit	= (1 << 26),
+	}, {
 		.name		= "ac97",
 		.id		= -1,
 		.enable		= exynos4_clk_ip_peril_ctrl,
@@ -858,6 +868,65 @@ static struct clk init_clocks[] = {
 	}
 };
 
+static int exynos4_spdif_set_rate(struct clk *clk, unsigned long rate)
+{
+	struct clk *pclk;
+	int ret;
+
+	pclk = clk_get_parent(clk);
+	if (IS_ERR(pclk))
+		return -EINVAL;
+
+	ret = pclk->ops->set_rate(pclk, rate);
+	clk_put(pclk);
+
+	return ret;
+}
+
+static unsigned long exynos4_spdif_get_rate(struct clk *clk)
+{
+	struct clk *pclk;
+	int rate;
+
+	pclk = clk_get_parent(clk);
+	if (IS_ERR(pclk))
+		return -EINVAL;
+
+	rate = pclk->ops->get_rate(clk);
+	clk_put(pclk);
+
+	return rate;
+}
+
+static struct clk_ops exynos4_sclk_spdif_ops = {
+	.set_rate	= exynos4_spdif_set_rate,
+	.get_rate	= exynos4_spdif_get_rate,
+};
+
+static struct clk *clkset_sclk_spdif_list[] = {
+	[0] = &clk_sclk_audio0.clk,
+	[1] = &clk_sclk_audio1.clk,
+	[2] = &clk_sclk_audio2.clk,
+	[3] = &clk_spdifcdclk,
+};
+
+static struct clksrc_sources clkset_sclk_spdif = {
+	.sources	= clkset_sclk_spdif_list,
+	.nr_sources	= ARRAY_SIZE(clkset_sclk_spdif_list),
+};
+
+static struct clksrc_clk clk_sclk_spdif = {
+	.clk	= {
+		.name		= "sclk_spdif",
+		.id		= -1,
+		.enable		= exynos4_clksrc_mask_peril1_ctrl,
+		.ctrlbit	= (1 << 8),
+		.ops		= &exynos4_sclk_spdif_ops,
+	},
+		.sources = &clkset_sclk_spdif,
+		.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 8, .size = 2 },
+};
+
 static struct clk *clkset_group_list[] = {
 	[0] = &clk_ext_xtal_mux,
 	[1] = &clk_xusbxti,
@@ -1274,6 +1343,7 @@ static struct clksrc_clk *sysclks[] = {
 	&clk_sclk_audio0,
 	&clk_sclk_audio1,
 	&clk_sclk_audio2,
+	&clk_sclk_spdif,
 };
 
 static u32 epll_div[][6] = {
-- 
1.7.2.3

[PATCH 3/5] ARM: EXYNOS4: fix improper gpio configuration

[Naveen Krishna Chatradhi]

These pins are incorrectly configured for PCM2
configure them to SPDIF(_OUT & _EXT_CLK)

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
 arch/arm/mach-exynos4/dev-audio.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-exynos4/dev-audio.c b/arch/arm/mach-exynos4/dev-audio.c
index 6347594..5add5fa 100644
--- a/arch/arm/mach-exynos4/dev-audio.c
+++ b/arch/arm/mach-exynos4/dev-audio.c
@@ -335,7 +335,7 @@ struct platform_device exynos4_device_ac97 = {
 
 static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
 {
-	s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(3));
+	s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4));
 
 	return 0;
 }
-- 
1.7.2.3

[PATCH 3/5] ARM: EXYNOS4: fix improper gpio configuration

[Naveen Krishna Chatradhi]

These pins are incorrectly configured for PCM2
configure them to SPDIF(_OUT & _EXT_CLK)

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
 arch/arm/mach-exynos4/dev-audio.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-exynos4/dev-audio.c b/arch/arm/mach-exynos4/dev-audio.c
index 6347594..5add5fa 100644
--- a/arch/arm/mach-exynos4/dev-audio.c
+++ b/arch/arm/mach-exynos4/dev-audio.c
@@ -335,7 +335,7 @@ struct platform_device exynos4_device_ac97 = {
 
 static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
 {
-	s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(3));
+	s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4));
 
 	return 0;
 }
-- 
1.7.2.3

[PATCH 4/5] ARM: EXYNOS4: Add SPDIF for SMDKV310

[Naveen Krishna Chatradhi]

This patch adds spdif to the machine supported device list for
SMDKV310.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
 arch/arm/mach-exynos4/mach-smdkv310.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
index 7e3ee6c..966c6f2 100644
--- a/arch/arm/mach-exynos4/mach-smdkv310.c
+++ b/arch/arm/mach-exynos4/mach-smdkv310.c
@@ -190,6 +190,7 @@ static struct platform_device *smdkv310_devices[] __initdata = {
 	&exynos4_device_pd[PD_CAM],
 	&exynos4_device_pd[PD_TV],
 	&exynos4_device_pd[PD_GPS],
+	&exynos4_device_spdif,
 	&exynos4_device_sysmmu,
 	&exynos4_device_pcm0,
 	&samsung_asoc_dma,
-- 
1.7.2.3

[PATCH 4/5] ARM: EXYNOS4: Add SPDIF for SMDKV310

[Naveen Krishna Chatradhi]

This patch adds spdif to the machine supported device list for
SMDKV310.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
 arch/arm/mach-exynos4/mach-smdkv310.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
index 7e3ee6c..966c6f2 100644
--- a/arch/arm/mach-exynos4/mach-smdkv310.c
+++ b/arch/arm/mach-exynos4/mach-smdkv310.c
@@ -190,6 +190,7 @@ static struct platform_device *smdkv310_devices[] __initdata = {
 	&exynos4_device_pd[PD_CAM],
 	&exynos4_device_pd[PD_TV],
 	&exynos4_device_pd[PD_GPS],
+	&exynos4_device_spdif,
 	&exynos4_device_sysmmu,
 	&exynos4_device_pcm0,
 	&samsung_asoc_dma,
-- 
1.7.2.3

[PATCH 5/5] ASoC: SMDKV310: Enable SPDIF device

[Naveen Krishna Chatradhi]

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
 sound/soc/samsung/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
index d155cbb..92236eb 100644
--- a/sound/soc/samsung/Kconfig
+++ b/sound/soc/samsung/Kconfig
@@ -158,7 +158,7 @@ config SND_SOC_GONI_AQUILA_WM8994
 
 config SND_SOC_SAMSUNG_SMDK_SPDIF
 	tristate "SoC S/PDIF Audio support for SMDK"
-	depends on SND_SOC_SAMSUNG && (MACH_SMDKC100 || MACH_SMDKC110 || MACH_SMDKV210)
+	depends on SND_SOC_SAMSUNG && (MACH_SMDKC100 || MACH_SMDKC110 || MACH_SMDKV210 || MACH_SMDKV310)
 	select SND_SAMSUNG_SPDIF
 	help
 	  Say Y if you want to add support for SoC S/PDIF audio on the SMDK.
-- 
1.7.2.3

[PATCH 5/5] ASoC: SMDKV310: Enable SPDIF device

[Naveen Krishna Chatradhi]

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
 sound/soc/samsung/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
index d155cbb..92236eb 100644
--- a/sound/soc/samsung/Kconfig
+++ b/sound/soc/samsung/Kconfig
@@ -158,7 +158,7 @@ config SND_SOC_GONI_AQUILA_WM8994
 
 config SND_SOC_SAMSUNG_SMDK_SPDIF
 	tristate "SoC S/PDIF Audio support for SMDK"
-	depends on SND_SOC_SAMSUNG && (MACH_SMDKC100 || MACH_SMDKC110 || MACH_SMDKV210)
+	depends on SND_SOC_SAMSUNG && (MACH_SMDKC100 || MACH_SMDKC110 || MACH_SMDKV210 || MACH_SMDKV310)
 	select SND_SAMSUNG_SPDIF
 	help
 	  Say Y if you want to add support for SoC S/PDIF audio on the SMDK.
-- 
1.7.2.3

Re: [PATCH 3/5] ARM: EXYNOS4: fix improper gpio configuration

[Jassi Brar]

On Fri, Jun 10, 2011 at 12:04 PM, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> These pins are incorrectly configured for PCM2
> configure them to SPDIF(_OUT & _EXT_CLK)
>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
>  arch/arm/mach-exynos4/dev-audio.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-exynos4/dev-audio.c b/arch/arm/mach-exynos4/dev-audio.c
> index 6347594..5add5fa 100644
> --- a/arch/arm/mach-exynos4/dev-audio.c
> +++ b/arch/arm/mach-exynos4/dev-audio.c
> @@ -335,7 +335,7 @@ struct platform_device exynos4_device_ac97 = {
>
>  static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
>  {
> -       s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(3));
> +       s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4));
>
>        return 0;
>  }

Acked-by: Jassi Brar <jassisinghbrar@gmail.com>

[PATCH 3/5] ARM: EXYNOS4: fix improper gpio configuration

[Jassi Brar]

On Fri, Jun 10, 2011 at 12:04 PM, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> These pins are incorrectly configured for PCM2
> configure them to SPDIF(_OUT & _EXT_CLK)
>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
> ?arch/arm/mach-exynos4/dev-audio.c | ? ?2 +-
> ?1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-exynos4/dev-audio.c b/arch/arm/mach-exynos4/dev-audio.c
> index 6347594..5add5fa 100644
> --- a/arch/arm/mach-exynos4/dev-audio.c
> +++ b/arch/arm/mach-exynos4/dev-audio.c
> @@ -335,7 +335,7 @@ struct platform_device exynos4_device_ac97 = {
>
> ?static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
> ?{
> - ? ? ? s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(3));
> + ? ? ? s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4));
>
> ? ? ? ?return 0;
> ?}

Acked-by: Jassi Brar <jassisinghbrar@gmail.com>

Re: [PATCH 4/5] ARM: EXYNOS4: Add SPDIF for SMDKV310

[Jassi Brar]

On Fri, Jun 10, 2011 at 12:04 PM, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> This patch adds spdif to the machine supported device list for
> SMDKV310.
>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
>  arch/arm/mach-exynos4/mach-smdkv310.c |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
> index 7e3ee6c..966c6f2 100644
> --- a/arch/arm/mach-exynos4/mach-smdkv310.c
> +++ b/arch/arm/mach-exynos4/mach-smdkv310.c
> @@ -190,6 +190,7 @@ static struct platform_device *smdkv310_devices[] __initdata = {
>        &exynos4_device_pd[PD_CAM],
>        &exynos4_device_pd[PD_TV],
>        &exynos4_device_pd[PD_GPS],
> +       &exynos4_device_spdif,
>        &exynos4_device_sysmmu,
>        &exynos4_device_pcm0,
>        &samsung_asoc_dma,

Acked-by: Jassi Brar <jassisinghbrar@gmail.com>

[PATCH 4/5] ARM: EXYNOS4: Add SPDIF for SMDKV310

[Jassi Brar]

On Fri, Jun 10, 2011 at 12:04 PM, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> This patch adds spdif to the machine supported device list for
> SMDKV310.
>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
> ?arch/arm/mach-exynos4/mach-smdkv310.c | ? ?1 +
> ?1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
> index 7e3ee6c..966c6f2 100644
> --- a/arch/arm/mach-exynos4/mach-smdkv310.c
> +++ b/arch/arm/mach-exynos4/mach-smdkv310.c
> @@ -190,6 +190,7 @@ static struct platform_device *smdkv310_devices[] __initdata = {
> ? ? ? ?&exynos4_device_pd[PD_CAM],
> ? ? ? ?&exynos4_device_pd[PD_TV],
> ? ? ? ?&exynos4_device_pd[PD_GPS],
> + ? ? ? &exynos4_device_spdif,
> ? ? ? ?&exynos4_device_sysmmu,
> ? ? ? ?&exynos4_device_pcm0,
> ? ? ? ?&samsung_asoc_dma,

Acked-by: Jassi Brar <jassisinghbrar@gmail.com>

Re: [PATCH 5/5] ASoC: SMDKV310: Enable SPDIF device

[Jassi Brar]

On Fri, Jun 10, 2011 at 12:04 PM, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
>  sound/soc/samsung/Kconfig |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
> index d155cbb..92236eb 100644
> --- a/sound/soc/samsung/Kconfig
> +++ b/sound/soc/samsung/Kconfig
> @@ -158,7 +158,7 @@ config SND_SOC_GONI_AQUILA_WM8994
>
>  config SND_SOC_SAMSUNG_SMDK_SPDIF
>        tristate "SoC S/PDIF Audio support for SMDK"
> -       depends on SND_SOC_SAMSUNG && (MACH_SMDKC100 || MACH_SMDKC110 || MACH_SMDKV210)
> +       depends on SND_SOC_SAMSUNG && (MACH_SMDKC100 || MACH_SMDKC110 || MACH_SMDKV210 || MACH_SMDKV310)
>        select SND_SAMSUNG_SPDIF
>        help
>          Say Y if you want to add support for SoC S/PDIF audio on the SMDK.

Acked-by: Jassi Brar <jassisinghbrar@gmail.com>

[PATCH 5/5] ASoC: SMDKV310: Enable SPDIF device

[Jassi Brar]

On Fri, Jun 10, 2011 at 12:04 PM, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
> ?sound/soc/samsung/Kconfig | ? ?2 +-
> ?1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
> index d155cbb..92236eb 100644
> --- a/sound/soc/samsung/Kconfig
> +++ b/sound/soc/samsung/Kconfig
> @@ -158,7 +158,7 @@ config SND_SOC_GONI_AQUILA_WM8994
>
> ?config SND_SOC_SAMSUNG_SMDK_SPDIF
> ? ? ? ?tristate "SoC S/PDIF Audio support for SMDK"
> - ? ? ? depends on SND_SOC_SAMSUNG && (MACH_SMDKC100 || MACH_SMDKC110 || MACH_SMDKV210)
> + ? ? ? depends on SND_SOC_SAMSUNG && (MACH_SMDKC100 || MACH_SMDKC110 || MACH_SMDKV210 || MACH_SMDKV310)
> ? ? ? ?select SND_SAMSUNG_SPDIF
> ? ? ? ?help
> ? ? ? ? ?Say Y if you want to add support for SoC S/PDIF audio on the SMDK.

Acked-by: Jassi Brar <jassisinghbrar@gmail.com>

Re: [PATCH 5/5] ASoC: SMDKV310: Enable SPDIF device

[Mark Brown]

On Fri, Jun 10, 2011 at 12:04:27PM +0530, Naveen Krishna Chatradhi wrote:
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>

Applied, thanks.

[PATCH 5/5] ASoC: SMDKV310: Enable SPDIF device

[Mark Brown]

On Fri, Jun 10, 2011 at 12:04:27PM +0530, Naveen Krishna Chatradhi wrote:
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>

Applied, thanks.

RE: [PATCH 1/5] ARM: EXYNOS4: Add EPLL clock operations

[Kukjin Kim]

Naveen Krishna Chatradhi wrote:
> 
> This patch adds EPLL specific clock get_rate/set_rate
> operations on EXYNOS4.
> 
> Note: Initial code from S5PV210
> http://permalink.gmane.org/gmane.linux.alsa.devel/77519
> 
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
>  arch/arm/mach-exynos4/clock.c |   78
> +++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 78 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
> index b1b93b9..7aa4aef 100644
> --- a/arch/arm/mach-exynos4/clock.c
> +++ b/arch/arm/mach-exynos4/clock.c
> @@ -1276,6 +1276,82 @@ static struct clksrc_clk *sysclks[] = {
>  	&clk_sclk_audio2,
>  };
> 
> +static u32 epll_div[][6] = {
> +	{  48000000, 0, 48, 3, 3, 0 },
> +	{  96000000, 0, 48, 3, 2, 0 },
> +	{ 144000000, 1, 72, 3, 2, 0 },
> +	{ 192000000, 0, 48, 3, 1, 0 },
> +	{ 288000000, 1, 72, 3, 1, 0 },
> +	{  32750000, 1, 65, 3, 4, 35127 },
> +	{  32768000, 1, 65, 3, 4, 35127 },
> +	{  45158400, 0, 45, 3, 3, 10355 },
> +	{  45000000, 0, 45, 3, 3, 10355 },
> +	{  45158000, 0, 45, 3, 3, 10355 },
> +	{  49125000, 0, 49, 3, 3, 9961 },
> +	{  49152000, 0, 49, 3, 3, 9961 },
> +	{  67737600, 1, 67, 3, 3, 48366 },
> +	{  67738000, 1, 67, 3, 3, 48366 },
> +	{  73800000, 1, 73, 3, 3, 47710 },
> +	{  73728000, 1, 73, 3, 3, 47710 },
> +	{  36000000, 1, 32, 3, 4, 0 },
> +	{  60000000, 1, 60, 3, 3, 0 },
> +	{  72000000, 1, 72, 3, 3, 0 },
> +	{  80000000, 1, 80, 3, 3, 0 },
> +	{  84000000, 0, 42, 3, 2, 0 },
> +	{  50000000, 0, 50, 3, 3, 0 },
> +};
> +
> +static int exynos4_epll_set_rate(struct clk *clk, unsigned long rate)
> +{
> +	unsigned int epll_con, epll_con_k;
> +	unsigned int i;
> +
> +	/* Return if nothing changed */
> +	if (clk->rate == rate)
> +		return 0;
> +
> +	epll_con = __raw_readl(S5P_EPLL_CON);
> +	epll_con_k = __raw_readl(S5P_EPLL_CON1);
> +
> +	epll_con_k &= ~PLL46XX_KDIV_MASK;
> +	epll_con &= ~(1 << 27 |
> +			PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
> +			PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
> +			PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
> +
> +	for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
> +		if (epll_div[i][0] == rate) {
> +			epll_con_k |= epll_div[i][5] << 0;
> +			epll_con |= (epll_div[i][1] << 27 |
> +					epll_div[i][2] <<
> PLL46XX_MDIV_SHIFT |
> +					epll_div[i][3] <<
> PLL46XX_PDIV_SHIFT |
> +					epll_div[i][4] <<
> PLL46XX_SDIV_SHIFT);
> +			break;
> +		}
> +	}
> +
> +	if (i == ARRAY_SIZE(epll_div)) {
> +		printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
> +				__func__);
> +		return -EINVAL;
> +	}
> +
> +	__raw_writel(epll_con, S5P_EPLL_CON);
> +	__raw_writel(epll_con_k, S5P_EPLL_CON1);
> +
> +	printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
> +			clk->rate, rate);
> +
> +	clk->rate = rate;
> +
> +	return 0;
> +}

I think, this is same with S5PV210.

Would be better if this could be moved into plat-s5p/ with other set_pllXXX.

> +
> +static struct clk_ops exynos4_epll_ops = {
> +	.set_rate = exynos4_epll_set_rate,
> +	.get_rate = s5p_epll_get_rate,
> +};
> +
>  static int xtal_rate;
> 
>  static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
> @@ -1354,6 +1430,8 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
>  	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
>  		s3c_set_clksrc(&clksrcs[ptr], true);
> 
> +	clk_fout_epll.ops = &exynos4_epll_ops;
> +
>  	clk_audiocdclk0.rate = PCM_EXTCLK0;
>  	clk_set_parent(&clk_sclk_audio0.clk, &clk_audiocdclk0);
>  }
> --



Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH 1/5] ARM: EXYNOS4: Add EPLL clock operations

[Kukjin Kim]

Naveen Krishna Chatradhi wrote:
> 
> This patch adds EPLL specific clock get_rate/set_rate
> operations on EXYNOS4.
> 
> Note: Initial code from S5PV210
> http://permalink.gmane.org/gmane.linux.alsa.devel/77519
> 
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
>  arch/arm/mach-exynos4/clock.c |   78
> +++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 78 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
> index b1b93b9..7aa4aef 100644
> --- a/arch/arm/mach-exynos4/clock.c
> +++ b/arch/arm/mach-exynos4/clock.c
> @@ -1276,6 +1276,82 @@ static struct clksrc_clk *sysclks[] = {
>  	&clk_sclk_audio2,
>  };
> 
> +static u32 epll_div[][6] = {
> +	{  48000000, 0, 48, 3, 3, 0 },
> +	{  96000000, 0, 48, 3, 2, 0 },
> +	{ 144000000, 1, 72, 3, 2, 0 },
> +	{ 192000000, 0, 48, 3, 1, 0 },
> +	{ 288000000, 1, 72, 3, 1, 0 },
> +	{  32750000, 1, 65, 3, 4, 35127 },
> +	{  32768000, 1, 65, 3, 4, 35127 },
> +	{  45158400, 0, 45, 3, 3, 10355 },
> +	{  45000000, 0, 45, 3, 3, 10355 },
> +	{  45158000, 0, 45, 3, 3, 10355 },
> +	{  49125000, 0, 49, 3, 3, 9961 },
> +	{  49152000, 0, 49, 3, 3, 9961 },
> +	{  67737600, 1, 67, 3, 3, 48366 },
> +	{  67738000, 1, 67, 3, 3, 48366 },
> +	{  73800000, 1, 73, 3, 3, 47710 },
> +	{  73728000, 1, 73, 3, 3, 47710 },
> +	{  36000000, 1, 32, 3, 4, 0 },
> +	{  60000000, 1, 60, 3, 3, 0 },
> +	{  72000000, 1, 72, 3, 3, 0 },
> +	{  80000000, 1, 80, 3, 3, 0 },
> +	{  84000000, 0, 42, 3, 2, 0 },
> +	{  50000000, 0, 50, 3, 3, 0 },
> +};
> +
> +static int exynos4_epll_set_rate(struct clk *clk, unsigned long rate)
> +{
> +	unsigned int epll_con, epll_con_k;
> +	unsigned int i;
> +
> +	/* Return if nothing changed */
> +	if (clk->rate == rate)
> +		return 0;
> +
> +	epll_con = __raw_readl(S5P_EPLL_CON);
> +	epll_con_k = __raw_readl(S5P_EPLL_CON1);
> +
> +	epll_con_k &= ~PLL46XX_KDIV_MASK;
> +	epll_con &= ~(1 << 27 |
> +			PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
> +			PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
> +			PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
> +
> +	for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
> +		if (epll_div[i][0] == rate) {
> +			epll_con_k |= epll_div[i][5] << 0;
> +			epll_con |= (epll_div[i][1] << 27 |
> +					epll_div[i][2] <<
> PLL46XX_MDIV_SHIFT |
> +					epll_div[i][3] <<
> PLL46XX_PDIV_SHIFT |
> +					epll_div[i][4] <<
> PLL46XX_SDIV_SHIFT);
> +			break;
> +		}
> +	}
> +
> +	if (i == ARRAY_SIZE(epll_div)) {
> +		printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
> +				__func__);
> +		return -EINVAL;
> +	}
> +
> +	__raw_writel(epll_con, S5P_EPLL_CON);
> +	__raw_writel(epll_con_k, S5P_EPLL_CON1);
> +
> +	printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
> +			clk->rate, rate);
> +
> +	clk->rate = rate;
> +
> +	return 0;
> +}

I think, this is same with S5PV210.

Would be better if this could be moved into plat-s5p/ with other set_pllXXX.

> +
> +static struct clk_ops exynos4_epll_ops = {
> +	.set_rate = exynos4_epll_set_rate,
> +	.get_rate = s5p_epll_get_rate,
> +};
> +
>  static int xtal_rate;
> 
>  static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
> @@ -1354,6 +1430,8 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
>  	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
>  		s3c_set_clksrc(&clksrcs[ptr], true);
> 
> +	clk_fout_epll.ops = &exynos4_epll_ops;
> +
>  	clk_audiocdclk0.rate = PCM_EXTCLK0;
>  	clk_set_parent(&clk_sclk_audio0.clk, &clk_audiocdclk0);
>  }
> --



Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

RE: [PATCH 2/5] ARM: EXYNOS4: Add sclk_spdif clocks

[Kukjin Kim]

> From: Naveen Krishna Chatradhi wrote:
> 
> Add the sclk_spdif clock is of type 'struct clksrc_clk' clock.
> Also, add clk_spdifcdclk clocks of type 'struct clk' clock.
> 
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
>  arch/arm/mach-exynos4/clock.c |   70
> +++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 70 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
> index 7aa4aef..57ca356 100644
> --- a/arch/arm/mach-exynos4/clock.c
> +++ b/arch/arm/mach-exynos4/clock.c
> @@ -73,6 +73,11 @@ static struct clk clk_audiocdclk2 = {
>  	.id		= 2,
>  };
> 
> +static struct clk clk_spdifcdclk = {
> +	.name		= "spdifcdclk",
> +	.id		= -1,
> +};

Do we really need this?

spdif_extclk? not spdifcdclk.

> +
>  static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
>  {
>  	return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
> @@ -592,6 +597,11 @@ static struct clk init_clocks_off[] = {
>  		.enable		= exynos4_clk_ip_peril_ctrl,
>  		.ctrlbit	= (1 << 21),
>  	}, {
> +		.name		= "spdif",
> +		.id		= -1,
> +		.enable		= exynos4_clk_ip_peril_ctrl,
> +		.ctrlbit	= (1 << 26),
> +	}, {
>  		.name		= "ac97",
>  		.id		= -1,
>  		.enable		= exynos4_clk_ip_peril_ctrl,
> @@ -858,6 +868,65 @@ static struct clk init_clocks[] = {
>  	}
>  };
> 
> +static int exynos4_spdif_set_rate(struct clk *clk, unsigned long rate)
> +{
> +	struct clk *pclk;
> +	int ret;
> +
> +	pclk = clk_get_parent(clk);
> +	if (IS_ERR(pclk))
> +		return -EINVAL;
> +
> +	ret = pclk->ops->set_rate(pclk, rate);
> +	clk_put(pclk);
> +
> +	return ret;
> +}
> +
> +static unsigned long exynos4_spdif_get_rate(struct clk *clk)
> +{
> +	struct clk *pclk;
> +	int rate;
> +
> +	pclk = clk_get_parent(clk);
> +	if (IS_ERR(pclk))
> +		return -EINVAL;
> +
> +	rate = pclk->ops->get_rate(clk);
> +	clk_put(pclk);
> +
> +	return rate;
> +}

I think, we can move above into plat-s5p for common spdif with others.

> +
> +static struct clk_ops exynos4_sclk_spdif_ops = {
> +	.set_rate	= exynos4_spdif_set_rate,
> +	.get_rate	= exynos4_spdif_get_rate,
> +};
> +
> +static struct clk *clkset_sclk_spdif_list[] = {
> +	[0] = &clk_sclk_audio0.clk,
> +	[1] = &clk_sclk_audio1.clk,
> +	[2] = &clk_sclk_audio2.clk,
> +	[3] = &clk_spdifcdclk,
> +};
> +
> +static struct clksrc_sources clkset_sclk_spdif = {
> +	.sources	= clkset_sclk_spdif_list,
> +	.nr_sources	= ARRAY_SIZE(clkset_sclk_spdif_list),
> +};
> +
> +static struct clksrc_clk clk_sclk_spdif = {
> +	.clk	= {
> +		.name		= "sclk_spdif",
> +		.id		= -1,
> +		.enable		= exynos4_clksrc_mask_peril1_ctrl,
> +		.ctrlbit	= (1 << 8),
> +		.ops		= &exynos4_sclk_spdif_ops,
> +	},
> +		.sources = &clkset_sclk_spdif,
> +		.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 8, .size = 2
},
> +};
> +
>  static struct clk *clkset_group_list[] = {
>  	[0] = &clk_ext_xtal_mux,
>  	[1] = &clk_xusbxti,
> @@ -1274,6 +1343,7 @@ static struct clksrc_clk *sysclks[] = {
>  	&clk_sclk_audio0,
>  	&clk_sclk_audio1,
>  	&clk_sclk_audio2,
> +	&clk_sclk_spdif,
>  };
> 
>  static u32 epll_div[][6] = {
> --
> 1.7.2.3



Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH 2/5] ARM: EXYNOS4: Add sclk_spdif clocks

[Kukjin Kim]

> From: Naveen Krishna Chatradhi wrote:
> 
> Add the sclk_spdif clock is of type 'struct clksrc_clk' clock.
> Also, add clk_spdifcdclk clocks of type 'struct clk' clock.
> 
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
>  arch/arm/mach-exynos4/clock.c |   70
> +++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 70 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
> index 7aa4aef..57ca356 100644
> --- a/arch/arm/mach-exynos4/clock.c
> +++ b/arch/arm/mach-exynos4/clock.c
> @@ -73,6 +73,11 @@ static struct clk clk_audiocdclk2 = {
>  	.id		= 2,
>  };
> 
> +static struct clk clk_spdifcdclk = {
> +	.name		= "spdifcdclk",
> +	.id		= -1,
> +};

Do we really need this?

spdif_extclk? not spdifcdclk.

> +
>  static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
>  {
>  	return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
> @@ -592,6 +597,11 @@ static struct clk init_clocks_off[] = {
>  		.enable		= exynos4_clk_ip_peril_ctrl,
>  		.ctrlbit	= (1 << 21),
>  	}, {
> +		.name		= "spdif",
> +		.id		= -1,
> +		.enable		= exynos4_clk_ip_peril_ctrl,
> +		.ctrlbit	= (1 << 26),
> +	}, {
>  		.name		= "ac97",
>  		.id		= -1,
>  		.enable		= exynos4_clk_ip_peril_ctrl,
> @@ -858,6 +868,65 @@ static struct clk init_clocks[] = {
>  	}
>  };
> 
> +static int exynos4_spdif_set_rate(struct clk *clk, unsigned long rate)
> +{
> +	struct clk *pclk;
> +	int ret;
> +
> +	pclk = clk_get_parent(clk);
> +	if (IS_ERR(pclk))
> +		return -EINVAL;
> +
> +	ret = pclk->ops->set_rate(pclk, rate);
> +	clk_put(pclk);
> +
> +	return ret;
> +}
> +
> +static unsigned long exynos4_spdif_get_rate(struct clk *clk)
> +{
> +	struct clk *pclk;
> +	int rate;
> +
> +	pclk = clk_get_parent(clk);
> +	if (IS_ERR(pclk))
> +		return -EINVAL;
> +
> +	rate = pclk->ops->get_rate(clk);
> +	clk_put(pclk);
> +
> +	return rate;
> +}

I think, we can move above into plat-s5p for common spdif with others.

> +
> +static struct clk_ops exynos4_sclk_spdif_ops = {
> +	.set_rate	= exynos4_spdif_set_rate,
> +	.get_rate	= exynos4_spdif_get_rate,
> +};
> +
> +static struct clk *clkset_sclk_spdif_list[] = {
> +	[0] = &clk_sclk_audio0.clk,
> +	[1] = &clk_sclk_audio1.clk,
> +	[2] = &clk_sclk_audio2.clk,
> +	[3] = &clk_spdifcdclk,
> +};
> +
> +static struct clksrc_sources clkset_sclk_spdif = {
> +	.sources	= clkset_sclk_spdif_list,
> +	.nr_sources	= ARRAY_SIZE(clkset_sclk_spdif_list),
> +};
> +
> +static struct clksrc_clk clk_sclk_spdif = {
> +	.clk	= {
> +		.name		= "sclk_spdif",
> +		.id		= -1,
> +		.enable		= exynos4_clksrc_mask_peril1_ctrl,
> +		.ctrlbit	= (1 << 8),
> +		.ops		= &exynos4_sclk_spdif_ops,
> +	},
> +		.sources = &clkset_sclk_spdif,
> +		.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 8, .size = 2
},
> +};
> +
>  static struct clk *clkset_group_list[] = {
>  	[0] = &clk_ext_xtal_mux,
>  	[1] = &clk_xusbxti,
> @@ -1274,6 +1343,7 @@ static struct clksrc_clk *sysclks[] = {
>  	&clk_sclk_audio0,
>  	&clk_sclk_audio1,
>  	&clk_sclk_audio2,
> +	&clk_sclk_spdif,
>  };
> 
>  static u32 epll_div[][6] = {
> --
> 1.7.2.3



Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

Re: [PATCH 2/5] ARM: EXYNOS4: Add sclk_spdif clocks

[Naveen Krishna Ch]

Hi Kukjin,

On 14 June 2011 11:17, Kukjin Kim <kgene.kim@samsung.com> wrote:
>> From: Naveen Krishna Chatradhi wrote:
>>
>> Add the sclk_spdif clock is of type 'struct clksrc_clk' clock.
>> Also, add clk_spdifcdclk clocks of type 'struct clk' clock.
>>
>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>> ---
>>  arch/arm/mach-exynos4/clock.c |   70
>> +++++++++++++++++++++++++++++++++++++++++
>>  1 files changed, 70 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
>> index 7aa4aef..57ca356 100644
>> --- a/arch/arm/mach-exynos4/clock.c
>> +++ b/arch/arm/mach-exynos4/clock.c
>> @@ -73,6 +73,11 @@ static struct clk clk_audiocdclk2 = {
>>       .id             = 2,
>>  };
>>
>> +static struct clk clk_spdifcdclk = {
>> +     .name           = "spdifcdclk",
>> +     .id             = -1,
>> +};
>
> Do we really need this?
This is to complete the clock structure.
>
> spdif_extclk? not spdifcdclk.
Sorry, my bad. Will change
>
>> +
>>  static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
>>  {
>>       return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
>> @@ -592,6 +597,11 @@ static struct clk init_clocks_off[] = {
>>               .enable         = exynos4_clk_ip_peril_ctrl,
>>               .ctrlbit        = (1 << 21),
>>       }, {
>> +             .name           = "spdif",
>> +             .id             = -1,
>> +             .enable         = exynos4_clk_ip_peril_ctrl,
>> +             .ctrlbit        = (1 << 26),
>> +     }, {
>>               .name           = "ac97",
>>               .id             = -1,
>>               .enable         = exynos4_clk_ip_peril_ctrl,
>> @@ -858,6 +868,65 @@ static struct clk init_clocks[] = {
>>       }
>>  };
>>
>> +static int exynos4_spdif_set_rate(struct clk *clk, unsigned long rate)
>> +{
>> +     struct clk *pclk;
>> +     int ret;
>> +
>> +     pclk = clk_get_parent(clk);
>> +     if (IS_ERR(pclk))
>> +             return -EINVAL;
>> +
>> +     ret = pclk->ops->set_rate(pclk, rate);
>> +     clk_put(pclk);
>> +
>> +     return ret;
>> +}
>> +
>> +static unsigned long exynos4_spdif_get_rate(struct clk *clk)
>> +{
>> +     struct clk *pclk;
>> +     int rate;
>> +
>> +     pclk = clk_get_parent(clk);
>> +     if (IS_ERR(pclk))
>> +             return -EINVAL;
>> +
>> +     rate = pclk->ops->get_rate(clk);
>> +     clk_put(pclk);
>> +
>> +     return rate;
>> +}
>
> I think, we can move above into plat-s5p for common spdif with others.
Sure, Will move.
Note: It wont apply for S5P64X0 series.
>
>> +
>> +static struct clk_ops exynos4_sclk_spdif_ops = {
>> +     .set_rate       = exynos4_spdif_set_rate,
>> +     .get_rate       = exynos4_spdif_get_rate,
>> +};
>> +
>> +static struct clk *clkset_sclk_spdif_list[] = {
>> +     [0] = &clk_sclk_audio0.clk,
>> +     [1] = &clk_sclk_audio1.clk,
>> +     [2] = &clk_sclk_audio2.clk,
>> +     [3] = &clk_spdifcdclk,
>> +};
>> +
>> +static struct clksrc_sources clkset_sclk_spdif = {
>> +     .sources        = clkset_sclk_spdif_list,
>> +     .nr_sources     = ARRAY_SIZE(clkset_sclk_spdif_list),
>> +};
>> +
>> +static struct clksrc_clk clk_sclk_spdif = {
>> +     .clk    = {
>> +             .name           = "sclk_spdif",
>> +             .id             = -1,
>> +             .enable         = exynos4_clksrc_mask_peril1_ctrl,
>> +             .ctrlbit        = (1 << 8),
>> +             .ops            = &exynos4_sclk_spdif_ops,
>> +     },
>> +             .sources = &clkset_sclk_spdif,
>> +             .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 8, .size = 2
> },
>> +};
>> +
>>  static struct clk *clkset_group_list[] = {
>>       [0] = &clk_ext_xtal_mux,
>>       [1] = &clk_xusbxti,
>> @@ -1274,6 +1343,7 @@ static struct clksrc_clk *sysclks[] = {
>>       &clk_sclk_audio0,
>>       &clk_sclk_audio1,
>>       &clk_sclk_audio2,
>> +     &clk_sclk_spdif,
>>  };
>>
>>  static u32 epll_div[][6] = {
>> --
>> 1.7.2.3
>
>
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>



-- 
Shine bright,
(: Nav :)

[PATCH 2/5] ARM: EXYNOS4: Add sclk_spdif clocks

[Naveen Krishna Ch]

Hi Kukjin,

On 14 June 2011 11:17, Kukjin Kim <kgene.kim@samsung.com> wrote:
>> From: Naveen Krishna Chatradhi wrote:
>>
>> Add the sclk_spdif clock is of type 'struct clksrc_clk' clock.
>> Also, add clk_spdifcdclk clocks of type 'struct clk' clock.
>>
>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>> ---
>> ?arch/arm/mach-exynos4/clock.c | ? 70
>> +++++++++++++++++++++++++++++++++++++++++
>> ?1 files changed, 70 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
>> index 7aa4aef..57ca356 100644
>> --- a/arch/arm/mach-exynos4/clock.c
>> +++ b/arch/arm/mach-exynos4/clock.c
>> @@ -73,6 +73,11 @@ static struct clk clk_audiocdclk2 = {
>> ? ? ? .id ? ? ? ? ? ? = 2,
>> ?};
>>
>> +static struct clk clk_spdifcdclk = {
>> + ? ? .name ? ? ? ? ? = "spdifcdclk",
>> + ? ? .id ? ? ? ? ? ? = -1,
>> +};
>
> Do we really need this?
This is to complete the clock structure.
>
> spdif_extclk? not spdifcdclk.
Sorry, my bad. Will change
>
>> +
>> ?static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
>> ?{
>> ? ? ? return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
>> @@ -592,6 +597,11 @@ static struct clk init_clocks_off[] = {
>> ? ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clk_ip_peril_ctrl,
>> ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 21),
>> ? ? ? }, {
>> + ? ? ? ? ? ? .name ? ? ? ? ? = "spdif",
>> + ? ? ? ? ? ? .id ? ? ? ? ? ? = -1,
>> + ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clk_ip_peril_ctrl,
>> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 26),
>> + ? ? }, {
>> ? ? ? ? ? ? ? .name ? ? ? ? ? = "ac97",
>> ? ? ? ? ? ? ? .id ? ? ? ? ? ? = -1,
>> ? ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clk_ip_peril_ctrl,
>> @@ -858,6 +868,65 @@ static struct clk init_clocks[] = {
>> ? ? ? }
>> ?};
>>
>> +static int exynos4_spdif_set_rate(struct clk *clk, unsigned long rate)
>> +{
>> + ? ? struct clk *pclk;
>> + ? ? int ret;
>> +
>> + ? ? pclk = clk_get_parent(clk);
>> + ? ? if (IS_ERR(pclk))
>> + ? ? ? ? ? ? return -EINVAL;
>> +
>> + ? ? ret = pclk->ops->set_rate(pclk, rate);
>> + ? ? clk_put(pclk);
>> +
>> + ? ? return ret;
>> +}
>> +
>> +static unsigned long exynos4_spdif_get_rate(struct clk *clk)
>> +{
>> + ? ? struct clk *pclk;
>> + ? ? int rate;
>> +
>> + ? ? pclk = clk_get_parent(clk);
>> + ? ? if (IS_ERR(pclk))
>> + ? ? ? ? ? ? return -EINVAL;
>> +
>> + ? ? rate = pclk->ops->get_rate(clk);
>> + ? ? clk_put(pclk);
>> +
>> + ? ? return rate;
>> +}
>
> I think, we can move above into plat-s5p for common spdif with others.
Sure, Will move.
Note: It wont apply for S5P64X0 series.
>
>> +
>> +static struct clk_ops exynos4_sclk_spdif_ops = {
>> + ? ? .set_rate ? ? ? = exynos4_spdif_set_rate,
>> + ? ? .get_rate ? ? ? = exynos4_spdif_get_rate,
>> +};
>> +
>> +static struct clk *clkset_sclk_spdif_list[] = {
>> + ? ? [0] = &clk_sclk_audio0.clk,
>> + ? ? [1] = &clk_sclk_audio1.clk,
>> + ? ? [2] = &clk_sclk_audio2.clk,
>> + ? ? [3] = &clk_spdifcdclk,
>> +};
>> +
>> +static struct clksrc_sources clkset_sclk_spdif = {
>> + ? ? .sources ? ? ? ?= clkset_sclk_spdif_list,
>> + ? ? .nr_sources ? ? = ARRAY_SIZE(clkset_sclk_spdif_list),
>> +};
>> +
>> +static struct clksrc_clk clk_sclk_spdif = {
>> + ? ? .clk ? ?= {
>> + ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_spdif",
>> + ? ? ? ? ? ? .id ? ? ? ? ? ? = -1,
>> + ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clksrc_mask_peril1_ctrl,
>> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 8),
>> + ? ? ? ? ? ? .ops ? ? ? ? ? ?= &exynos4_sclk_spdif_ops,
>> + ? ? },
>> + ? ? ? ? ? ? .sources = &clkset_sclk_spdif,
>> + ? ? ? ? ? ? .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 8, .size = 2
> },
>> +};
>> +
>> ?static struct clk *clkset_group_list[] = {
>> ? ? ? [0] = &clk_ext_xtal_mux,
>> ? ? ? [1] = &clk_xusbxti,
>> @@ -1274,6 +1343,7 @@ static struct clksrc_clk *sysclks[] = {
>> ? ? ? &clk_sclk_audio0,
>> ? ? ? &clk_sclk_audio1,
>> ? ? ? &clk_sclk_audio2,
>> + ? ? &clk_sclk_spdif,
>> ?};
>>
>> ?static u32 epll_div[][6] = {
>> --
>> 1.7.2.3
>
>
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>



-- 
Shine bright,
(: Nav :)

RE: [PATCH 3/5] ARM: EXYNOS4: fix improper gpio configuration

[Kukjin Kim]

Naveen Krishna Chatradhi wrote:
> 
> These pins are incorrectly configured for PCM2
> configure them to SPDIF(_OUT & _EXT_CLK)
> 
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
>  arch/arm/mach-exynos4/dev-audio.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos4/dev-audio.c
b/arch/arm/mach-exynos4/dev-
> audio.c
> index 6347594..5add5fa 100644
> --- a/arch/arm/mach-exynos4/dev-audio.c
> +++ b/arch/arm/mach-exynos4/dev-audio.c
> @@ -335,7 +335,7 @@ struct platform_device exynos4_device_ac97 = {
> 
>  static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
>  {
> -	s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(3));
> +	s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4));
> 
>  	return 0;
>  }
> --

OK, will apply into s5p-fixes-for-linus branch with Jassi's ack.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH 3/5] ARM: EXYNOS4: fix improper gpio configuration

[Kukjin Kim]

Naveen Krishna Chatradhi wrote:
> 
> These pins are incorrectly configured for PCM2
> configure them to SPDIF(_OUT & _EXT_CLK)
> 
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
>  arch/arm/mach-exynos4/dev-audio.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos4/dev-audio.c
b/arch/arm/mach-exynos4/dev-
> audio.c
> index 6347594..5add5fa 100644
> --- a/arch/arm/mach-exynos4/dev-audio.c
> +++ b/arch/arm/mach-exynos4/dev-audio.c
> @@ -335,7 +335,7 @@ struct platform_device exynos4_device_ac97 = {
> 
>  static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
>  {
> -	s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(3));
> +	s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4));
> 
>  	return 0;
>  }
> --

OK, will apply into s5p-fixes-for-linus branch with Jassi's ack.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

Re: [PATCH 1/5] ARM: EXYNOS4: Add EPLL clock operations

[Naveen Krishna Ch]

Hi Kukjin,

On 14 June 2011 11:03, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Naveen Krishna Chatradhi wrote:
>>
>> This patch adds EPLL specific clock get_rate/set_rate
>> operations on EXYNOS4.
>>
>> Note: Initial code from S5PV210
>> http://permalink.gmane.org/gmane.linux.alsa.devel/77519
>>
>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>> ---
>>  arch/arm/mach-exynos4/clock.c |   78
>> +++++++++++++++++++++++++++++++++++++++++
>>  1 files changed, 78 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
>> index b1b93b9..7aa4aef 100644
>> --- a/arch/arm/mach-exynos4/clock.c
>> +++ b/arch/arm/mach-exynos4/clock.c
>> @@ -1276,6 +1276,82 @@ static struct clksrc_clk *sysclks[] = {
>>       &clk_sclk_audio2,
>>  };
>>
>> +static u32 epll_div[][6] = {
>> +     {  48000000, 0, 48, 3, 3, 0 },
>> +     {  96000000, 0, 48, 3, 2, 0 },
>> +     { 144000000, 1, 72, 3, 2, 0 },
>> +     { 192000000, 0, 48, 3, 1, 0 },
>> +     { 288000000, 1, 72, 3, 1, 0 },
>> +     {  32750000, 1, 65, 3, 4, 35127 },
>> +     {  32768000, 1, 65, 3, 4, 35127 },
>> +     {  45158400, 0, 45, 3, 3, 10355 },
>> +     {  45000000, 0, 45, 3, 3, 10355 },
>> +     {  45158000, 0, 45, 3, 3, 10355 },
>> +     {  49125000, 0, 49, 3, 3, 9961 },
>> +     {  49152000, 0, 49, 3, 3, 9961 },
>> +     {  67737600, 1, 67, 3, 3, 48366 },
>> +     {  67738000, 1, 67, 3, 3, 48366 },
>> +     {  73800000, 1, 73, 3, 3, 47710 },
>> +     {  73728000, 1, 73, 3, 3, 47710 },
>> +     {  36000000, 1, 32, 3, 4, 0 },
>> +     {  60000000, 1, 60, 3, 3, 0 },
>> +     {  72000000, 1, 72, 3, 3, 0 },
>> +     {  80000000, 1, 80, 3, 3, 0 },
>> +     {  84000000, 0, 42, 3, 2, 0 },
>> +     {  50000000, 0, 50, 3, 3, 0 },
>> +};
>> +
>> +static int exynos4_epll_set_rate(struct clk *clk, unsigned long rate)
>> +{
>> +     unsigned int epll_con, epll_con_k;
>> +     unsigned int i;
>> +
>> +     /* Return if nothing changed */
>> +     if (clk->rate == rate)
>> +             return 0;
>> +
>> +     epll_con = __raw_readl(S5P_EPLL_CON);
>> +     epll_con_k = __raw_readl(S5P_EPLL_CON1);
>> +
>> +     epll_con_k &= ~PLL46XX_KDIV_MASK;
>> +     epll_con &= ~(1 << 27 |
>> +                     PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
>> +                     PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
>> +                     PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
>> +
>> +     for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
>> +             if (epll_div[i][0] == rate) {
>> +                     epll_con_k |= epll_div[i][5] << 0;
>> +                     epll_con |= (epll_div[i][1] << 27 |
>> +                                     epll_div[i][2] <<
>> PLL46XX_MDIV_SHIFT |
>> +                                     epll_div[i][3] <<
>> PLL46XX_PDIV_SHIFT |
>> +                                     epll_div[i][4] <<
>> PLL46XX_SDIV_SHIFT);
>> +                     break;
>> +             }
>> +     }
>> +
>> +     if (i == ARRAY_SIZE(epll_div)) {
>> +             printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
>> +                             __func__);
>> +             return -EINVAL;
>> +     }
>> +
>> +     __raw_writel(epll_con, S5P_EPLL_CON);
>> +     __raw_writel(epll_con_k, S5P_EPLL_CON1);
>> +
>> +     printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
>> +                     clk->rate, rate);
>> +
>> +     clk->rate = rate;
>> +
>> +     return 0;
>> +}
>
> I think, this is same with S5PV210.
This is exactly similar to V210 as mentioned in the commit message.
>
> Would be better if this could be moved into plat-s5p/ with other set_pllXXX.
I'm preparing patch to move the epll_set_rate as common function
across s5p series.
Will send it soon.
>
>> +
>> +static struct clk_ops exynos4_epll_ops = {
>> +     .set_rate = exynos4_epll_set_rate,
>> +     .get_rate = s5p_epll_get_rate,
>> +};
>> +
>>  static int xtal_rate;
>>
>>  static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
>> @@ -1354,6 +1430,8 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
>>       for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
>>               s3c_set_clksrc(&clksrcs[ptr], true);
>>
>> +     clk_fout_epll.ops = &exynos4_epll_ops;
>> +
>>       clk_audiocdclk0.rate = PCM_EXTCLK0;
>>       clk_set_parent(&clk_sclk_audio0.clk, &clk_audiocdclk0);
>>  }
>> --
>
>
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>



-- 
Shine bright,
(: Nav :)

[PATCH 1/5] ARM: EXYNOS4: Add EPLL clock operations

[Naveen Krishna Ch]

Hi Kukjin,

On 14 June 2011 11:03, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Naveen Krishna Chatradhi wrote:
>>
>> This patch adds EPLL specific clock get_rate/set_rate
>> operations on EXYNOS4.
>>
>> Note: Initial code from S5PV210
>> http://permalink.gmane.org/gmane.linux.alsa.devel/77519
>>
>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>> ---
>> ?arch/arm/mach-exynos4/clock.c | ? 78
>> +++++++++++++++++++++++++++++++++++++++++
>> ?1 files changed, 78 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
>> index b1b93b9..7aa4aef 100644
>> --- a/arch/arm/mach-exynos4/clock.c
>> +++ b/arch/arm/mach-exynos4/clock.c
>> @@ -1276,6 +1276,82 @@ static struct clksrc_clk *sysclks[] = {
>> ? ? ? &clk_sclk_audio2,
>> ?};
>>
>> +static u32 epll_div[][6] = {
>> + ? ? { ?48000000, 0, 48, 3, 3, 0 },
>> + ? ? { ?96000000, 0, 48, 3, 2, 0 },
>> + ? ? { 144000000, 1, 72, 3, 2, 0 },
>> + ? ? { 192000000, 0, 48, 3, 1, 0 },
>> + ? ? { 288000000, 1, 72, 3, 1, 0 },
>> + ? ? { ?32750000, 1, 65, 3, 4, 35127 },
>> + ? ? { ?32768000, 1, 65, 3, 4, 35127 },
>> + ? ? { ?45158400, 0, 45, 3, 3, 10355 },
>> + ? ? { ?45000000, 0, 45, 3, 3, 10355 },
>> + ? ? { ?45158000, 0, 45, 3, 3, 10355 },
>> + ? ? { ?49125000, 0, 49, 3, 3, 9961 },
>> + ? ? { ?49152000, 0, 49, 3, 3, 9961 },
>> + ? ? { ?67737600, 1, 67, 3, 3, 48366 },
>> + ? ? { ?67738000, 1, 67, 3, 3, 48366 },
>> + ? ? { ?73800000, 1, 73, 3, 3, 47710 },
>> + ? ? { ?73728000, 1, 73, 3, 3, 47710 },
>> + ? ? { ?36000000, 1, 32, 3, 4, 0 },
>> + ? ? { ?60000000, 1, 60, 3, 3, 0 },
>> + ? ? { ?72000000, 1, 72, 3, 3, 0 },
>> + ? ? { ?80000000, 1, 80, 3, 3, 0 },
>> + ? ? { ?84000000, 0, 42, 3, 2, 0 },
>> + ? ? { ?50000000, 0, 50, 3, 3, 0 },
>> +};
>> +
>> +static int exynos4_epll_set_rate(struct clk *clk, unsigned long rate)
>> +{
>> + ? ? unsigned int epll_con, epll_con_k;
>> + ? ? unsigned int i;
>> +
>> + ? ? /* Return if nothing changed */
>> + ? ? if (clk->rate == rate)
>> + ? ? ? ? ? ? return 0;
>> +
>> + ? ? epll_con = __raw_readl(S5P_EPLL_CON);
>> + ? ? epll_con_k = __raw_readl(S5P_EPLL_CON1);
>> +
>> + ? ? epll_con_k &= ~PLL46XX_KDIV_MASK;
>> + ? ? epll_con &= ~(1 << 27 |
>> + ? ? ? ? ? ? ? ? ? ? PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
>> + ? ? ? ? ? ? ? ? ? ? PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
>> + ? ? ? ? ? ? ? ? ? ? PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
>> +
>> + ? ? for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
>> + ? ? ? ? ? ? if (epll_div[i][0] == rate) {
>> + ? ? ? ? ? ? ? ? ? ? epll_con_k |= epll_div[i][5] << 0;
>> + ? ? ? ? ? ? ? ? ? ? epll_con |= (epll_div[i][1] << 27 |
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? epll_div[i][2] <<
>> PLL46XX_MDIV_SHIFT |
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? epll_div[i][3] <<
>> PLL46XX_PDIV_SHIFT |
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? epll_div[i][4] <<
>> PLL46XX_SDIV_SHIFT);
>> + ? ? ? ? ? ? ? ? ? ? break;
>> + ? ? ? ? ? ? }
>> + ? ? }
>> +
>> + ? ? if (i == ARRAY_SIZE(epll_div)) {
>> + ? ? ? ? ? ? printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? __func__);
>> + ? ? ? ? ? ? return -EINVAL;
>> + ? ? }
>> +
>> + ? ? __raw_writel(epll_con, S5P_EPLL_CON);
>> + ? ? __raw_writel(epll_con_k, S5P_EPLL_CON1);
>> +
>> + ? ? printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
>> + ? ? ? ? ? ? ? ? ? ? clk->rate, rate);
>> +
>> + ? ? clk->rate = rate;
>> +
>> + ? ? return 0;
>> +}
>
> I think, this is same with S5PV210.
This is exactly similar to V210 as mentioned in the commit message.
>
> Would be better if this could be moved into plat-s5p/ with other set_pllXXX.
I'm preparing patch to move the epll_set_rate as common function
across s5p series.
Will send it soon.
>
>> +
>> +static struct clk_ops exynos4_epll_ops = {
>> + ? ? .set_rate = exynos4_epll_set_rate,
>> + ? ? .get_rate = s5p_epll_get_rate,
>> +};
>> +
>> ?static int xtal_rate;
>>
>> ?static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
>> @@ -1354,6 +1430,8 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
>> ? ? ? for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
>> ? ? ? ? ? ? ? s3c_set_clksrc(&clksrcs[ptr], true);
>>
>> + ? ? clk_fout_epll.ops = &exynos4_epll_ops;
>> +
>> ? ? ? clk_audiocdclk0.rate = PCM_EXTCLK0;
>> ? ? ? clk_set_parent(&clk_sclk_audio0.clk, &clk_audiocdclk0);
>> ?}
>> --
>
>
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>



-- 
Shine bright,
(: Nav :)

RE: [PATCH 4/5] ARM: EXYNOS4: Add SPDIF for SMDKV310

[Kukjin Kim]

Jassi Brar wrote:
> 
> On Fri, Jun 10, 2011 at 12:04 PM, Naveen Krishna Chatradhi
> <ch.naveen@samsung.com> wrote:
> > This patch adds spdif to the machine supported device list for
> > SMDKV310.
> >
> > Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> > ---
> >  arch/arm/mach-exynos4/mach-smdkv310.c |    1 +
> >  1 files changed, 1 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-
> exynos4/mach-smdkv310.c
> > index 7e3ee6c..966c6f2 100644
> > --- a/arch/arm/mach-exynos4/mach-smdkv310.c
> > +++ b/arch/arm/mach-exynos4/mach-smdkv310.c
> > @@ -190,6 +190,7 @@ static struct platform_device *smdkv310_devices[]
> __initdata = {
> >        &exynos4_device_pd[PD_CAM],
> >        &exynos4_device_pd[PD_TV],
> >        &exynos4_device_pd[PD_GPS],
> > +       &exynos4_device_spdif,
> >        &exynos4_device_sysmmu,
> >        &exynos4_device_pcm0,
> >        &samsung_asoc_dma,
> 
> Acked-by: Jassi Brar <jassisinghbrar@gmail.com>

Applied.
Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH 4/5] ARM: EXYNOS4: Add SPDIF for SMDKV310

[Kukjin Kim]

Jassi Brar wrote:
> 
> On Fri, Jun 10, 2011 at 12:04 PM, Naveen Krishna Chatradhi
> <ch.naveen@samsung.com> wrote:
> > This patch adds spdif to the machine supported device list for
> > SMDKV310.
> >
> > Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> > ---
> >  arch/arm/mach-exynos4/mach-smdkv310.c |    1 +
> >  1 files changed, 1 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-
> exynos4/mach-smdkv310.c
> > index 7e3ee6c..966c6f2 100644
> > --- a/arch/arm/mach-exynos4/mach-smdkv310.c
> > +++ b/arch/arm/mach-exynos4/mach-smdkv310.c
> > @@ -190,6 +190,7 @@ static struct platform_device *smdkv310_devices[]
> __initdata = {
> >        &exynos4_device_pd[PD_CAM],
> >        &exynos4_device_pd[PD_TV],
> >        &exynos4_device_pd[PD_GPS],
> > +       &exynos4_device_spdif,
> >        &exynos4_device_sysmmu,
> >        &exynos4_device_pcm0,
> >        &samsung_asoc_dma,
> 
> Acked-by: Jassi Brar <jassisinghbrar@gmail.com>

Applied.
Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.