* [PATCH 0/6] ARM: Exynos: Enable SPI platform support for Exynos4 and Exynos5
@ 2012-05-18 9:46 ` Thomas Abraham
0 siblings, 0 replies; 32+ messages in thread
From: Thomas Abraham @ 2012-05-18 9:46 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: linux-samsung-soc, kgene.kim, jaswinder.singh
This patch set enables device tree based platform support for the three spi
controllers on Samsung's Exynos4 and Exynos5 SoC's.
Thomas Abraham (6):
ARM: Exynos4: Fix the incorrect hierarchy of spi controller bus clock
ARM: Exynos5: Add spi clock support
ARM: Exynos4: Enable platform support for SPI controllers
ARM: Exynos5: Enable platform support for SPI controllers
ARM: dts: Add nodes for spi controllers for Samsung Exynos4 platforms
ARM: dts: Add nodes for spi controllers for Samsung Exynos5 platforms
arch/arm/boot/dts/exynos4210-origen.dts | 12 +++
arch/arm/boot/dts/exynos4210-smdkv310.dts | 44 +++++++++++
arch/arm/boot/dts/exynos4210.dtsi | 30 +++++++
arch/arm/boot/dts/exynos5250-smdk5250.dts | 47 +++++++++++-
arch/arm/boot/dts/exynos5250.dtsi | 46 +++++++++++
arch/arm/mach-exynos/Kconfig | 2 +
arch/arm/mach-exynos/clock-exynos4.c | 48 ++++++++++--
arch/arm/mach-exynos/clock-exynos5.c | 98 ++++++++++++++++++++++++
arch/arm/mach-exynos/include/mach/irqs.h | 4 +
arch/arm/mach-exynos/include/mach/map.h | 3 +
arch/arm/mach-exynos/include/mach/regs-clock.h | 4 +
arch/arm/mach-exynos/mach-exynos4-dt.c | 6 ++
arch/arm/mach-exynos/mach-exynos5-dt.c | 6 ++
13 files changed, 341 insertions(+), 9 deletions(-)
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 0/6] ARM: Exynos: Enable SPI platform support for Exynos4 and Exynos5
@ 2012-05-18 9:46 ` Thomas Abraham
0 siblings, 0 replies; 32+ messages in thread
From: Thomas Abraham @ 2012-05-18 9:46 UTC (permalink / raw)
To: linux-arm-kernel
This patch set enables device tree based platform support for the three spi
controllers on Samsung's Exynos4 and Exynos5 SoC's.
Thomas Abraham (6):
ARM: Exynos4: Fix the incorrect hierarchy of spi controller bus clock
ARM: Exynos5: Add spi clock support
ARM: Exynos4: Enable platform support for SPI controllers
ARM: Exynos5: Enable platform support for SPI controllers
ARM: dts: Add nodes for spi controllers for Samsung Exynos4 platforms
ARM: dts: Add nodes for spi controllers for Samsung Exynos5 platforms
arch/arm/boot/dts/exynos4210-origen.dts | 12 +++
arch/arm/boot/dts/exynos4210-smdkv310.dts | 44 +++++++++++
arch/arm/boot/dts/exynos4210.dtsi | 30 +++++++
arch/arm/boot/dts/exynos5250-smdk5250.dts | 47 +++++++++++-
arch/arm/boot/dts/exynos5250.dtsi | 46 +++++++++++
arch/arm/mach-exynos/Kconfig | 2 +
arch/arm/mach-exynos/clock-exynos4.c | 48 ++++++++++--
arch/arm/mach-exynos/clock-exynos5.c | 98 ++++++++++++++++++++++++
arch/arm/mach-exynos/include/mach/irqs.h | 4 +
arch/arm/mach-exynos/include/mach/map.h | 3 +
arch/arm/mach-exynos/include/mach/regs-clock.h | 4 +
arch/arm/mach-exynos/mach-exynos4-dt.c | 6 ++
arch/arm/mach-exynos/mach-exynos5-dt.c | 6 ++
13 files changed, 341 insertions(+), 9 deletions(-)
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 1/6] ARM: Exynos4: Fix the incorrect hierarchy of spi controller bus clock
2012-05-18 9:46 ` Thomas Abraham
@ 2012-05-18 9:46 ` Thomas Abraham
-1 siblings, 0 replies; 32+ messages in thread
From: Thomas Abraham @ 2012-05-18 9:46 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: linux-samsung-soc, kgene.kim, jaswinder.singh
The sclk_spi clock is derived currently from the first level divider
(MMCx_RATIO) which is incorrect. The output of the first level clock
is divided by a second level divider (MMCx_PRE_RATIO), the output of
which is used as the spi bus clock (sclk_spi). Fix the clock hierarchy
issues for the sclk_spi clock.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Jaswinder Singh <jaswinder.singh@linaro.org>
---
arch/arm/mach-exynos/clock-exynos4.c | 48 ++++++++++++++++++++++++++++-----
1 files changed, 40 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index 10a46a9..b5f0507 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -1242,40 +1242,70 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
};
+static struct clksrc_clk exynos4_clk_mdout_spi0 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.0",
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+
+};
+
static struct clksrc_clk exynos4_clk_sclk_spi0 = {
.clk = {
.name = "sclk_spi",
.devname = "exynos4210-spi.0",
+ .parent = &exynos4_clk_mdout_spi0.clk,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 16),
},
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_mdout_spi1 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.1",
+ },
.sources = &exynos4_clkset_group,
- .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
- .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+
};
static struct clksrc_clk exynos4_clk_sclk_spi1 = {
.clk = {
.name = "sclk_spi",
.devname = "exynos4210-spi.1",
+ .parent = &exynos4_clk_mdout_spi1.clk,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 20),
},
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_mdout_spi2 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.2",
+ },
.sources = &exynos4_clkset_group,
- .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
- .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+
};
static struct clksrc_clk exynos4_clk_sclk_spi2 = {
.clk = {
.name = "sclk_spi",
.devname = "exynos4210-spi.2",
+ .parent = &exynos4_clk_mdout_spi2.clk,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 24),
},
- .sources = &exynos4_clkset_group,
- .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
- .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
};
/* Clock initialization code */
@@ -1331,7 +1361,9 @@ static struct clksrc_clk *exynos4_clksrc_cdev[] = {
&exynos4_clk_sclk_spi0,
&exynos4_clk_sclk_spi1,
&exynos4_clk_sclk_spi2,
-
+ &exynos4_clk_mdout_spi0,
+ &exynos4_clk_mdout_spi1,
+ &exynos4_clk_mdout_spi2,
};
static struct clk_lookup exynos4_clk_lookup[] = {
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 1/6] ARM: Exynos4: Fix the incorrect hierarchy of spi controller bus clock
@ 2012-05-18 9:46 ` Thomas Abraham
0 siblings, 0 replies; 32+ messages in thread
From: Thomas Abraham @ 2012-05-18 9:46 UTC (permalink / raw)
To: linux-arm-kernel
The sclk_spi clock is derived currently from the first level divider
(MMCx_RATIO) which is incorrect. The output of the first level clock
is divided by a second level divider (MMCx_PRE_RATIO), the output of
which is used as the spi bus clock (sclk_spi). Fix the clock hierarchy
issues for the sclk_spi clock.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Jaswinder Singh <jaswinder.singh@linaro.org>
---
arch/arm/mach-exynos/clock-exynos4.c | 48 ++++++++++++++++++++++++++++-----
1 files changed, 40 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index 10a46a9..b5f0507 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -1242,40 +1242,70 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
};
+static struct clksrc_clk exynos4_clk_mdout_spi0 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.0",
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+
+};
+
static struct clksrc_clk exynos4_clk_sclk_spi0 = {
.clk = {
.name = "sclk_spi",
.devname = "exynos4210-spi.0",
+ .parent = &exynos4_clk_mdout_spi0.clk,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 16),
},
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_mdout_spi1 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.1",
+ },
.sources = &exynos4_clkset_group,
- .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
- .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+
};
static struct clksrc_clk exynos4_clk_sclk_spi1 = {
.clk = {
.name = "sclk_spi",
.devname = "exynos4210-spi.1",
+ .parent = &exynos4_clk_mdout_spi1.clk,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 20),
},
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_mdout_spi2 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.2",
+ },
.sources = &exynos4_clkset_group,
- .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
- .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+
};
static struct clksrc_clk exynos4_clk_sclk_spi2 = {
.clk = {
.name = "sclk_spi",
.devname = "exynos4210-spi.2",
+ .parent = &exynos4_clk_mdout_spi2.clk,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 24),
},
- .sources = &exynos4_clkset_group,
- .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
- .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
};
/* Clock initialization code */
@@ -1331,7 +1361,9 @@ static struct clksrc_clk *exynos4_clksrc_cdev[] = {
&exynos4_clk_sclk_spi0,
&exynos4_clk_sclk_spi1,
&exynos4_clk_sclk_spi2,
-
+ &exynos4_clk_mdout_spi0,
+ &exynos4_clk_mdout_spi1,
+ &exynos4_clk_mdout_spi2,
};
static struct clk_lookup exynos4_clk_lookup[] = {
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 2/6] ARM: Exynos5: Add spi clock support
2012-05-18 9:46 ` Thomas Abraham
@ 2012-05-18 9:46 ` Thomas Abraham
-1 siblings, 0 replies; 32+ messages in thread
From: Thomas Abraham @ 2012-05-18 9:46 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: linux-samsung-soc, kgene.kim, jaswinder.singh
Add support for clock instances for each spi controller.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Jaswinder Singh <jaswinder.singh@linaro.org>
---
arch/arm/mach-exynos/clock-exynos5.c | 98 ++++++++++++++++++++++++
arch/arm/mach-exynos/include/mach/regs-clock.h | 4 +
2 files changed, 102 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 5aa460b..ad6c959 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -82,6 +82,11 @@ static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
}
+static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
+}
+
static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
@@ -692,6 +697,24 @@ static struct clk exynos5_init_clocks_off[] = {
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 14),
}, {
+ .name = "spi",
+ .devname = "exynos4210-spi.0",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 16),
+ }, {
+ .name = "spi",
+ .devname = "exynos4210-spi.1",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 17),
+ }, {
+ .name = "spi",
+ .devname = "exynos4210-spi.2",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 18),
+ }, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
.enable = &exynos5_clk_ip_mfc_ctrl,
@@ -985,6 +1008,72 @@ static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
};
+static struct clksrc_clk exynos5_clk_mdout_spi0 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.0",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
+
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi0 = {
+ .clk = {
+ .name = "sclk_spi",
+ .devname = "exynos4210-spi.0",
+ .parent = &exynos5_clk_mdout_spi0.clk,
+ .enable = exynos5_clksrc_mask_peric1_ctrl,
+ .ctrlbit = (1 << 16),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_mdout_spi1 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.1",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
+
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi1 = {
+ .clk = {
+ .name = "sclk_spi",
+ .devname = "exynos4210-spi.1",
+ .parent = &exynos5_clk_mdout_spi1.clk,
+ .enable = exynos5_clksrc_mask_peric1_ctrl,
+ .ctrlbit = (1 << 20),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_mdout_spi2 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.2",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
+
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi2 = {
+ .clk = {
+ .name = "sclk_spi",
+ .devname = "exynos4210-spi.2",
+ .parent = &exynos5_clk_mdout_spi2.clk,
+ .enable = exynos5_clksrc_mask_peric1_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
+};
+
static struct clksrc_clk exynos5_clksrcs[] = {
{
.clk = {
@@ -1116,6 +1205,12 @@ static struct clksrc_clk *exynos5_clksrc_cdev[] = {
&exynos5_clk_sclk_mmc1,
&exynos5_clk_sclk_mmc2,
&exynos5_clk_sclk_mmc3,
+ &exynos5_clk_sclk_spi0,
+ &exynos5_clk_sclk_spi1,
+ &exynos5_clk_sclk_spi2,
+ &exynos5_clk_mdout_spi0,
+ &exynos5_clk_mdout_spi1,
+ &exynos5_clk_mdout_spi2,
};
static struct clk_lookup exynos5_clk_lookup[] = {
@@ -1127,6 +1222,9 @@ static struct clk_lookup exynos5_clk_lookup[] = {
CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
+ CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
+ CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
+ CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index b78b5f3..ca86aba 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -287,6 +287,7 @@
#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
+#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254)
#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
@@ -304,6 +305,9 @@
#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
+#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C)
+#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560)
+#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354)
#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800)
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 2/6] ARM: Exynos5: Add spi clock support
@ 2012-05-18 9:46 ` Thomas Abraham
0 siblings, 0 replies; 32+ messages in thread
From: Thomas Abraham @ 2012-05-18 9:46 UTC (permalink / raw)
To: linux-arm-kernel
Add support for clock instances for each spi controller.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Jaswinder Singh <jaswinder.singh@linaro.org>
---
arch/arm/mach-exynos/clock-exynos5.c | 98 ++++++++++++++++++++++++
arch/arm/mach-exynos/include/mach/regs-clock.h | 4 +
2 files changed, 102 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 5aa460b..ad6c959 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -82,6 +82,11 @@ static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
}
+static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
+}
+
static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
@@ -692,6 +697,24 @@ static struct clk exynos5_init_clocks_off[] = {
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 14),
}, {
+ .name = "spi",
+ .devname = "exynos4210-spi.0",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 16),
+ }, {
+ .name = "spi",
+ .devname = "exynos4210-spi.1",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 17),
+ }, {
+ .name = "spi",
+ .devname = "exynos4210-spi.2",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 18),
+ }, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
.enable = &exynos5_clk_ip_mfc_ctrl,
@@ -985,6 +1008,72 @@ static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
};
+static struct clksrc_clk exynos5_clk_mdout_spi0 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.0",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
+
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi0 = {
+ .clk = {
+ .name = "sclk_spi",
+ .devname = "exynos4210-spi.0",
+ .parent = &exynos5_clk_mdout_spi0.clk,
+ .enable = exynos5_clksrc_mask_peric1_ctrl,
+ .ctrlbit = (1 << 16),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_mdout_spi1 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.1",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
+
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi1 = {
+ .clk = {
+ .name = "sclk_spi",
+ .devname = "exynos4210-spi.1",
+ .parent = &exynos5_clk_mdout_spi1.clk,
+ .enable = exynos5_clksrc_mask_peric1_ctrl,
+ .ctrlbit = (1 << 20),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_mdout_spi2 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.2",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
+
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi2 = {
+ .clk = {
+ .name = "sclk_spi",
+ .devname = "exynos4210-spi.2",
+ .parent = &exynos5_clk_mdout_spi2.clk,
+ .enable = exynos5_clksrc_mask_peric1_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
+};
+
static struct clksrc_clk exynos5_clksrcs[] = {
{
.clk = {
@@ -1116,6 +1205,12 @@ static struct clksrc_clk *exynos5_clksrc_cdev[] = {
&exynos5_clk_sclk_mmc1,
&exynos5_clk_sclk_mmc2,
&exynos5_clk_sclk_mmc3,
+ &exynos5_clk_sclk_spi0,
+ &exynos5_clk_sclk_spi1,
+ &exynos5_clk_sclk_spi2,
+ &exynos5_clk_mdout_spi0,
+ &exynos5_clk_mdout_spi1,
+ &exynos5_clk_mdout_spi2,
};
static struct clk_lookup exynos5_clk_lookup[] = {
@@ -1127,6 +1222,9 @@ static struct clk_lookup exynos5_clk_lookup[] = {
CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
+ CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
+ CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
+ CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index b78b5f3..ca86aba 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -287,6 +287,7 @@
#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
+#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254)
#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
@@ -304,6 +305,9 @@
#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
+#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C)
+#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560)
+#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354)
#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800)
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 3/6] ARM: Exynos4: Enable platform support for SPI controllers
2012-05-18 9:46 ` Thomas Abraham
@ 2012-05-18 9:46 ` Thomas Abraham
-1 siblings, 0 replies; 32+ messages in thread
From: Thomas Abraham @ 2012-05-18 9:46 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: linux-samsung-soc, kgene.kim, jaswinder.singh
Add the platform bits which are required to support SPI controllers.
The OF based partition parsing is also enabled to allow usage of SPI
nor flash on smdkv310 board.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos/Kconfig | 1 +
arch/arm/mach-exynos/include/mach/irqs.h | 4 ++++
arch/arm/mach-exynos/mach-exynos4-dt.c | 6 ++++++
3 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 07f6346..9d07e3d 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -393,6 +393,7 @@ config MACH_EXYNOS4_DT
select USE_OF
select ARM_AMBA
select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
+ select MTD_OF_PARTS if (MTD && OF && SPI_S3C64XX)
help
Machine support for Samsung Exynos4 machine with device tree enabled.
Select this if a fdt blob is available for the Exynos4 SoC based board.
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 561553a..195773b 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -195,6 +195,10 @@
#define IRQ_IIC6 EXYNOS4_IRQ_IIC6
#define IRQ_IIC7 EXYNOS4_IRQ_IIC7
+#define IRQ_SPI0 EXYNOS4_IRQ_SPI0
+#define IRQ_SPI1 EXYNOS4_IRQ_SPI1
+#define IRQ_SPI2 EXYNOS4_IRQ_SPI2
+
#define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST
#define IRQ_HSMMC0 EXYNOS4_IRQ_HSMMC0
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 8245f1c..f63f0bb 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -55,6 +55,12 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
"exynos4-sdhci.3", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
"s3c2440-i2c.0", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0,
+ "exynos4210-spi.0", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1,
+ "exynos4210-spi.1", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2,
+ "exynos4210-spi.2", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
{},
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 3/6] ARM: Exynos4: Enable platform support for SPI controllers
@ 2012-05-18 9:46 ` Thomas Abraham
0 siblings, 0 replies; 32+ messages in thread
From: Thomas Abraham @ 2012-05-18 9:46 UTC (permalink / raw)
To: linux-arm-kernel
Add the platform bits which are required to support SPI controllers.
The OF based partition parsing is also enabled to allow usage of SPI
nor flash on smdkv310 board.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos/Kconfig | 1 +
arch/arm/mach-exynos/include/mach/irqs.h | 4 ++++
arch/arm/mach-exynos/mach-exynos4-dt.c | 6 ++++++
3 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 07f6346..9d07e3d 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -393,6 +393,7 @@ config MACH_EXYNOS4_DT
select USE_OF
select ARM_AMBA
select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
+ select MTD_OF_PARTS if (MTD && OF && SPI_S3C64XX)
help
Machine support for Samsung Exynos4 machine with device tree enabled.
Select this if a fdt blob is available for the Exynos4 SoC based board.
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 561553a..195773b 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -195,6 +195,10 @@
#define IRQ_IIC6 EXYNOS4_IRQ_IIC6
#define IRQ_IIC7 EXYNOS4_IRQ_IIC7
+#define IRQ_SPI0 EXYNOS4_IRQ_SPI0
+#define IRQ_SPI1 EXYNOS4_IRQ_SPI1
+#define IRQ_SPI2 EXYNOS4_IRQ_SPI2
+
#define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST
#define IRQ_HSMMC0 EXYNOS4_IRQ_HSMMC0
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 8245f1c..f63f0bb 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -55,6 +55,12 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
"exynos4-sdhci.3", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
"s3c2440-i2c.0", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0,
+ "exynos4210-spi.0", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1,
+ "exynos4210-spi.1", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2,
+ "exynos4210-spi.2", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
{},
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 4/6] ARM: Exynos5: Enable platform support for SPI controllers
2012-05-18 9:46 ` Thomas Abraham
@ 2012-05-18 9:46 ` Thomas Abraham
-1 siblings, 0 replies; 32+ messages in thread
From: Thomas Abraham @ 2012-05-18 9:46 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: linux-samsung-soc, kgene.kim, jaswinder.singh
Add the platform bits which are required to support SPI controllers.
The OF based partition parsing is also enabled to allow usage of SPI
nor flash on smdk5250 board.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos/Kconfig | 1 +
arch/arm/mach-exynos/include/mach/map.h | 3 +++
arch/arm/mach-exynos/mach-exynos5-dt.c | 6 ++++++
3 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 9d07e3d..c050f1d 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -406,6 +406,7 @@ config MACH_EXYNOS5_DT
select SOC_EXYNOS5250
select USE_OF
select ARM_AMBA
+ select MTD_OF_PARTS if (MTD && OF && SPI_S3C64XX)
help
Machine support for Samsung Exynos4 machine with device tree enabled.
Select this if a fdt blob is available for the EXYNOS4 SoC based board.
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c72f808..06fa583 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -154,6 +154,9 @@
#define EXYNOS4_PA_SPI0 0x13920000
#define EXYNOS4_PA_SPI1 0x13930000
#define EXYNOS4_PA_SPI2 0x13940000
+#define EXYNOS5_PA_SPI0 0x12D20000
+#define EXYNOS5_PA_SPI1 0x12D30000
+#define EXYNOS5_PA_SPI2 0x12D40000
#define EXYNOS4_PA_GPIO1 0x11400000
#define EXYNOS4_PA_GPIO2 0x11000000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index cf5d222..b63b0f0 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -47,6 +47,12 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
"s3c2440-i2c.0", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
"s3c2440-i2c.1", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
+ "exynos4210-spi.0", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
+ "exynos4210-spi.1", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
+ "exynos4210-spi.2", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 4/6] ARM: Exynos5: Enable platform support for SPI controllers
@ 2012-05-18 9:46 ` Thomas Abraham
0 siblings, 0 replies; 32+ messages in thread
From: Thomas Abraham @ 2012-05-18 9:46 UTC (permalink / raw)
To: linux-arm-kernel
Add the platform bits which are required to support SPI controllers.
The OF based partition parsing is also enabled to allow usage of SPI
nor flash on smdk5250 board.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos/Kconfig | 1 +
arch/arm/mach-exynos/include/mach/map.h | 3 +++
arch/arm/mach-exynos/mach-exynos5-dt.c | 6 ++++++
3 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 9d07e3d..c050f1d 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -406,6 +406,7 @@ config MACH_EXYNOS5_DT
select SOC_EXYNOS5250
select USE_OF
select ARM_AMBA
+ select MTD_OF_PARTS if (MTD && OF && SPI_S3C64XX)
help
Machine support for Samsung Exynos4 machine with device tree enabled.
Select this if a fdt blob is available for the EXYNOS4 SoC based board.
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c72f808..06fa583 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -154,6 +154,9 @@
#define EXYNOS4_PA_SPI0 0x13920000
#define EXYNOS4_PA_SPI1 0x13930000
#define EXYNOS4_PA_SPI2 0x13940000
+#define EXYNOS5_PA_SPI0 0x12D20000
+#define EXYNOS5_PA_SPI1 0x12D30000
+#define EXYNOS5_PA_SPI2 0x12D40000
#define EXYNOS4_PA_GPIO1 0x11400000
#define EXYNOS4_PA_GPIO2 0x11000000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index cf5d222..b63b0f0 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -47,6 +47,12 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
"s3c2440-i2c.0", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
"s3c2440-i2c.1", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
+ "exynos4210-spi.0", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
+ "exynos4210-spi.1", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
+ "exynos4210-spi.2", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 5/6] ARM: dts: Add nodes for spi controllers for Samsung Exynos4 platforms
2012-05-18 9:46 ` Thomas Abraham
@ 2012-05-18 9:46 ` Thomas Abraham
-1 siblings, 0 replies; 32+ messages in thread
From: Thomas Abraham @ 2012-05-18 9:46 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: linux-samsung-soc, kgene.kim, jaswinder.singh
Add device nodes for the three instances of spi controllers in Exynos4
platforms. Enable instance spi 2 for smdkv310 board and disable all
spi instances for origen board.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/boot/dts/exynos4210-origen.dts | 12 ++++++++
arch/arm/boot/dts/exynos4210-smdkv310.dts | 44 +++++++++++++++++++++++++++++
arch/arm/boot/dts/exynos4210.dtsi | 30 +++++++++++++++++++
3 files changed, 86 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index b8c4763..f27d367 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -134,4 +134,16 @@
i2c@138D0000 {
status = "disabled";
};
+
+ spi_0: spi@13920000 {
+ status = "disabled";
+ };
+
+ spi_1: spi@13930000 {
+ status = "disabled";
+ };
+
+ spi_2: spi@13940000 {
+ status = "disabled";
+ };
};
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 27afc8e..411ac8e 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -21,6 +21,12 @@
model = "Samsung smdkv310 evaluation board based on Exynos4210";
compatible = "samsung,smdkv310", "samsung,exynos4210";
+ aliases {
+ spi0 = &spi_0;
+ spi1 = &spi_1;
+ spi2 = &spi_2;
+ };
+
memory {
reg = <0x40000000 0x80000000>;
};
@@ -42,6 +48,36 @@
<&gpk2 6 2 3 3>;
};
+ spi_2: spi@13940000 {
+ gpios = <&gpc1 1 5 3 0>,
+ <&gpc1 3 5 3 0>,
+ <&gpc1 4 5 3 0>;
+
+ w25x80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "w25x80";
+ reg = <0>;
+ spi-max-frequency = <10000>;
+
+ controller-data {
+ cs-gpio = <&gpc1 2 1 0 3>;
+ samsung,spi-feedback-delay = <0>;
+ };
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+
+ partition@40000 {
+ label = "Kernel";
+ reg = <0x40000 0xc0000>;
+ };
+ };
+ };
+
keypad@100A0000 {
samsung,keypad-num-rows = <2>;
samsung,keypad-num-columns = <8>;
@@ -179,4 +215,12 @@
i2c@138D0000 {
status = "disabled";
};
+
+ spi_0: spi@13920000 {
+ status = "disabled";
+ };
+
+ spi_1: spi@13930000 {
+ status = "disabled";
+ };
};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index a1dd2ee..f107c5d 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -147,6 +147,36 @@
interrupts = <0 65 0>;
};
+ spi_0: spi@13920000 {
+ compatible = "samsung,exynos4210-spi";
+ reg = <0x13920000 0x100>;
+ interrupts = <0 66 0>;
+ tx-dma-channel = <&pdma0 7>;
+ rx-dma-channel = <&pdma0 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi_1: spi@13930000 {
+ compatible = "samsung,exynos4210-spi";
+ reg = <0x13930000 0x100>;
+ interrupts = <0 67 0>;
+ tx-dma-channel = <&pdma1 7>;
+ rx-dma-channel = <&pdma1 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi_2: spi@13940000 {
+ compatible = "samsung,exynos4210-spi";
+ reg = <0x13940000 0x100>;
+ interrupts = <0 68 0>;
+ tx-dma-channel = <&pdma0 9>;
+ rx-dma-channel = <&pdma0 8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
amba {
#address-cells = <1>;
#size-cells = <1>;
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 5/6] ARM: dts: Add nodes for spi controllers for Samsung Exynos4 platforms
@ 2012-05-18 9:46 ` Thomas Abraham
0 siblings, 0 replies; 32+ messages in thread
From: Thomas Abraham @ 2012-05-18 9:46 UTC (permalink / raw)
To: linux-arm-kernel
Add device nodes for the three instances of spi controllers in Exynos4
platforms. Enable instance spi 2 for smdkv310 board and disable all
spi instances for origen board.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/boot/dts/exynos4210-origen.dts | 12 ++++++++
arch/arm/boot/dts/exynos4210-smdkv310.dts | 44 +++++++++++++++++++++++++++++
arch/arm/boot/dts/exynos4210.dtsi | 30 +++++++++++++++++++
3 files changed, 86 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index b8c4763..f27d367 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -134,4 +134,16 @@
i2c at 138D0000 {
status = "disabled";
};
+
+ spi_0: spi at 13920000 {
+ status = "disabled";
+ };
+
+ spi_1: spi at 13930000 {
+ status = "disabled";
+ };
+
+ spi_2: spi at 13940000 {
+ status = "disabled";
+ };
};
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 27afc8e..411ac8e 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -21,6 +21,12 @@
model = "Samsung smdkv310 evaluation board based on Exynos4210";
compatible = "samsung,smdkv310", "samsung,exynos4210";
+ aliases {
+ spi0 = &spi_0;
+ spi1 = &spi_1;
+ spi2 = &spi_2;
+ };
+
memory {
reg = <0x40000000 0x80000000>;
};
@@ -42,6 +48,36 @@
<&gpk2 6 2 3 3>;
};
+ spi_2: spi at 13940000 {
+ gpios = <&gpc1 1 5 3 0>,
+ <&gpc1 3 5 3 0>,
+ <&gpc1 4 5 3 0>;
+
+ w25x80 at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "w25x80";
+ reg = <0>;
+ spi-max-frequency = <10000>;
+
+ controller-data {
+ cs-gpio = <&gpc1 2 1 0 3>;
+ samsung,spi-feedback-delay = <0>;
+ };
+
+ partition at 0 {
+ label = "U-Boot";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+
+ partition at 40000 {
+ label = "Kernel";
+ reg = <0x40000 0xc0000>;
+ };
+ };
+ };
+
keypad at 100A0000 {
samsung,keypad-num-rows = <2>;
samsung,keypad-num-columns = <8>;
@@ -179,4 +215,12 @@
i2c at 138D0000 {
status = "disabled";
};
+
+ spi_0: spi at 13920000 {
+ status = "disabled";
+ };
+
+ spi_1: spi at 13930000 {
+ status = "disabled";
+ };
};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index a1dd2ee..f107c5d 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -147,6 +147,36 @@
interrupts = <0 65 0>;
};
+ spi_0: spi at 13920000 {
+ compatible = "samsung,exynos4210-spi";
+ reg = <0x13920000 0x100>;
+ interrupts = <0 66 0>;
+ tx-dma-channel = <&pdma0 7>;
+ rx-dma-channel = <&pdma0 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi_1: spi at 13930000 {
+ compatible = "samsung,exynos4210-spi";
+ reg = <0x13930000 0x100>;
+ interrupts = <0 67 0>;
+ tx-dma-channel = <&pdma1 7>;
+ rx-dma-channel = <&pdma1 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi_2: spi at 13940000 {
+ compatible = "samsung,exynos4210-spi";
+ reg = <0x13940000 0x100>;
+ interrupts = <0 68 0>;
+ tx-dma-channel = <&pdma0 9>;
+ rx-dma-channel = <&pdma0 8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
amba {
#address-cells = <1>;
#size-cells = <1>;
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 6/6] ARM: dts: Add nodes for spi controllers for Samsung Exynos5 platforms
2012-05-18 9:46 ` Thomas Abraham
@ 2012-05-18 9:46 ` Thomas Abraham
-1 siblings, 0 replies; 32+ messages in thread
From: Thomas Abraham @ 2012-05-18 9:46 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: linux-samsung-soc, kgene.kim, jaswinder.singh
Add device nodes for the three instances of spi controllers in Exynos5
platforms and enable instance spi 1 for smdk5250 board.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 47 ++++++++++++++++++++++++++++-
arch/arm/boot/dts/exynos5250.dtsi | 46 ++++++++++++++++++++++++++++
2 files changed, 92 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 49945cc..dca572d 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -16,12 +16,18 @@
model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
compatible = "samsung,smdk5250", "samsung,exynos5250";
+ aliases {
+ spi0 = &spi_0;
+ spi1 = &spi_1;
+ spi2 = &spi_2;
+ };
+
memory {
reg = <0x40000000 0x80000000>;
};
chosen {
- bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
+ bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
};
i2c@12C60000 {
@@ -48,6 +54,45 @@
};
};
+
+ spi_1: spi@12d30000 {
+ gpios = <&gpa2 4 2 3 0>,
+ <&gpa2 6 2 3 0>,
+ <&gpa2 7 2 3 0>;
+
+ w25q80bw@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "w25x80";
+ reg = <0>;
+ spi-max-frequency = <10000>;
+
+ controller-data {
+ cs-gpio = <&gpa2 5 1 0 3>;
+ samsung,spi-feedback-delay = <0>;
+ };
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+
+ partition@40000 {
+ label = "Kernel";
+ reg = <0x40000 0xc0000>;
+ };
+ };
+ };
+
+ spi_0: spi@12d20000 {
+ status = "disabled";
+ };
+
+ spi_2: spi@12d40000 {
+ status = "disabled";
+ };
+
i2c@12C80000 {
status = "disabled";
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 5ca0cdb..9d7add0 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -30,6 +30,22 @@
reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
};
+ combiner:interrupt-controller@10440000 {
+ compatible = "samsung,exynos4210-combiner";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ samsung,combiner-nr = <32>;
+ reg = <0x10440000 0x1000>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+ <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+ <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+ <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+ <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+ <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+ <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+ };
+
watchdog {
compatible = "samsung,s3c2410-wdt";
reg = <0x101D0000 0x100>;
@@ -130,6 +146,36 @@
#size-cells = <0>;
};
+ spi_0: spi@12d20000 {
+ compatible = "samsung,exynos4210-spi";
+ reg = <0x12d20000 0x100>;
+ interrupts = <0 66 0>;
+ tx-dma-channel = <&pdma0 5>;
+ rx-dma-channel = <&pdma0 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi_1: spi@12d30000 {
+ compatible = "samsung,exynos4210-spi";
+ reg = <0x12d30000 0x100>;
+ interrupts = <0 67 0>;
+ tx-dma-channel = <&pdma1 5>;
+ rx-dma-channel = <&pdma1 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi_2: spi@12d40000 {
+ compatible = "samsung,exynos4210-spi";
+ reg = <0x12d40000 0x100>;
+ interrupts = <0 68 0>;
+ tx-dma-channel = <&pdma0 7>;
+ rx-dma-channel = <&pdma0 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
amba {
#address-cells = <1>;
#size-cells = <1>;
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 6/6] ARM: dts: Add nodes for spi controllers for Samsung Exynos5 platforms
@ 2012-05-18 9:46 ` Thomas Abraham
0 siblings, 0 replies; 32+ messages in thread
From: Thomas Abraham @ 2012-05-18 9:46 UTC (permalink / raw)
To: linux-arm-kernel
Add device nodes for the three instances of spi controllers in Exynos5
platforms and enable instance spi 1 for smdk5250 board.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 47 ++++++++++++++++++++++++++++-
arch/arm/boot/dts/exynos5250.dtsi | 46 ++++++++++++++++++++++++++++
2 files changed, 92 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 49945cc..dca572d 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -16,12 +16,18 @@
model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
compatible = "samsung,smdk5250", "samsung,exynos5250";
+ aliases {
+ spi0 = &spi_0;
+ spi1 = &spi_1;
+ spi2 = &spi_2;
+ };
+
memory {
reg = <0x40000000 0x80000000>;
};
chosen {
- bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
+ bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
};
i2c at 12C60000 {
@@ -48,6 +54,45 @@
};
};
+
+ spi_1: spi at 12d30000 {
+ gpios = <&gpa2 4 2 3 0>,
+ <&gpa2 6 2 3 0>,
+ <&gpa2 7 2 3 0>;
+
+ w25q80bw at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "w25x80";
+ reg = <0>;
+ spi-max-frequency = <10000>;
+
+ controller-data {
+ cs-gpio = <&gpa2 5 1 0 3>;
+ samsung,spi-feedback-delay = <0>;
+ };
+
+ partition at 0 {
+ label = "U-Boot";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+
+ partition at 40000 {
+ label = "Kernel";
+ reg = <0x40000 0xc0000>;
+ };
+ };
+ };
+
+ spi_0: spi at 12d20000 {
+ status = "disabled";
+ };
+
+ spi_2: spi at 12d40000 {
+ status = "disabled";
+ };
+
i2c at 12C80000 {
status = "disabled";
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 5ca0cdb..9d7add0 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -30,6 +30,22 @@
reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
};
+ combiner:interrupt-controller at 10440000 {
+ compatible = "samsung,exynos4210-combiner";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ samsung,combiner-nr = <32>;
+ reg = <0x10440000 0x1000>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+ <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+ <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+ <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+ <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+ <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+ <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+ };
+
watchdog {
compatible = "samsung,s3c2410-wdt";
reg = <0x101D0000 0x100>;
@@ -130,6 +146,36 @@
#size-cells = <0>;
};
+ spi_0: spi at 12d20000 {
+ compatible = "samsung,exynos4210-spi";
+ reg = <0x12d20000 0x100>;
+ interrupts = <0 66 0>;
+ tx-dma-channel = <&pdma0 5>;
+ rx-dma-channel = <&pdma0 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi_1: spi at 12d30000 {
+ compatible = "samsung,exynos4210-spi";
+ reg = <0x12d30000 0x100>;
+ interrupts = <0 67 0>;
+ tx-dma-channel = <&pdma1 5>;
+ rx-dma-channel = <&pdma1 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi_2: spi at 12d40000 {
+ compatible = "samsung,exynos4210-spi";
+ reg = <0x12d40000 0x100>;
+ interrupts = <0 68 0>;
+ tx-dma-channel = <&pdma0 7>;
+ rx-dma-channel = <&pdma0 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
amba {
#address-cells = <1>;
#size-cells = <1>;
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH 6/6] ARM: dts: Add nodes for spi controllers for Samsung Exynos5 platforms
2012-05-18 9:46 ` Thomas Abraham
@ 2012-05-23 9:50 ` padma venkat
-1 siblings, 0 replies; 32+ messages in thread
From: padma venkat @ 2012-05-23 9:50 UTC (permalink / raw)
To: Thomas Abraham
Cc: kgene.kim, linux-samsung-soc, linux-arm-kernel, jaswinder.singh
[-- Attachment #1.1: Type: text/plain, Size: 5777 bytes --]
Hi Thomas,
On Fri, May 18, 2012 at 3:16 PM, Thomas Abraham
<thomas.abraham@linaro.org>wrote:
> Add device nodes for the three instances of spi controllers in Exynos5
> platforms and enable instance spi 1 for smdk5250 board.
>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> ---
> arch/arm/boot/dts/exynos5250-smdk5250.dts | 47
> ++++++++++++++++++++++++++++-
> arch/arm/boot/dts/exynos5250.dtsi | 46
> ++++++++++++++++++++++++++++
> 2 files changed, 92 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> index 49945cc..dca572d 100644
> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> @@ -16,12 +16,18 @@
> model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
> compatible = "samsung,smdk5250", "samsung,exynos5250";
>
> + aliases {
> + spi0 = &spi_0;
> + spi1 = &spi_1;
> + spi2 = &spi_2;
> + };
> +
> memory {
> reg = <0x40000000 0x80000000>;
> };
>
> chosen {
> - bootargs = "root=/dev/ram0 rw ramdisk=8192
> console=ttySAC1,115200";
> + bootargs ="root=/dev/ram0 rw ramdisk=8192
> initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
> };
>
> i2c@12C60000 {
> @@ -48,6 +54,45 @@
> };
> };
>
> +
> + spi_1: spi@12d30000 {
> + gpios = <&gpa2 4 2 3 0>,
> + <&gpa2 6 2 3 0>,
> + <&gpa2 7 2 3 0>;
> +
> + w25q80bw@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "w25x80";
> + reg = <0>;
> + spi-max-frequency = <10000>;
> +
> + controller-data {
> + cs-gpio = <&gpa2 5 1 0 3>;
> + samsung,spi-feedback-delay = <0>;
> + };
> +
> + partition@0 {
> + label = "U-Boot";
> + reg = <0x0 0x40000>;
> + read-only;
> + };
> +
> + partition@40000 {
> + label = "Kernel";
> + reg = <0x40000 0xc0000>;
> + };
> + };
> + };
> +
> + spi_0: spi@12d20000 {
> + status = "disabled";
> + };
> +
> + spi_2: spi@12d40000 {
> + status = "disabled";
> + };
> +
> i2c@12C80000 {
> status = "disabled";
> };
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi
> b/arch/arm/boot/dts/exynos5250.dtsi
> index 5ca0cdb..9d7add0 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -30,6 +30,22 @@
> reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
> };
>
> + combiner:interrupt-controller@10440000 {
> + compatible = "samsung,exynos4210-combiner";
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + samsung,combiner-nr = <32>;
> + reg = <0x10440000 0x1000>;
> + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
> + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
> + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
> + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
> + <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
> + <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
> + <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
> + <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
> + };
> +
>
The combiner interrupt controller support is already present in the
following patch.
ARM: Exynos5: Add combiner, wakeup interrupt controller and
ethernet nodes
This code can be removed from this patch.
Thanks&Regards
Padma
> watchdog {
> compatible = "samsung,s3c2410-wdt";
> reg = <0x101D0000 0x100>;
> @@ -130,6 +146,36 @@
> #size-cells = <0>;
> };
>
> + spi_0: spi@12d20000 {
> + compatible = "samsung,exynos4210-spi";
> + reg = <0x12d20000 0x100>;
> + interrupts = <0 66 0>;
> + tx-dma-channel = <&pdma0 5>;
> + rx-dma-channel = <&pdma0 4>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + spi_1: spi@12d30000 {
> + compatible = "samsung,exynos4210-spi";
> + reg = <0x12d30000 0x100>;
> + interrupts = <0 67 0>;
> + tx-dma-channel = <&pdma1 5>;
> + rx-dma-channel = <&pdma1 4>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + spi_2: spi@12d40000 {
> + compatible = "samsung,exynos4210-spi";
> + reg = <0x12d40000 0x100>;
> + interrupts = <0 68 0>;
> + tx-dma-channel = <&pdma0 7>;
> + rx-dma-channel = <&pdma0 6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> amba {
> #address-cells = <1>;
> #size-cells = <1>;
> --
> 1.6.6.rc2
>
> --
> To unsubscribe from this list: send the line "unsubscribe
> linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
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^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 6/6] ARM: dts: Add nodes for spi controllers for Samsung Exynos5 platforms
@ 2012-05-23 9:50 ` padma venkat
0 siblings, 0 replies; 32+ messages in thread
From: padma venkat @ 2012-05-23 9:50 UTC (permalink / raw)
To: linux-arm-kernel
Hi Thomas,
On Fri, May 18, 2012 at 3:16 PM, Thomas Abraham
<thomas.abraham@linaro.org>wrote:
> Add device nodes for the three instances of spi controllers in Exynos5
> platforms and enable instance spi 1 for smdk5250 board.
>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> ---
> arch/arm/boot/dts/exynos5250-smdk5250.dts | 47
> ++++++++++++++++++++++++++++-
> arch/arm/boot/dts/exynos5250.dtsi | 46
> ++++++++++++++++++++++++++++
> 2 files changed, 92 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> index 49945cc..dca572d 100644
> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> @@ -16,12 +16,18 @@
> model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
> compatible = "samsung,smdk5250", "samsung,exynos5250";
>
> + aliases {
> + spi0 = &spi_0;
> + spi1 = &spi_1;
> + spi2 = &spi_2;
> + };
> +
> memory {
> reg = <0x40000000 0x80000000>;
> };
>
> chosen {
> - bootargs = "root=/dev/ram0 rw ramdisk=8192
> console=ttySAC1,115200";
> + bootargs ="root=/dev/ram0 rw ramdisk=8192
> initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
> };
>
> i2c at 12C60000 {
> @@ -48,6 +54,45 @@
> };
> };
>
> +
> + spi_1: spi at 12d30000 {
> + gpios = <&gpa2 4 2 3 0>,
> + <&gpa2 6 2 3 0>,
> + <&gpa2 7 2 3 0>;
> +
> + w25q80bw at 0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "w25x80";
> + reg = <0>;
> + spi-max-frequency = <10000>;
> +
> + controller-data {
> + cs-gpio = <&gpa2 5 1 0 3>;
> + samsung,spi-feedback-delay = <0>;
> + };
> +
> + partition at 0 {
> + label = "U-Boot";
> + reg = <0x0 0x40000>;
> + read-only;
> + };
> +
> + partition at 40000 {
> + label = "Kernel";
> + reg = <0x40000 0xc0000>;
> + };
> + };
> + };
> +
> + spi_0: spi at 12d20000 {
> + status = "disabled";
> + };
> +
> + spi_2: spi at 12d40000 {
> + status = "disabled";
> + };
> +
> i2c at 12C80000 {
> status = "disabled";
> };
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi
> b/arch/arm/boot/dts/exynos5250.dtsi
> index 5ca0cdb..9d7add0 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -30,6 +30,22 @@
> reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
> };
>
> + combiner:interrupt-controller at 10440000 {
> + compatible = "samsung,exynos4210-combiner";
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + samsung,combiner-nr = <32>;
> + reg = <0x10440000 0x1000>;
> + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
> + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
> + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
> + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
> + <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
> + <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
> + <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
> + <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
> + };
> +
>
The combiner interrupt controller support is already present in the
following patch.
ARM: Exynos5: Add combiner, wakeup interrupt controller and
ethernet nodes
This code can be removed from this patch.
Thanks&Regards
Padma
> watchdog {
> compatible = "samsung,s3c2410-wdt";
> reg = <0x101D0000 0x100>;
> @@ -130,6 +146,36 @@
> #size-cells = <0>;
> };
>
> + spi_0: spi at 12d20000 {
> + compatible = "samsung,exynos4210-spi";
> + reg = <0x12d20000 0x100>;
> + interrupts = <0 66 0>;
> + tx-dma-channel = <&pdma0 5>;
> + rx-dma-channel = <&pdma0 4>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + spi_1: spi at 12d30000 {
> + compatible = "samsung,exynos4210-spi";
> + reg = <0x12d30000 0x100>;
> + interrupts = <0 67 0>;
> + tx-dma-channel = <&pdma1 5>;
> + rx-dma-channel = <&pdma1 4>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + spi_2: spi at 12d40000 {
> + compatible = "samsung,exynos4210-spi";
> + reg = <0x12d40000 0x100>;
> + interrupts = <0 68 0>;
> + tx-dma-channel = <&pdma0 7>;
> + rx-dma-channel = <&pdma0 6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> amba {
> #address-cells = <1>;
> #size-cells = <1>;
> --
> 1.6.6.rc2
>
> --
> To unsubscribe from this list: send the line "unsubscribe
> linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
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^ permalink raw reply [flat|nested] 32+ messages in thread
* RE: [PATCH 1/6] ARM: Exynos4: Fix the incorrect hierarchy of spi controller bus clock
2012-05-18 9:46 ` Thomas Abraham
@ 2012-05-24 7:27 ` Kukjin Kim
-1 siblings, 0 replies; 32+ messages in thread
From: Kukjin Kim @ 2012-05-24 7:27 UTC (permalink / raw)
To: 'Thomas Abraham', linux-arm-kernel
Cc: linux-samsung-soc, jaswinder.singh
Thomas Abraham wrote:
>
> The sclk_spi clock is derived currently from the first level divider
> (MMCx_RATIO) which is incorrect. The output of the first level clock
> is divided by a second level divider (MMCx_PRE_RATIO), the output of
> which is used as the spi bus clock (sclk_spi). Fix the clock hierarchy
> issues for the sclk_spi clock.
>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> Acked-by: Jaswinder Singh <jaswinder.singh@linaro.org>
> ---
> arch/arm/mach-exynos/clock-exynos4.c | 48
++++++++++++++++++++++++++++--
> ---
> 1 files changed, 40 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-
> exynos/clock-exynos4.c
> index 10a46a9..b5f0507 100644
> --- a/arch/arm/mach-exynos/clock-exynos4.c
> +++ b/arch/arm/mach-exynos/clock-exynos4.c
> @@ -1242,40 +1242,70 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
> .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
> };
>
> +static struct clksrc_clk exynos4_clk_mdout_spi0 = {
In this case, it's expected that 'exynos4_clk_dout_spi0' will be used even
though this indicates the clock of mux_out and divider_out together.
> + .clk = {
> + .name = "sclk_spi_mdout",
So, this should be 'dout_spi0'
> + .devname = "exynos4210-spi.0",
[...]
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 1/6] ARM: Exynos4: Fix the incorrect hierarchy of spi controller bus clock
@ 2012-05-24 7:27 ` Kukjin Kim
0 siblings, 0 replies; 32+ messages in thread
From: Kukjin Kim @ 2012-05-24 7:27 UTC (permalink / raw)
To: linux-arm-kernel
Thomas Abraham wrote:
>
> The sclk_spi clock is derived currently from the first level divider
> (MMCx_RATIO) which is incorrect. The output of the first level clock
> is divided by a second level divider (MMCx_PRE_RATIO), the output of
> which is used as the spi bus clock (sclk_spi). Fix the clock hierarchy
> issues for the sclk_spi clock.
>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> Acked-by: Jaswinder Singh <jaswinder.singh@linaro.org>
> ---
> arch/arm/mach-exynos/clock-exynos4.c | 48
++++++++++++++++++++++++++++--
> ---
> 1 files changed, 40 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-
> exynos/clock-exynos4.c
> index 10a46a9..b5f0507 100644
> --- a/arch/arm/mach-exynos/clock-exynos4.c
> +++ b/arch/arm/mach-exynos/clock-exynos4.c
> @@ -1242,40 +1242,70 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
> .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
> };
>
> +static struct clksrc_clk exynos4_clk_mdout_spi0 = {
In this case, it's expected that 'exynos4_clk_dout_spi0' will be used even
though this indicates the clock of mux_out and divider_out together.
> + .clk = {
> + .name = "sclk_spi_mdout",
So, this should be 'dout_spi0'
> + .devname = "exynos4210-spi.0",
[...]
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 32+ messages in thread
* RE: [PATCH 2/6] ARM: Exynos5: Add spi clock support
2012-05-18 9:46 ` Thomas Abraham
@ 2012-05-24 7:30 ` Kukjin Kim
-1 siblings, 0 replies; 32+ messages in thread
From: Kukjin Kim @ 2012-05-24 7:30 UTC (permalink / raw)
To: 'Thomas Abraham', linux-arm-kernel
Cc: linux-samsung-soc, jaswinder.singh, 'Kyoungil Kim'
Thomas Abraham wrote:
>
> Add support for clock instances for each spi controller.
>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> Acked-by: Jaswinder Singh <jaswinder.singh@linaro.org>
> ---
> arch/arm/mach-exynos/clock-exynos5.c | 98
> ++++++++++++++++++++++++
> arch/arm/mach-exynos/include/mach/regs-clock.h | 4 +
> 2 files changed, 102 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-
> exynos/clock-exynos5.c
> index 5aa460b..ad6c959 100644
> --- a/arch/arm/mach-exynos/clock-exynos5.c
> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> @@ -82,6 +82,11 @@ static int exynos5_clksrc_mask_peric0_ctrl(struct clk
> *clk, int enable)
> return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
> }
>
> +static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
> +{
> + return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
> +}
> +
> static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
> {
> return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
> @@ -692,6 +697,24 @@ static struct clk exynos5_init_clocks_off[] = {
> .enable = exynos5_clk_ip_peric_ctrl,
> .ctrlbit = (1 << 14),
> }, {
> + .name = "spi",
> + .devname = "exynos4210-spi.0",
> + .parent = &exynos5_clk_aclk_66.clk,
> + .enable = exynos5_clk_ip_peric_ctrl,
> + .ctrlbit = (1 << 16),
> + }, {
> + .name = "spi",
> + .devname = "exynos4210-spi.1",
> + .parent = &exynos5_clk_aclk_66.clk,
> + .enable = exynos5_clk_ip_peric_ctrl,
> + .ctrlbit = (1 << 17),
> + }, {
> + .name = "spi",
> + .devname = "exynos4210-spi.2",
> + .parent = &exynos5_clk_aclk_66.clk,
> + .enable = exynos5_clk_ip_peric_ctrl,
> + .ctrlbit = (1 << 18),
> + }, {
> .name = SYSMMU_CLOCK_NAME,
> .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
> .enable = &exynos5_clk_ip_mfc_ctrl,
> @@ -985,6 +1008,72 @@ static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
> .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
> };
>
> +static struct clksrc_clk exynos5_clk_mdout_spi0 = {
See the previous comments and below url.
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/083153.h
tml
[...]
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 2/6] ARM: Exynos5: Add spi clock support
@ 2012-05-24 7:30 ` Kukjin Kim
0 siblings, 0 replies; 32+ messages in thread
From: Kukjin Kim @ 2012-05-24 7:30 UTC (permalink / raw)
To: linux-arm-kernel
Thomas Abraham wrote:
>
> Add support for clock instances for each spi controller.
>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> Acked-by: Jaswinder Singh <jaswinder.singh@linaro.org>
> ---
> arch/arm/mach-exynos/clock-exynos5.c | 98
> ++++++++++++++++++++++++
> arch/arm/mach-exynos/include/mach/regs-clock.h | 4 +
> 2 files changed, 102 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-
> exynos/clock-exynos5.c
> index 5aa460b..ad6c959 100644
> --- a/arch/arm/mach-exynos/clock-exynos5.c
> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> @@ -82,6 +82,11 @@ static int exynos5_clksrc_mask_peric0_ctrl(struct clk
> *clk, int enable)
> return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
> }
>
> +static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
> +{
> + return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
> +}
> +
> static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
> {
> return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
> @@ -692,6 +697,24 @@ static struct clk exynos5_init_clocks_off[] = {
> .enable = exynos5_clk_ip_peric_ctrl,
> .ctrlbit = (1 << 14),
> }, {
> + .name = "spi",
> + .devname = "exynos4210-spi.0",
> + .parent = &exynos5_clk_aclk_66.clk,
> + .enable = exynos5_clk_ip_peric_ctrl,
> + .ctrlbit = (1 << 16),
> + }, {
> + .name = "spi",
> + .devname = "exynos4210-spi.1",
> + .parent = &exynos5_clk_aclk_66.clk,
> + .enable = exynos5_clk_ip_peric_ctrl,
> + .ctrlbit = (1 << 17),
> + }, {
> + .name = "spi",
> + .devname = "exynos4210-spi.2",
> + .parent = &exynos5_clk_aclk_66.clk,
> + .enable = exynos5_clk_ip_peric_ctrl,
> + .ctrlbit = (1 << 18),
> + }, {
> .name = SYSMMU_CLOCK_NAME,
> .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
> .enable = &exynos5_clk_ip_mfc_ctrl,
> @@ -985,6 +1008,72 @@ static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
> .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
> };
>
> +static struct clksrc_clk exynos5_clk_mdout_spi0 = {
See the previous comments and below url.
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/083153.h
tml
[...]
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 32+ messages in thread
* RE: [PATCH 5/6] ARM: dts: Add nodes for spi controllers for Samsung Exynos4 platforms
2012-05-18 9:46 ` Thomas Abraham
@ 2012-05-24 7:43 ` Kukjin Kim
-1 siblings, 0 replies; 32+ messages in thread
From: Kukjin Kim @ 2012-05-24 7:43 UTC (permalink / raw)
To: 'Thomas Abraham', linux-arm-kernel
Cc: linux-samsung-soc, jaswinder.singh, 'Kyoungil Kim'
Thomas Abraham wrote:
>
> Add device nodes for the three instances of spi controllers in Exynos4
> platforms. Enable instance spi 2 for smdkv310 board and disable all
> spi instances for origen board.
>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> ---
> arch/arm/boot/dts/exynos4210-origen.dts | 12 ++++++++
> arch/arm/boot/dts/exynos4210-smdkv310.dts | 44
> +++++++++++++++++++++++++++++
> arch/arm/boot/dts/exynos4210.dtsi | 30 +++++++++++++++++++
> 3 files changed, 86 insertions(+), 0 deletions(-)
[...]
> + aliases {
> + spi0 = &spi_0;
> + spi1 = &spi_1;
> + spi2 = &spi_2;
> + };
> +
Do we need above aliases?
[...]
>
> + spi_2: spi@13940000 {
> + gpios = <&gpc1 1 5 3 0>,
> + <&gpc1 3 5 3 0>,
> + <&gpc1 4 5 3 0>;
> +
> + w25x80@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "w25x80";
> + reg = <0>;
> + spi-max-frequency = <10000>;
> +
> + controller-data {
> + cs-gpio = <&gpc1 2 1 0 3>;
> + samsung,spi-feedback-delay = <0>;
> + };
> +
> + partition@0 {
> + label = "U-Boot";
> + reg = <0x0 0x40000>;
> + read-only;
> + };
> +
> + partition@40000 {
> + label = "Kernel";
> + reg = <0x40000 0xc0000>;
> + };
> + };
> + };
> +
Is there a serial flash(w25x80) is connected via SPI2 on smdkv310?
[...]
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 5/6] ARM: dts: Add nodes for spi controllers for Samsung Exynos4 platforms
@ 2012-05-24 7:43 ` Kukjin Kim
0 siblings, 0 replies; 32+ messages in thread
From: Kukjin Kim @ 2012-05-24 7:43 UTC (permalink / raw)
To: linux-arm-kernel
Thomas Abraham wrote:
>
> Add device nodes for the three instances of spi controllers in Exynos4
> platforms. Enable instance spi 2 for smdkv310 board and disable all
> spi instances for origen board.
>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> ---
> arch/arm/boot/dts/exynos4210-origen.dts | 12 ++++++++
> arch/arm/boot/dts/exynos4210-smdkv310.dts | 44
> +++++++++++++++++++++++++++++
> arch/arm/boot/dts/exynos4210.dtsi | 30 +++++++++++++++++++
> 3 files changed, 86 insertions(+), 0 deletions(-)
[...]
> + aliases {
> + spi0 = &spi_0;
> + spi1 = &spi_1;
> + spi2 = &spi_2;
> + };
> +
Do we need above aliases?
[...]
>
> + spi_2: spi at 13940000 {
> + gpios = <&gpc1 1 5 3 0>,
> + <&gpc1 3 5 3 0>,
> + <&gpc1 4 5 3 0>;
> +
> + w25x80 at 0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "w25x80";
> + reg = <0>;
> + spi-max-frequency = <10000>;
> +
> + controller-data {
> + cs-gpio = <&gpc1 2 1 0 3>;
> + samsung,spi-feedback-delay = <0>;
> + };
> +
> + partition at 0 {
> + label = "U-Boot";
> + reg = <0x0 0x40000>;
> + read-only;
> + };
> +
> + partition at 40000 {
> + label = "Kernel";
> + reg = <0x40000 0xc0000>;
> + };
> + };
> + };
> +
Is there a serial flash(w25x80) is connected via SPI2 on smdkv310?
[...]
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 32+ messages in thread
* RE: [PATCH 6/6] ARM: dts: Add nodes for spi controllers for Samsung Exynos5 platforms
2012-05-18 9:46 ` Thomas Abraham
@ 2012-05-24 7:49 ` Kukjin Kim
-1 siblings, 0 replies; 32+ messages in thread
From: Kukjin Kim @ 2012-05-24 7:49 UTC (permalink / raw)
To: 'Thomas Abraham', linux-arm-kernel
Cc: linux-samsung-soc, jaswinder.singh, 'Kyoungil Kim'
Thomas Abraham wrote:
>
> Add device nodes for the three instances of spi controllers in Exynos5
> platforms and enable instance spi 1 for smdk5250 board.
>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> ---
> arch/arm/boot/dts/exynos5250-smdk5250.dts | 47
> ++++++++++++++++++++++++++++-
> arch/arm/boot/dts/exynos5250.dtsi | 46
> ++++++++++++++++++++++++++++
> 2 files changed, 92 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> index 49945cc..dca572d 100644
> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
[...]
> - bootargs = "root=/dev/ram0 rw ramdisk=8192
> console=ttySAC1,115200";
> + bootargs ="root=/dev/ram0 rw ramdisk=8192
> initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
Yes, we need above. But it should be separated patch from here.
[...]
> + spi_1: spi@12d30000 {
> + gpios = <&gpa2 4 2 3 0>,
> + <&gpa2 6 2 3 0>,
> + <&gpa2 7 2 3 0>;
> +
> + w25q80bw@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "w25x80";
> + reg = <0>;
> + spi-max-frequency = <10000>;
> +
> + controller-data {
> + cs-gpio = <&gpa2 5 1 0 3>;
> + samsung,spi-feedback-delay = <0>;
> + };
> +
> + partition@0 {
> + label = "U-Boot";
> + reg = <0x0 0x40000>;
> + read-only;
> + };
> +
> + partition@40000 {
> + label = "Kernel";
> + reg = <0x40000 0xc0000>;
> + };
> + };
> + };
See my previous comments on 5/6.
[...]
> + combiner:interrupt-controller@10440000 {
> + compatible = "samsung,exynos4210-combiner";
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + samsung,combiner-nr = <32>;
> + reg = <0x10440000 0x1000>;
> + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
> + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
> + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
> + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
> + <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
> + <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
> + <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
> + <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
> + };
Already merged above in my tree.
[...]
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 6/6] ARM: dts: Add nodes for spi controllers for Samsung Exynos5 platforms
@ 2012-05-24 7:49 ` Kukjin Kim
0 siblings, 0 replies; 32+ messages in thread
From: Kukjin Kim @ 2012-05-24 7:49 UTC (permalink / raw)
To: linux-arm-kernel
Thomas Abraham wrote:
>
> Add device nodes for the three instances of spi controllers in Exynos5
> platforms and enable instance spi 1 for smdk5250 board.
>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> ---
> arch/arm/boot/dts/exynos5250-smdk5250.dts | 47
> ++++++++++++++++++++++++++++-
> arch/arm/boot/dts/exynos5250.dtsi | 46
> ++++++++++++++++++++++++++++
> 2 files changed, 92 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> index 49945cc..dca572d 100644
> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
[...]
> - bootargs = "root=/dev/ram0 rw ramdisk=8192
> console=ttySAC1,115200";
> + bootargs ="root=/dev/ram0 rw ramdisk=8192
> initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
Yes, we need above. But it should be separated patch from here.
[...]
> + spi_1: spi at 12d30000 {
> + gpios = <&gpa2 4 2 3 0>,
> + <&gpa2 6 2 3 0>,
> + <&gpa2 7 2 3 0>;
> +
> + w25q80bw at 0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "w25x80";
> + reg = <0>;
> + spi-max-frequency = <10000>;
> +
> + controller-data {
> + cs-gpio = <&gpa2 5 1 0 3>;
> + samsung,spi-feedback-delay = <0>;
> + };
> +
> + partition at 0 {
> + label = "U-Boot";
> + reg = <0x0 0x40000>;
> + read-only;
> + };
> +
> + partition at 40000 {
> + label = "Kernel";
> + reg = <0x40000 0xc0000>;
> + };
> + };
> + };
See my previous comments on 5/6.
[...]
> + combiner:interrupt-controller at 10440000 {
> + compatible = "samsung,exynos4210-combiner";
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + samsung,combiner-nr = <32>;
> + reg = <0x10440000 0x1000>;
> + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
> + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
> + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
> + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
> + <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
> + <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
> + <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
> + <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
> + };
Already merged above in my tree.
[...]
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 1/6] ARM: Exynos4: Fix the incorrect hierarchy of spi controller bus clock
2012-05-24 7:27 ` Kukjin Kim
@ 2012-05-24 9:00 ` Thomas Abraham
-1 siblings, 0 replies; 32+ messages in thread
From: Thomas Abraham @ 2012-05-24 9:00 UTC (permalink / raw)
To: Kukjin Kim; +Cc: linux-arm-kernel, linux-samsung-soc, jaswinder.singh
On 24 May 2012 12:57, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Thomas Abraham wrote:
>>
>> The sclk_spi clock is derived currently from the first level divider
>> (MMCx_RATIO) which is incorrect. The output of the first level clock
>> is divided by a second level divider (MMCx_PRE_RATIO), the output of
>> which is used as the spi bus clock (sclk_spi). Fix the clock hierarchy
>> issues for the sclk_spi clock.
>>
>> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>> Acked-by: Jaswinder Singh <jaswinder.singh@linaro.org>
>> ---
>> arch/arm/mach-exynos/clock-exynos4.c | 48
> ++++++++++++++++++++++++++++--
>> ---
>> 1 files changed, 40 insertions(+), 8 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-
>> exynos/clock-exynos4.c
>> index 10a46a9..b5f0507 100644
>> --- a/arch/arm/mach-exynos/clock-exynos4.c
>> +++ b/arch/arm/mach-exynos/clock-exynos4.c
>> @@ -1242,40 +1242,70 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
>> .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
>> };
>>
>> +static struct clksrc_clk exynos4_clk_mdout_spi0 = {
>
> In this case, it's expected that 'exynos4_clk_dout_spi0' will be used even
> though this indicates the clock of mux_out and divider_out together.
>
>> + .clk = {
>> + .name = "sclk_spi_mdout",
>
> So, this should be 'dout_spi0'
This clock instance has both a mux and a divider. So I used mdout to
mean that there is both a mux and a divider in this clock instance. If
you insist on changing the name to dout_spi0, I will change it.
Thanks,
Thomas.
>
>> + .devname = "exynos4210-spi.0",
>
> [...]
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 1/6] ARM: Exynos4: Fix the incorrect hierarchy of spi controller bus clock
@ 2012-05-24 9:00 ` Thomas Abraham
0 siblings, 0 replies; 32+ messages in thread
From: Thomas Abraham @ 2012-05-24 9:00 UTC (permalink / raw)
To: linux-arm-kernel
On 24 May 2012 12:57, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Thomas Abraham wrote:
>>
>> The sclk_spi clock is derived currently from the first level divider
>> (MMCx_RATIO) which is incorrect. The output of the first level clock
>> is divided by a second level divider (MMCx_PRE_RATIO), the output of
>> which is used as the spi bus clock (sclk_spi). Fix the clock hierarchy
>> issues for the sclk_spi clock.
>>
>> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>> Acked-by: Jaswinder Singh <jaswinder.singh@linaro.org>
>> ---
>> ?arch/arm/mach-exynos/clock-exynos4.c | ? 48
> ++++++++++++++++++++++++++++--
>> ---
>> ?1 files changed, 40 insertions(+), 8 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-
>> exynos/clock-exynos4.c
>> index 10a46a9..b5f0507 100644
>> --- a/arch/arm/mach-exynos/clock-exynos4.c
>> +++ b/arch/arm/mach-exynos/clock-exynos4.c
>> @@ -1242,40 +1242,70 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
>> ? ? ? .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
>> ?};
>>
>> +static struct clksrc_clk exynos4_clk_mdout_spi0 = {
>
> In this case, it's expected that 'exynos4_clk_dout_spi0' will be used even
> though this indicates the clock of mux_out and divider_out together.
>
>> + ? ? .clk ? ?= {
>> + ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_spi_mdout",
>
> So, this should be 'dout_spi0'
This clock instance has both a mux and a divider. So I used mdout to
mean that there is both a mux and a divider in this clock instance. If
you insist on changing the name to dout_spi0, I will change it.
Thanks,
Thomas.
>
>> + ? ? ? ? ? ? .devname ? ? ? ?= "exynos4210-spi.0",
>
> [...]
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 2/6] ARM: Exynos5: Add spi clock support
2012-05-24 7:30 ` Kukjin Kim
@ 2012-05-24 9:04 ` Thomas Abraham
-1 siblings, 0 replies; 32+ messages in thread
From: Thomas Abraham @ 2012-05-24 9:04 UTC (permalink / raw)
To: Kukjin Kim
Cc: linux-arm-kernel, linux-samsung-soc, jaswinder.singh, Kyoungil Kim
On 24 May 2012 13:00, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Thomas Abraham wrote:
>>
>> Add support for clock instances for each spi controller.
>>
>> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>> Acked-by: Jaswinder Singh <jaswinder.singh@linaro.org>
>> ---
>>
>> +static struct clksrc_clk exynos5_clk_mdout_spi0 = {
>
> See the previous comments and below url.
>
> http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/083153.h
> tml
Exynos5 is only device tree based now. And there are changes in the
platform data also now.
Thanks,
Thomas.
>
> [...]
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 2/6] ARM: Exynos5: Add spi clock support
@ 2012-05-24 9:04 ` Thomas Abraham
0 siblings, 0 replies; 32+ messages in thread
From: Thomas Abraham @ 2012-05-24 9:04 UTC (permalink / raw)
To: linux-arm-kernel
On 24 May 2012 13:00, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Thomas Abraham wrote:
>>
>> Add support for clock instances for each spi controller.
>>
>> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>> Acked-by: Jaswinder Singh <jaswinder.singh@linaro.org>
>> ---
>>
>> +static struct clksrc_clk exynos5_clk_mdout_spi0 = {
>
> See the previous comments and below url.
>
> http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/083153.h
> tml
Exynos5 is only device tree based now. And there are changes in the
platform data also now.
Thanks,
Thomas.
>
> [...]
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 5/6] ARM: dts: Add nodes for spi controllers for Samsung Exynos4 platforms
2012-05-24 7:43 ` Kukjin Kim
@ 2012-05-24 9:07 ` Thomas Abraham
-1 siblings, 0 replies; 32+ messages in thread
From: Thomas Abraham @ 2012-05-24 9:07 UTC (permalink / raw)
To: Kukjin Kim
Cc: linux-arm-kernel, linux-samsung-soc, jaswinder.singh, Kyoungil Kim
On 24 May 2012 13:13, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Thomas Abraham wrote:
>>
>> Add device nodes for the three instances of spi controllers in Exynos4
>> platforms. Enable instance spi 2 for smdkv310 board and disable all
>> spi instances for origen board.
>>
>> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>> ---
>> arch/arm/boot/dts/exynos4210-origen.dts | 12 ++++++++
>> arch/arm/boot/dts/exynos4210-smdkv310.dts | 44
>> +++++++++++++++++++++++++++++
>> arch/arm/boot/dts/exynos4210.dtsi | 30 +++++++++++++++++++
>> 3 files changed, 86 insertions(+), 0 deletions(-)
>
> [...]
>
>> + aliases {
>> + spi0 = &spi_0;
>> + spi1 = &spi_1;
>> + spi2 = &spi_2;
>> + };
>> +
>
> Do we need above aliases?
spi0 controller has different fifo sizes than spi1 and spi2. So we
need aliases to identify the port number and know the fifo sizes.
>
> [...]
>
>>
>> + spi_2: spi@13940000 {
>> + gpios = <&gpc1 1 5 3 0>,
>> + <&gpc1 3 5 3 0>,
>> + <&gpc1 4 5 3 0>;
>> +
>> + w25x80@0 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "w25x80";
>> + reg = <0>;
>> + spi-max-frequency = <10000>;
>> +
>> + controller-data {
>> + cs-gpio = <&gpc1 2 1 0 3>;
>> + samsung,spi-feedback-delay = <0>;
>> + };
>> +
>> + partition@0 {
>> + label = "U-Boot";
>> + reg = <0x0 0x40000>;
>> + read-only;
>> + };
>> +
>> + partition@40000 {
>> + label = "Kernel";
>> + reg = <0x40000 0xc0000>;
>> + };
>> + };
>> + };
>> +
>
>
> Is there a serial flash(w25x80) is connected via SPI2 on smdkv310?
Yes, smdkv310 has a onboard spi flash connected to SPI2 (w25x80).
Thanks,
Thomas.
>
> [...]
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 5/6] ARM: dts: Add nodes for spi controllers for Samsung Exynos4 platforms
@ 2012-05-24 9:07 ` Thomas Abraham
0 siblings, 0 replies; 32+ messages in thread
From: Thomas Abraham @ 2012-05-24 9:07 UTC (permalink / raw)
To: linux-arm-kernel
On 24 May 2012 13:13, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Thomas Abraham wrote:
>>
>> Add device nodes for the three instances of spi controllers in Exynos4
>> platforms. Enable instance spi 2 for smdkv310 board and disable all
>> spi instances for origen board.
>>
>> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>> ---
>> ?arch/arm/boot/dts/exynos4210-origen.dts ? | ? 12 ++++++++
>> ?arch/arm/boot/dts/exynos4210-smdkv310.dts | ? 44
>> +++++++++++++++++++++++++++++
>> ?arch/arm/boot/dts/exynos4210.dtsi ? ? ? ? | ? 30 +++++++++++++++++++
>> ?3 files changed, 86 insertions(+), 0 deletions(-)
>
> [...]
>
>> + ? ? aliases {
>> + ? ? ? ? ? ? spi0 = &spi_0;
>> + ? ? ? ? ? ? spi1 = &spi_1;
>> + ? ? ? ? ? ? spi2 = &spi_2;
>> + ? ? };
>> +
>
> Do we need above aliases?
spi0 controller has different fifo sizes than spi1 and spi2. So we
need aliases to identify the port number and know the fifo sizes.
>
> [...]
>
>>
>> + ? ? spi_2: spi at 13940000 {
>> + ? ? ? ? ? ? gpios = <&gpc1 1 5 3 0>,
>> + ? ? ? ? ? ? ? ? ? ? <&gpc1 3 5 3 0>,
>> + ? ? ? ? ? ? ? ? ? ? <&gpc1 4 5 3 0>;
>> +
>> + ? ? ? ? ? ? w25x80 at 0 {
>> + ? ? ? ? ? ? ? ? ? ? #address-cells = <1>;
>> + ? ? ? ? ? ? ? ? ? ? #size-cells = <1>;
>> + ? ? ? ? ? ? ? ? ? ? compatible = "w25x80";
>> + ? ? ? ? ? ? ? ? ? ? reg = <0>;
>> + ? ? ? ? ? ? ? ? ? ? spi-max-frequency = <10000>;
>> +
>> + ? ? ? ? ? ? ? ? ? ? controller-data {
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? cs-gpio = <&gpc1 2 1 0 3>;
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? samsung,spi-feedback-delay = <0>;
>> + ? ? ? ? ? ? ? ? ? ? };
>> +
>> + ? ? ? ? ? ? ? ? ? ? partition at 0 {
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? label = "U-Boot";
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? reg = <0x0 0x40000>;
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? read-only;
>> + ? ? ? ? ? ? ? ? ? ? };
>> +
>> + ? ? ? ? ? ? ? ? ? ? partition at 40000 {
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? label = "Kernel";
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? reg = <0x40000 0xc0000>;
>> + ? ? ? ? ? ? ? ? ? ? };
>> + ? ? ? ? ? ? };
>> + ? ? };
>> +
>
>
> Is there a serial flash(w25x80) is connected via SPI2 on smdkv310?
Yes, smdkv310 has a onboard spi flash connected to SPI2 (w25x80).
Thanks,
Thomas.
>
> [...]
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 6/6] ARM: dts: Add nodes for spi controllers for Samsung Exynos5 platforms
2012-05-24 7:49 ` Kukjin Kim
@ 2012-05-24 9:09 ` Thomas Abraham
-1 siblings, 0 replies; 32+ messages in thread
From: Thomas Abraham @ 2012-05-24 9:09 UTC (permalink / raw)
To: Kukjin Kim
Cc: linux-arm-kernel, linux-samsung-soc, jaswinder.singh, Kyoungil Kim
On 24 May 2012 13:19, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Thomas Abraham wrote:
>>
>> Add device nodes for the three instances of spi controllers in Exynos5
>> platforms and enable instance spi 1 for smdk5250 board.
>>
>> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>> ---
>> arch/arm/boot/dts/exynos5250-smdk5250.dts | 47
>> ++++++++++++++++++++++++++++-
>> arch/arm/boot/dts/exynos5250.dtsi | 46
>> ++++++++++++++++++++++++++++
>> 2 files changed, 92 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> b/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> index 49945cc..dca572d 100644
>> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
>
> [...]
>
>> - bootargs = "root=/dev/ram0 rw ramdisk=8192
>> console=ttySAC1,115200";
>> + bootargs ="root=/dev/ram0 rw ramdisk=8192
>> initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
>
> Yes, we need above. But it should be separated patch from here.
This is mistake. I will remove this from here. Thanks for pointing this out.
>
> [...]
>
>> + spi_1: spi@12d30000 {
>> + gpios = <&gpa2 4 2 3 0>,
>> + <&gpa2 6 2 3 0>,
>> + <&gpa2 7 2 3 0>;
>> +
>> + w25q80bw@0 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "w25x80";
>> + reg = <0>;
>> + spi-max-frequency = <10000>;
>> +
>> + controller-data {
>> + cs-gpio = <&gpa2 5 1 0 3>;
>> + samsung,spi-feedback-delay = <0>;
>> + };
>> +
>> + partition@0 {
>> + label = "U-Boot";
>> + reg = <0x0 0x40000>;
>> + read-only;
>> + };
>> +
>> + partition@40000 {
>> + label = "Kernel";
>> + reg = <0x40000 0xc0000>;
>> + };
>> + };
>> + };
>
> See my previous comments on 5/6.
Yes, there is a onboard spi flash.
>
> [...]
>
>> + combiner:interrupt-controller@10440000 {
>> + compatible = "samsung,exynos4210-combiner";
>> + #interrupt-cells = <2>;
>> + interrupt-controller;
>> + samsung,combiner-nr = <32>;
>> + reg = <0x10440000 0x1000>;
>> + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
>> + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
>> + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
>> + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
>> + <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
>> + <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
>> + <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
>> + <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
>> + };
>
> Already merged above in my tree.
Right. I completely missed this one. I will remove this from here.
Thanks a lot for your review and comments.
Regards,
Thomas.
>
> [...]
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 6/6] ARM: dts: Add nodes for spi controllers for Samsung Exynos5 platforms
@ 2012-05-24 9:09 ` Thomas Abraham
0 siblings, 0 replies; 32+ messages in thread
From: Thomas Abraham @ 2012-05-24 9:09 UTC (permalink / raw)
To: linux-arm-kernel
On 24 May 2012 13:19, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Thomas Abraham wrote:
>>
>> Add device nodes for the three instances of spi controllers in Exynos5
>> platforms and enable instance spi 1 for smdk5250 board.
>>
>> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>> ---
>> ?arch/arm/boot/dts/exynos5250-smdk5250.dts | ? 47
>> ++++++++++++++++++++++++++++-
>> ?arch/arm/boot/dts/exynos5250.dtsi ? ? ? ? | ? 46
>> ++++++++++++++++++++++++++++
>> ?2 files changed, 92 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> b/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> index 49945cc..dca572d 100644
>> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
>
> [...]
>
>> - ? ? ? ? ? ? bootargs = "root=/dev/ram0 rw ramdisk=8192
>> console=ttySAC1,115200";
>> + ? ? ? ? ? ? bootargs ="root=/dev/ram0 rw ramdisk=8192
>> initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
>
> Yes, we need above. But it should be separated patch from here.
This is mistake. I will remove this from here. Thanks for pointing this out.
>
> [...]
>
>> + ? ? spi_1: spi at 12d30000 {
>> + ? ? ? ? ? ? gpios = <&gpa2 4 2 3 0>,
>> + ? ? ? ? ? ? ? ? ? ? <&gpa2 6 2 3 0>,
>> + ? ? ? ? ? ? ? ? ? ? <&gpa2 7 2 3 0>;
>> +
>> + ? ? ? ? ? ? w25q80bw at 0 {
>> + ? ? ? ? ? ? ? ? ? ? #address-cells = <1>;
>> + ? ? ? ? ? ? ? ? ? ? #size-cells = <1>;
>> + ? ? ? ? ? ? ? ? ? ? compatible = "w25x80";
>> + ? ? ? ? ? ? ? ? ? ? reg = <0>;
>> + ? ? ? ? ? ? ? ? ? ? spi-max-frequency = <10000>;
>> +
>> + ? ? ? ? ? ? ? ? ? ? controller-data {
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? cs-gpio = <&gpa2 5 1 0 3>;
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? samsung,spi-feedback-delay = <0>;
>> + ? ? ? ? ? ? ? ? ? ? };
>> +
>> + ? ? ? ? ? ? ? ? ? ? partition at 0 {
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? label = "U-Boot";
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? reg = <0x0 0x40000>;
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? read-only;
>> + ? ? ? ? ? ? ? ? ? ? };
>> +
>> + ? ? ? ? ? ? ? ? ? ? partition at 40000 {
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? label = "Kernel";
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? reg = <0x40000 0xc0000>;
>> + ? ? ? ? ? ? ? ? ? ? };
>> + ? ? ? ? ? ? };
>> + ? ? };
>
> See my previous comments on 5/6.
Yes, there is a onboard spi flash.
>
> [...]
>
>> + ? ? combiner:interrupt-controller at 10440000 {
>> + ? ? ? ? ? ? compatible = "samsung,exynos4210-combiner";
>> + ? ? ? ? ? ? #interrupt-cells = <2>;
>> + ? ? ? ? ? ? interrupt-controller;
>> + ? ? ? ? ? ? samsung,combiner-nr = <32>;
>> + ? ? ? ? ? ? reg = <0x10440000 0x1000>;
>> + ? ? ? ? ? ? interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ?<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ?<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ?<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ?<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ?<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ?<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ?<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
>> + ? ? };
>
> Already merged above in my tree.
Right. I completely missed this one. I will remove this from here.
Thanks a lot for your review and comments.
Regards,
Thomas.
>
> [...]
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2012-05-24 9:10 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-05-18 9:46 [PATCH 0/6] ARM: Exynos: Enable SPI platform support for Exynos4 and Exynos5 Thomas Abraham
2012-05-18 9:46 ` Thomas Abraham
2012-05-18 9:46 ` [PATCH 1/6] ARM: Exynos4: Fix the incorrect hierarchy of spi controller bus clock Thomas Abraham
2012-05-18 9:46 ` Thomas Abraham
2012-05-24 7:27 ` Kukjin Kim
2012-05-24 7:27 ` Kukjin Kim
2012-05-24 9:00 ` Thomas Abraham
2012-05-24 9:00 ` Thomas Abraham
2012-05-18 9:46 ` [PATCH 2/6] ARM: Exynos5: Add spi clock support Thomas Abraham
2012-05-18 9:46 ` Thomas Abraham
2012-05-24 7:30 ` Kukjin Kim
2012-05-24 7:30 ` Kukjin Kim
2012-05-24 9:04 ` Thomas Abraham
2012-05-24 9:04 ` Thomas Abraham
2012-05-18 9:46 ` [PATCH 3/6] ARM: Exynos4: Enable platform support for SPI controllers Thomas Abraham
2012-05-18 9:46 ` Thomas Abraham
2012-05-18 9:46 ` [PATCH 4/6] ARM: Exynos5: " Thomas Abraham
2012-05-18 9:46 ` Thomas Abraham
2012-05-18 9:46 ` [PATCH 5/6] ARM: dts: Add nodes for spi controllers for Samsung Exynos4 platforms Thomas Abraham
2012-05-18 9:46 ` Thomas Abraham
2012-05-24 7:43 ` Kukjin Kim
2012-05-24 7:43 ` Kukjin Kim
2012-05-24 9:07 ` Thomas Abraham
2012-05-24 9:07 ` Thomas Abraham
2012-05-18 9:46 ` [PATCH 6/6] ARM: dts: Add nodes for spi controllers for Samsung Exynos5 platforms Thomas Abraham
2012-05-18 9:46 ` Thomas Abraham
2012-05-23 9:50 ` padma venkat
2012-05-23 9:50 ` padma venkat
2012-05-24 7:49 ` Kukjin Kim
2012-05-24 7:49 ` Kukjin Kim
2012-05-24 9:09 ` Thomas Abraham
2012-05-24 9:09 ` Thomas Abraham
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