* [PATCH 0/6] S5PV210 PM Support (suspend-to-mem) @ 2010-06-14 8:39 MyungJoo Ham 2010-06-14 8:39 ` [PATCH 1/6] S5PV210 Add IRQ/EINT register information for the CPU MyungJoo Ham 2010-06-15 3:45 ` [PATCH 0/6] S5PV210 PM Support (suspend-to-mem) Kukjin Kim 0 siblings, 2 replies; 11+ messages in thread From: MyungJoo Ham @ 2010-06-14 8:39 UTC (permalink / raw) To: linux-arm-kernel This patch set supports S5PV210/S5PC110 PM (suspend-to-mem). MyungJoo Ham (8): S5PV210 Add IRQ/EINT register information for the CPU. S5PV210 add clock registers for the CPU. S5PV210 added register mappings S5PV210 GPIO relataed registers are added. S5PV210 added EINT-GPIO register mappings S5PV210 PM Support (suspend-to-mem) arch/arm/mach-s5pv210/Makefile | 4 + arch/arm/mach-s5pv210/include/mach/irqs.h | 9 + arch/arm/mach-s5pv210/include/mach/map.h | 45 +++ arch/arm/mach-s5pv210/include/mach/regs-clock.h | 467 ++++++++++++++++++++++- arch/arm/mach-s5pv210/include/mach/regs-gpio.h | 121 ++++++ arch/arm/mach-s5pv210/include/mach/regs-irq.h | 6 + arch/arm/plat-s5p/Makefile | 3 + arch/arm/plat-s5p/include/plat/gpio-ext.h | 44 +++ arch/arm/plat-s5p/include/plat/map-s5p.h | 1 + arch/arm/plat-s5p/sleep.S | 248 ++++++++++++ arch/arm/plat-samsung/include/plat/pm-core.h | 53 +++ arch/arm/plat-samsung/include/plat/pm.h | 13 + arch/arm/plat-samsung/pm-gpio.c | 4 +- arch/arm/plat-samsung/pm.c | 75 ++++- 14 files changed, 1082 insertions(+), 11 deletions(-) create mode 100644 arch/arm/plat-s5p/include/plat/gpio-ext.h create mode 100644 arch/arm/plat-s5p/sleep.S create mode 100644 arch/arm/plat-samsung/include/plat/pm-core.h ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/6] S5PV210 Add IRQ/EINT register information for the CPU. 2010-06-14 8:39 [PATCH 0/6] S5PV210 PM Support (suspend-to-mem) MyungJoo Ham @ 2010-06-14 8:39 ` MyungJoo Ham 2010-06-14 8:39 ` [PATCH 2/6] S5PV210 add clock registers " MyungJoo Ham 2010-06-15 6:05 ` [PATCH 1/6] S5PV210 Add IRQ/EINT register information " Kukjin Kim 2010-06-15 3:45 ` [PATCH 0/6] S5PV210 PM Support (suspend-to-mem) Kukjin Kim 1 sibling, 2 replies; 11+ messages in thread From: MyungJoo Ham @ 2010-06-14 8:39 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: MyungJoo Ham <MyungJoo.Ham@samsung.com> --- arch/arm/mach-s5pv210/include/mach/irqs.h | 9 +++++++++ arch/arm/mach-s5pv210/include/mach/regs-irq.h | 6 ++++++ 2 files changed, 15 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h index 9689537..6c5f491 100644 --- a/arch/arm/mach-s5pv210/include/mach/irqs.h +++ b/arch/arm/mach-s5pv210/include/mach/irqs.h @@ -118,9 +118,18 @@ #define IRQ_MDNIE3 S5P_IRQ_VIC3(8) #define IRQ_VIC_END S5P_IRQ_VIC3(31) +/* External interrupt */ + #define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) #define S5P_EINT_BASE2 (IRQ_VIC_END + 1) +#define S5P_EINT(x) (S5P_EINT_BASE2 + ((x) - 16)) +#define IRQ_EINT_BIT(x) ((x) < IRQ_EINT16_31 ? (x) - S5P_VIC0_BASE : (x) - S5P_EINT(0)) + +/* GPIO interrupt */ +#define S5P_IRQ_GPIO_BASE (IRQ_EINT(31) + 1) +#define S5P_IRQ_GPIO(x) (S5P_IRQ_GPIO_BASE + (x)) + /* Set the default NR_IRQS */ #define NR_IRQS (IRQ_EINT(31) + 1) diff --git a/arch/arm/mach-s5pv210/include/mach/regs-irq.h b/arch/arm/mach-s5pv210/include/mach/regs-irq.h index 5c3b104..139604f 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-irq.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-irq.h @@ -16,4 +16,10 @@ #include <asm/hardware/vic.h> #include <mach/map.h> +/* interrupt controller */ +#define S5PV210_VIC0REG(x) ((x) + VA_VIC0) +#define S5PV210_VIC1REG(x) ((x) + VA_VIC1) +#define S5PV210_VIC2REG(x) ((x) + VA_VIC2) +#define S5PV210_VIC3REG(x) ((x) + VA_VIC3) + #endif /* __ASM_ARCH_REGS_IRQ_H */ -- 1.6.3.3 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/6] S5PV210 add clock registers for the CPU. 2010-06-14 8:39 ` [PATCH 1/6] S5PV210 Add IRQ/EINT register information for the CPU MyungJoo Ham @ 2010-06-14 8:39 ` MyungJoo Ham 2010-06-14 8:39 ` [PATCH 3/6] S5PV210 added register mappings MyungJoo Ham 2010-06-15 4:20 ` [PATCH 2/6] S5PV210 add clock registers for the CPU Kukjin Kim 2010-06-15 6:05 ` [PATCH 1/6] S5PV210 Add IRQ/EINT register information " Kukjin Kim 1 sibling, 2 replies; 11+ messages in thread From: MyungJoo Ham @ 2010-06-14 8:39 UTC (permalink / raw) To: linux-arm-kernel Besides, renamed a register name "BUS0" into "IP5" as EVT1 uses "IP5" instead of BUS0 (of EVT0) Signed-off-by: MyungJoo Ham <MyungJoo.Ham@samsung.com> --- arch/arm/mach-s5pv210/include/mach/regs-clock.h | 467 ++++++++++++++++++++++- 1 files changed, 465 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h index 2a25ab4..9652338 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h @@ -25,6 +25,8 @@ #define S5P_APLL_CON S5P_CLKREG(0x100) #define S5P_MPLL_CON S5P_CLKREG(0x108) #define S5P_EPLL_CON S5P_CLKREG(0x110) +#define S5P_EPLL_CON1 S5P_CLKREG(0x114) +#define S5P_EPLL_CON1_MASK (0xFFFF << 0) #define S5P_VPLL_CON S5P_CLKREG(0x120) #define S5P_CLK_SRC0 S5P_CLKREG(0x200) @@ -63,14 +65,139 @@ #define S5P_CLKGATE_IP4 S5P_CLKREG(0x470) #define S5P_CLKGATE_BLOCK S5P_CLKREG(0x480) -#define S5P_CLKGATE_BUS0 S5P_CLKREG(0x484) +#define S5P_CLKGATE_IP5 S5P_CLKREG(0x484) #define S5P_CLKGATE_BUS1 S5P_CLKREG(0x488) #define S5P_CLK_OUT S5P_CLKREG(0x500) +#define S5P_CLK_DIV_STAT0 S5P_CLKREG(0x1000) +#define S5P_CLK_DIV_STAT1 S5P_CLKREG(0x1004) +#define S5P_CLK_MUX_STAT0 S5P_CLKREG(0x1100) +#define S5P_CLK_MUX_STAT1 S5P_CLKREG(0x1104) +#define S5P_MIXER_OUT_SEL S5P_CLKREG(0x7004) +#define S5P_MDNIE_SEL S5P_CLKREG(0x7008) +#define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200) +#define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204) + +#define S5P_DCGIDX_MAP0 S5P_CLKREG(0x3000) +#define S5P_DCGIDX_MAP1 S5P_CLKREG(0x3004) +#define S5P_DCGIDX_MAP2 S5P_CLKREG(0x3008) +#define S5P_DCGPERF_MAP0 S5P_CLKREG(0x3020) +#define S5P_DCGPERF_MAP1 S5P_CLKREG(0x3024) +#define S5P_DVCIDX_MAP S5P_CLKREG(0x3040) +#define S5P_FREQ_CPU S5P_CLKREG(0x3060) +#define S5P_FREQ_DPM S5P_CLKREG(0x3064) +#define S5P_DVSEMCLK_EN S5P_CLKREG(0x3080) +#define S5P_MAXPERF S5P_CLKREG(0x3084) + +#define S5P_EPLL_EN (1<<31) +#define S5P_EPLL_MASK 0xffffffff +#define S5P_EPLLVAL(_v,_m,_p,_s) ((_v) << 27 | (_m) << 16 | ((_p) << 8) | ((_s))) /* CLKSRC0 */ +#define S5P_CLKSRC0_APLL_MASK (0x1<<0) +#define S5P_CLKSRC0_APLL_SHIFT (0) +#define S5P_CLKSRC0_MPLL_MASK (0x1<<4) +#define S5P_CLKSRC0_MPLL_SHIFT (4) +#define S5P_CLKSRC0_EPLL_MASK (0x1<<8) +#define S5P_CLKSRC0_EPLL_SHIFT (8) +#define S5P_CLKSRC0_VPLL_MASK (0x1<<12) +#define S5P_CLKSRC0_VPLL_SHIFT (12) #define S5P_CLKSRC0_MUX200_MASK (0x1<<16) +#define S5P_CLKSRC0_MUX200_SHIFT (16) #define S5P_CLKSRC0_MUX166_MASK (0x1<<20) +#define S5P_CLKSRC0_MUX166_SHIFT (20) #define S5P_CLKSRC0_MUX133_MASK (0x1<<24) +#define S5P_CLKSRC0_MUX133_SHIFT (24) +#define S5P_CLKSRC0_ONENAND_MASK (0x1<<28) +#define S5P_CLKSRC0_ONENAND_SHIFT (28) + +/* CLKSRC1 */ +#define S5P_CLKSRC1_HDMI_MASK (0x1<<0) +#define S5P_CLKSRC1_HDMI_SHIFT (0) +#define S5P_CLKSRC1_MIXER_MASK (0x1<<4) +#define S5P_CLKSRC1_MIXER_SHIFT (4) +#define S5P_CLKSRC1_DAC_MASK (0x1<<8) +#define S5P_CLKSRC1_DAC_SHIFT (8) +#define S5P_CLKSRC1_CAM0_MASK (0xF<<12) +#define S5P_CLKSRC1_CAM0_SHIFT (12) +#define S5P_CLKSRC1_CAM1_MASK (0xF<<16) +#define S5P_CLKSRC1_CAM1_SHIFT (16) +#define S5P_CLKSRC1_FIMD_MASK (0xF<<20) +#define S5P_CLKSRC1_FIMD_SHIFT (20) +#define S5P_CLKSRC1_CSIS_MASK (0xF<<24) +#define S5P_CLKSRC1_CSIS_SHIFT (24) +#define S5P_CLKSRC1_VPLLSRC_MASK (0x1<<28) +#define S5P_CLKSRC1_VPLLSRC_SHIFT (28) + +/* CLKSRC2 */ +#define S5P_CLKSRC2_G3D_MASK (0x3<<0) +#define S5P_CLKSRC2_G3D_SHIFT (0) +#define S5P_CLKSRC2_MFC_MASK (0x3<<4) +#define S5P_CLKSRC2_MFC_SHIFT (4) +#define S5P_CLKSRC2_G2D_MASK (0x3<<8) +#define S5P_CLKSRC2_G2D_SHIFT (8) + +/* CLKSRC3 */ +#define S5P_CLKSRC3_MDNIE_MASK (0xF<<0) +#define S5P_CLKSRC3_MDNIE_SHIFT (0) +#define S5P_CLKSRC3_MDNIE_PWMCLK_MASK (0xF<<4) +#define S5P_CLKSRC3_MDNIE_PWMCLK_SHIFT (4) +#define S5P_CLKSRC3_FIMC0_LCLK_MASK (0xF<<12) +#define S5P_CLKSRC3_FIMC0_LCLK_SHIFT (12) +#define S5P_CLKSRC3_FIMC1_LCLK_MASK (0xF<<16) +#define S5P_CLKSRC3_FIMC1_LCLK_SHIFT (16) +#define S5P_CLKSRC3_FIMC2_LCLK_MASK (0xF<<20) +#define S5P_CLKSRC3_FIMC2_LCLK_SHIFT (20) + +/* CLKSRC4 */ +#define S5P_CLKSRC4_MMC0_MASK (0xF<<0) +#define S5P_CLKSRC4_MMC0_SHIFT (0) +#define S5P_CLKSRC4_MMC1_MASK (0xF<<4) +#define S5P_CLKSRC4_MMC1_SHIFT (4) +#define S5P_CLKSRC4_MMC2_MASK (0xF<<8) +#define S5P_CLKSRC4_MMC2_SHIFT (8) +#define S5P_CLKSRC4_MMC3_MASK (0xF<<12) +#define S5P_CLKSRC4_MMC3_SHIFT (12) +#define S5P_CLKSRC4_UART0_MASK (0xF<<16) +#define S5P_CLKSRC4_UART0_SHIFT (16) +#define S5P_CLKSRC4_UART1_MASK (0xF<<20) +#define S5P_CLKSRC4_UART1_SHIFT (20) +#define S5P_CLKSRC4_UART2_MASK (0xF<<24) +#define S5P_CLKSRC4_UART2_SHIFT (24) +#define S5P_CLKSRC4_UART3_MASK (0xF<<28) +#define S5P_CLKSRC4_UART3_SHIFT (28) + +/* CLKSRC5 */ +#define S5P_CLKSRC5_SPI0_MASK (0xF<<0) +#define S5P_CLKSRC5_SPI0_SHIFT (0) +#define S5P_CLKSRC5_SPI1_MASK (0xF<<4) +#define S5P_CLKSRC5_SPI1_SHIFT (4) +#define S5P_CLKSRC5_SPI2_MASK (0xF<<8) +#define S5P_CLKSRC5_SPI2_SHIFT (8) +#define S5P_CLKSRC5_PWM_MASK (0xF<<12) +#define S5P_CLKSRC5_PWM_SHIFT (12) + +/* CLKSRC6 */ +#define S5P_CLKSRC6_AUDIO0_MASK (0xF<<0) +#define S5P_CLKSRC6_AUDIO0_SHIFT (0) +#define S5P_CLKSRC6_AUDIO1_MASK (0xF<<4) +#define S5P_CLKSRC6_AUDIO1_SHIFT (4) +#define S5P_CLKSRC6_AUDIO2_MASK (0xF<<8) +#define S5P_CLKSRC6_AUDIO2_SHIFT (8) +#define S5P_CLKSRC6_SPDIF_MASK (0x3<<12) +#define S5P_CLKSRC6_SPDIF_SHIFT (12) +#define S5P_CLKSRC6_HPM_MASK (0x1<<16) +#define S5P_CLKSRC6_HPM_SHIFT (16) +#define S5P_CLKSRC6_PWI_MASK (0xF<<20) +#define S5P_CLKSRC6_PWI_SHIFT (20) +#define S5P_CLKSRC6_ONEDRAM_MASK (0x3<<24) +#define S5P_CLKSRC6_ONEDRAM_SHIFT (24) + +/* CLKSRC_MASK0 - To be defined */ +#define S5P_CLKSRC_MASK0_HDMI (1<<0) +#define S5P_CLKSRC_MASK0_MIXER (1<<1) + +/* CLKSRC_MASK1 - To be defined */ + /* CLKDIV0 */ #define S5P_CLKDIV0_APLL_SHIFT (0) @@ -90,7 +217,325 @@ #define S5P_CLKDIV0_PCLK66_SHIFT (28) #define S5P_CLKDIV0_PCLK66_MASK (0x7 << S5P_CLKDIV0_PCLK66_SHIFT) +/* CLKDIV1 */ +#define S5P_CLKDIV1_TBLK_MASK (0xF<<0) +#define S5P_CLKDIV1_TBLK_SHIFT (0) +#define S5P_CLKDIV1_FIMC_MASK (0xF<<8) +#define S5P_CLKDIV1_FIMC_SHIFT (8) +#define S5P_CLKDIV1_CAM0_MASK (0xF<<12) +#define S5P_CLKDIV1_CAM0_SHIFT (12) +#define S5P_CLKDIV1_CAM1_MASK (0xF<<16) +#define S5P_CLKDIV1_CAM1_SHIFT (16) +#define S5P_CLKDIV1_FIMD_MASK (0xF<<20) +#define S5P_CLKDIV1_FIMD_SHIFT (20) +#define S5P_CLKDIV1_CSIS_MASK (0xF<<28) +#define S5P_CLKDIV1_CSIS_SHIFT (28) + +/* CLKDIV2 */ +#define S5P_CLKDIV2_G3D_MASK (0xF<<0) +#define S5P_CLKDIV2_G3D_SHIFT (0) +#define S5P_CLKDIV2_MFC_MASK (0xF<<4) +#define S5P_CLKDIV2_MFC_SHIFT (4) +#define S5P_CLKDIV2_G2D_MASK (0xF<<8) +#define S5P_CLKDIV2_G2D_SHIFT (8) + +/* CLKDIV3 */ +#define S5P_CLKDIV3_MDNIE_MASK (0xf<<0) +#define S5P_CLKDIV3_MDNIE_SHIFT (0) +#define S5P_CLKDIV3_MDNIE_PWM_MASK (0x3f<<4) +#define S5P_CLKDIV3_MDNIE_PWM_SHIFT (4) +#define S5P_CLKDIV3_FIMC0_LCLK_MASK (0xf<<12) +#define S5P_CLKDIV3_FIMC0_LCLK_SHIFT (12) +#define S5P_CLKDIV3_FIMC1_LCLK_MASK (0xf<<16) +#define S5P_CLKDIV3_FIMC1_LCLK_SHIFT (16) +#define S5P_CLKDIV3_FIMC2_LCLK_MASK (0xf<<20) +#define S5P_CLKDIV3_FIMC2_LCLK_SHIFT (20) + +/* CLKDIV4 */ +#define S5P_CLKDIV4_MMC0_MASK (0xF<<0) +#define S5P_CLKDIV4_MMC0_SHIFT (0) +#define S5P_CLKDIV4_MMC1_MASK (0xF<<4) +#define S5P_CLKDIV4_MMC1_SHIFT (4) +#define S5P_CLKDIV4_MMC2_MASK (0xF<<8) +#define S5P_CLKDIV4_MMC2_SHIFT (8) +#define S5P_CLKDIV4_MMC3_MASK (0xF<<12) +#define S5P_CLKDIV4_MMC3_SHIFT (12) +#define S5P_CLKDIV4_UART0_MASK (0xF<<16) +#define S5P_CLKDIV4_UART0_SHIFT (16) +#define S5P_CLKDIV4_UART1_MASK (0xf<<20) +#define S5P_CLKDIV4_UART1_SHIFT (20) +#define S5P_CLKDIV4_UART2_MASK (0xf<<24) +#define S5P_CLKDIV4_UART2_SHIFT (24) +#define S5P_CLKDIV4_UART3_MASK (0xf<<28) +#define S5P_CLKDIV4_UART3_SHIFT (28) + +/* CLKDIV5 */ +#define S5P_CLKDIV5_SPI0_MASK (0xF<<0) +#define S5P_CLKDIV5_SPI0_SHIFT (0) +#define S5P_CLKDIV5_SPI1_MASK (0xF<<4) +#define S5P_CLKDIV5_SPI1_SHIFT (4) +#define S5P_CLKDIV5_SPI2_MASK (0xF<<8) +#define S5P_CLKDIV5_SPI2_SHIFT (8) +#define S5P_CLKDIV5_PWM_MASK (0xF<<12) +#define S5P_CLKDIV5_PWM_SHIFT (12) + +/* CLKDIV6 */ +#define S5P_CLKDIV6_AUDIO0_MASK (0xF<<0) +#define S5P_CLKDIV6_AUDIO0_SHIFT (0) +#define S5P_CLKDIV6_AUDIO1_MASK (0xF<<4) +#define S5P_CLKDIV6_AUDIO1_SHIFT (4) +#define S5P_CLKDIV6_AUDIO2_MASK (0xF<<8) +#define S5P_CLKDIV6_AUDIO2_SHIFT (8) +#define S5P_CLKDIV6_ONENAND_MASK (0x7<<12) +#define S5P_CLKDIV6_ONENAND_SHIFT (12) +#define S5P_CLKDIV6_COPY_MASK (0x7<<16) +#define S5P_CLKDIV6_COPY_SHIFT (16) +#define S5P_CLKDIV6_HPM_MASK (0x7<<20) +#define S5P_CLKDIV6_HPM_SHIFT (20) +#define S5P_CLKDIV6_PWI_MASK (0xf<<24) +#define S5P_CLKDIV6_PWI_SHIFT (24) +#define S5P_CLKDIV6_ONEDRAM_MASK (0xf<<28) +#define S5P_CLKDIV6_ONEDRAM_SHIFT (28) + +/* IP Clock Gate 0 Registers */ +#define S5P_CLKGATE_IP0_CSIS (1<<31) +#define S5P_CLKGATE_IP0_IPC (1<<30) +#define S5P_CLKGATE_IP0_ROTATOR (1<<29) +#define S5P_CLKGATE_IP0_JPEG (1<<28) +#define S5P_CLKGATE_IP0_FIMC2 (1<<26) +#define S5P_CLKGATE_IP0_FIMC1 (1<<25) +#define S5P_CLKGATE_IP0_FIMC0 (1<<24) +#define S5P_CLKGATE_IP0_MFC (1<<16) +#define S5P_CLKGATE_IP0_G2D (1<<12) +#define S5P_CLKGATE_IP0_G3D (1<<8) +#define S5P_CLKGATE_IP0_IMEM (1<<5) +#define S5P_CLKGATE_IP0_PDMA1 (1<<4) +#define S5P_CLKGATE_IP0_PDMA0 (1<<3) +#define S5P_CLKGATE_IP0_MDMA (1<<2) +#define S5P_CLKGATE_IP0_DMC1 (1<<1) +#define S5P_CLKGATE_IP0_DMC0 (1<<0) +#define S5P_CLKGATE_IP0_RESERVED (0x08feeec0) +#define S5P_CLKGATE_IP0_ALWAYS_ON ( S5P_CLKGATE_IP0_DMC1 |\ + S5P_CLKGATE_IP0_DMC0 |\ + S5P_CLKGATE_IP0_IMEM ) +#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING +#define S5P_CLKGATE_IP0_BOOT_ON ( S5P_CLKGATE_IP0_PDMA0 |\ + S5P_CLKGATE_IP0_PDMA1) +#else +#define S5P_CLKGATE_IP0_BOOT_ON ( S5P_CLKGATE_IP0_PDMA0 |\ + S5P_CLKGATE_IP0_PDMA1 |\ + S5P_CLKGATE_IP0_G2D) +#endif + +/* IP Clock Gate 1 Registers */ +#define S5P_CLKGATE_IP1_NFCON (1<<28) +#define S5P_CLKGATE_IP1_SROMC (1<<26) +#define S5P_CLKGATE_IP1_CFCON (1<<25) +#define S5P_CLKGATE_IP1_NANDXL (1<<24) +#define S5P_CLKGATE_IP1_USBHOST (1<<17) +#define S5P_CLKGATE_IP1_USBOTG (1<<16) +#define S5P_CLKGATE_IP1_HDMI (1<<11) +#define S5P_CLKGATE_IP1_TVENC (1<<10) +#define S5P_CLKGATE_IP1_MIXER (1<<9) +#define S5P_CLKGATE_IP1_VP (1<<8) +#define S5P_CLKGATE_IP1_DSIM (1<<2) +#define S5P_CLKGATE_IP1_MIE (1<<1) +#define S5P_CLKGATE_IP1_FIMD (1<<0) +#define S5P_CLKGATE_IP1_RESERVED (0xe8fcf0f8) +#define S5P_CLKGATE_IP1_ALWAYS_ON ( 0 ) +#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING +#define S5P_CLKGATE_IP1_BOOT_ON ( S5P_CLKGATE_IP1_FIMD |\ + S5P_CLKGATE_IP1_NANDXL) +#else +#define S5P_CLKGATE_IP1_BOOT_ON ( S5P_CLKGATE_IP1_FIMD |\ + S5P_CLKGATE_IP1_NANDXL |\ + S5P_CLKGATE_IP1_USBOTG) +#endif + + +/* IP Clock Gate 2 Registers */ +#define S5P_CLKGATE_IP2_TZIC3 (1<<31) +#define S5P_CLKGATE_IP2_TZIC2 (1<<30) +#define S5P_CLKGATE_IP2_TZIC1 (1<<29) +#define S5P_CLKGATE_IP2_TZIC0 (1<<28) +#define S5P_CLKGATE_IP2_VIC3 (1<<27) +#define S5P_CLKGATE_IP2_VIC2 (1<<26) +#define S5P_CLKGATE_IP2_VIC1 (1<<25) +#define S5P_CLKGATE_IP2_VIC0 (1<<24) +#define S5P_CLKGATE_IP2_TSI (1<<20) +#define S5P_CLKGATE_IP2_HSMMC3 (1<<19) +#define S5P_CLKGATE_IP2_HSMMC2 (1<<18) +#define S5P_CLKGATE_IP2_HSMMC1 (1<<17) +#define S5P_CLKGATE_IP2_HSMMC0 (1<<16) +#define S5P_CLKGATE_IP2_SECJTAG (1<<11) +#define S5P_CLKGATE_IP2_HOSTIF (1<<10) +#define S5P_CLKGATE_IP2_MODEM (1<<9) +#define S5P_CLKGATE_IP2_CORESIGHT (1<<8) +#define S5P_CLKGATE_IP2_SDM (1<<1) +#define S5P_CLKGATE_IP2_SECSS (1<<0) +#define S5P_CLKGATE_IP2_RESERVED (0xe0f0fc) +#define S5P_CLKGATE_IP2_ALWAYS_ON ( S5P_CLKGATE_IP2_TZIC3 | S5P_CLKGATE_IP2_TZIC2 |\ + S5P_CLKGATE_IP2_TZIC1 | S5P_CLKGATE_IP2_TZIC0 |\ + S5P_CLKGATE_IP2_VIC3 | S5P_CLKGATE_IP2_VIC2 |\ + S5P_CLKGATE_IP2_VIC1 | S5P_CLKGATE_IP2_VIC0 |\ + S5P_CLKGATE_IP2_SECJTAG | S5P_CLKGATE_IP2_CORESIGHT |\ + S5P_CLKGATE_IP2_SDM | S5P_CLKGATE_IP2_SECSS ) +#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING +#define S5P_CLKGATE_IP2_BOOT_ON ( 0 ) +#else +#define S5P_CLKGATE_IP2_BOOT_ON ( S5P_CLKGATE_IP2_TSI |\ + S5P_CLKGATE_IP2_HSMMC2 |\ + S5P_CLKGATE_IP2_HSMMC0 |\ + S5P_CLKGATE_IP2_HOSTIF |\ + S5P_CLKGATE_IP2_MODEM) +#endif + + +/* IP Clock Gate 3 Registers */ +#define S5P_CLKGATE_IP3_PCM2 (1<<30) +#define S5P_CLKGATE_IP3_PCM1 (1<<29) +#define S5P_CLKGATE_IP3_PCM0 (1<<28) +#define S5P_CLKGATE_IP3_SYSCON (1<<27) +#define S5P_CLKGATE_IP3_GPIO (1<<26) +#define S5P_CLKGATE_IP3_TSADC (1<<24) +#define S5P_CLKGATE_IP3_PWM (1<<23) +#define S5P_CLKGATE_IP3_WDT (1<<22) +#define S5P_CLKGATE_IP3_KEYIF (1<<21) +#define S5P_CLKGATE_IP3_UART3 (1<<20) +#define S5P_CLKGATE_IP3_UART2 (1<<19) +#define S5P_CLKGATE_IP3_UART1 (1<<18) +#define S5P_CLKGATE_IP3_UART0 (1<<17) +#define S5P_CLKGATE_IP3_SYSTIMER (1<<16) +#define S5P_CLKGATE_IP3_RTC (1<<15) +#define S5P_CLKGATE_IP3_SPI2 (1<<14) +#define S5P_CLKGATE_IP3_SPI1 (1<<13) +#define S5P_CLKGATE_IP3_SPI0 (1<<12) +#define S5P_CLKGATE_IP3_I2C_HDMI_PHY (1<<11) +#define S5P_CLKGATE_IP3_I2C_HDMI_DDC (1<<10) +#define S5P_CLKGATE_IP3_I2C2 (1<<9) +#define S5P_CLKGATE_IP3_I2C1 (1<<8) +#define S5P_CLKGATE_IP3_I2C0 (1<<7) +#define S5P_CLKGATE_IP3_I2S2 (1<<6) +#define S5P_CLKGATE_IP3_I2S1 (1<<5) +#define S5P_CLKGATE_IP3_I2S0 (1<<4) +#define S5P_CLKGATE_IP3_AC97 (1<<1) +#define S5P_CLKGATE_IP3_SPDIF (1<<0) +#define S5P_CLKGATE_IP3_RESERVED (0x8200000c) +#define S5P_CLKGATE_IP3_ALWAYS_ON ( S5P_CLKGATE_IP3_SYSCON |\ + S5P_CLKGATE_IP3_GPIO |\ + S5P_CLKGATE_IP3_PWM |\ + S5P_CLKGATE_IP3_UART0 |\ + S5P_CLKGATE_IP3_UART1 |\ + S5P_CLKGATE_IP3_UART2 |\ + S5P_CLKGATE_IP3_UART3 |\ + S5P_CLKGATE_IP3_SYSTIMER |\ + S5P_CLKGATE_IP3_I2C0 |\ + S5P_CLKGATE_IP3_I2C1 |\ + S5P_CLKGATE_IP3_I2C2 |\ + S5P_CLKGATE_IP3_RTC ) +#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING +#define S5P_CLKGATE_IP3_BOOT_ON ( 0 ) +#else +#define S5P_CLKGATE_IP3_BOOT_ON ( S5P_CLKGATE_IP3_WDT |\ + S5P_CLKGATE_IP3_KEYIF |\ + S5P_CLKGATE_IP3_I2C_HDMI_PHY ) +#endif + + +/* IP Clock Gate 4 Registers */ +#define S5P_CLKGATE_IP4_TZPC3 (1<<8) +#define S5P_CLKGATE_IP4_TZPC2 (1<<7) +#define S5P_CLKGATE_IP4_TZPC1 (1<<6) +#define S5P_CLKGATE_IP4_TZPC0 (1<<5) +#define S5P_CLKGATE_IP4_SECKEY (1<<3) +#define S5P_CLKGATE_IP4_IEM_APC (1<<2) +#define S5P_CLKGATE_IP4_IEM_IEC (1<<1) +#define S5P_CLKGATE_IP4_CHIP_ID (1<<0) +#define S5P_CLKGATE_IP4_RESERVED (0xfffffe10) +#define S5P_CLKGATE_IP4_ALWAYS_ON ( S5P_CLKGATE_IP4_TZPC3 |\ + S5P_CLKGATE_IP4_TZPC2 |\ + S5P_CLKGATE_IP4_TZPC1 |\ + S5P_CLKGATE_IP4_TZPC0 ) +#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING +#define S5P_CLKGATE_IP4_BOOT_ON ( 0 ) +#else +#define S5P_CLKGATE_IP4_BOOT_ON ( S5P_CLKGATE_IP4_CHIP_ID ) +#endif + + +/* Block Clock Gate Registers */ +#define S5P_CLKGATE_BLOCK_INTC (1<<10) +#define S5P_CLKGATE_BLOCK_HSMMC (1<<9) +#define S5P_CLKGATE_BLOCK_DEBUG (1<<8) +#define S5P_CLKGATE_BLOCK_SECURITY (1<<7) +#define S5P_CLKGATE_BLOCK_MEMORY (1<<6) +#define S5P_CLKGATE_BLOCK_USB (1<<5) +#define S5P_CLKGATE_BLOCK_TV (1<<4) +#define S5P_CLKGATE_BLOCK_LCD (1<<3) +#define S5P_CLKGATE_BLOCK_IMG (1<<2) +#define S5P_CLKGATE_BLOCK_MFC (1<<1) +#define S5P_CLKGATE_BLOCK_G3D (1<<0) + +/* IP Clock Gate 5 Registers */ +#define S5P_CLKGATE_IP5_JPEG (1<<29) +#define S5P_CLKGATE_IP5_RESERVED (0xdfffffff) +#define S5P_CLKGATE_IP5_ALWAYS_ON (0) +#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING +#define S5P_CLKGATE_IP5_BOOT_ON (0) +#else +#define S5P_CLKGATE_IP5_BOOT_ON ( S5P_CLKGATE_IP5_JPEG ) +#endif + +/* Bus Clock Gate Registers (hidden) */ + + +/* CLK_OUT Registers */ +#define S5P_CLKOUT_DIV_SHIFT (20) +#define S5P_CLKOUT_DIV_MASK (0xf << S5P_CLKOUT_DIV_SHIFT) +#define S5P_CLKOUT_CLKSEL_SHIFT (12) +#define S5P_CLKOUT_CLKSEL_MASK (0x1f << S5P_CLKOUT_CLKSEL_SHIFT) +#define S5P_CLKOUT_CLKSEL_APLL (0 << S5P_CLKOUT_CLKSEL_SHIFT) +#define S5P_CLKOUT_CLKSEL_MPLL (1 << S5P_CLKOUT_CLKSEL_SHIFT) +#define S5P_CLKOUT_CLKSEL_EPLL (2 << S5P_CLKOUT_CLKSEL_SHIFT) +#define S5P_CLKOUT_CLKSEL_VPLL (3 << S5P_CLKOUT_CLKSEL_SHIFT) +#define S5P_CLKOUT_CLKSEL_SCLK_USBPHY0 (4 << S5P_CLKOUT_CLKSEL_SHIFT) +#define S5P_CLKOUT_CLKSEL_SCLK_USBPHY1 (5 << S5P_CLKOUT_CLKSEL_SHIFT) +#define S5P_CLKOUT_CLKSEL_SCLK_HDMIPHY (6 << S5P_CLKOUT_CLKSEL_SHIFT) +#define S5P_CLKOUT_CLKSEL_RTC (7 << S5P_CLKOUT_CLKSEL_SHIFT) +#define S5P_CLKOUT_CLKSEL_TICK (8 << S5P_CLKOUT_CLKSEL_SHIFT) +#define S5P_CLKOUT_CLKSEL_HCLK200 (9 << S5P_CLKOUT_CLKSEL_SHIFT) +#define S5P_CLKOUT_CLKSEL_PCLK100 (10 << S5P_CLKOUT_CLKSEL_SHIFT) +#define S5P_CLKOUT_CLKSEL_HCLK166 (11 << S5P_CLKOUT_CLKSEL_SHIFT) +#define S5P_CLKOUT_CLKSEL_PCLK83 (12 << S5P_CLKOUT_CLKSEL_SHIFT) +#define S5P_CLKOUT_CLKSEL_HCLK133 (13 << S5P_CLKOUT_CLKSEL_SHIFT) +#define S5P_CLKOUT_CLKSEL_PCLK66 (14 << S5P_CLKOUT_CLKSEL_SHIFT) +#define S5P_CLKOUT_CLKSEL_ARMCLK (15 << S5P_CLKOUT_CLKSEL_SHIFT) +#define S5P_CLKOUT_CLKSEL_SCLK_HPM (16 << S5P_CLKOUT_CLKSEL_SHIFT) +#define S5P_CLKOUT_CLKSEL_XXTI (17 << S5P_CLKOUT_CLKSEL_SHIFT) +#define S5P_CLKOUT_CLKSEL_XUSBXTI (18 << S5P_CLKOUT_CLKSEL_SHIFT) +#define S5P_CLKOUT_CLKSEL_DOUT (19 << S5P_CLKOUT_CLKSEL_SHIFT) +#define S5P_CLKOUT_DCLKCMP_SHIFT (8) +#define S5P_CLKOUT_DCLKCMP_MASK (0xf << S5P_CLKOUT_DCLKCMP_SHIFT) +#define S5P_CLKOUT_DCLKDIV_SHIFT (4) +#define S5P_CLKOUT_DCLKDIV_MASK (0xf << S5P_CLKOUT_DCLKDIV_SHIFT) +#define S5P_CLKOUT_DCLKSEL_SHIFT (1) +#define S5P_CLKOUT_DCLKSEL_MASK (0x7 << S5P_CLKOUT_DCLKSEL_SHIFT) +#define S5P_CLKOUT_DCLKSEL_XXTI (0 << S5P_CLKOUT_DCLKSEL_SHIFT) +#define S5P_CLKOUT_DCLKSEL_XUSBXTI (1 << S5P_CLKOUT_DCLKSEL_SHIFT) +#define S5P_CLKOUT_DCLKSEL_HDMI27M (2 << S5P_CLKOUT_DCLKSEL_SHIFT) +#define S5P_CLKOUT_DCLKSEL_USBPHY0 (3 << S5P_CLKOUT_DCLKSEL_SHIFT) +#define S5P_CLKOUT_DCLKSEL_USBPHY1 (4 << S5P_CLKOUT_DCLKSEL_SHIFT) +#define S5P_CLKOUT_DCLKSEL_HDMIPHY (5 << S5P_CLKOUT_DCLKSEL_SHIFT) +#define S5P_CLKOUT_DCLKSEL_FOUTEPLL (6 << S5P_CLKOUT_DCLKSEL_SHIFT) +#define S5P_CLKOUT_DCLKSEL_SCLKEPLL (7 << S5P_CLKOUT_DCLKSEL_SHIFT) +#define S5P_CLKOUT_DCLKEN_SHIFT (0) +#define S5P_CLKOUT_DCLKEN_MASK (0x1 << S5P_CLKOUT_DCLKEN_SHIFT) +#define S5P_CLKOUT_DCLKEN_ENABLE (1 << S5P_CLKOUT_DCLKEN_SHIFT) +#define S5P_CLKOUT_DCLKEN_DISABLE (0 << S5P_CLKOUT_DCLKEN_SHIFT) + /* Registers related to power management */ +#define S5P_SWRESET S5P_CLKREG(0x2000) + #define S5P_PWR_CFG S5P_CLKREG(0xC000) #define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0xC004) #define S5P_WAKEUP_MASK S5P_CLKREG(0xC008) @@ -112,8 +557,13 @@ #define S5P_OTHERS S5P_CLKREG(0xE000) #define S5P_OM_STAT S5P_CLKREG(0xE100) +#define S5P_MIE_CONTROL S5P_CLKREG(0xE800) +#define S5P_HDMI_PHY_CONTROL S5P_CLKREG(0xE804) #define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE80C) #define S5P_DAC_CONTROL S5P_CLKREG(0xE810) +#define S5P_MIPI_DPHY_CONTROL S5P_CLKREG(0xE814) +#define S5P_ADC_CONTROL S5P_CLKREG(0xE818) +#define S5P_PS_HOLD_CONTROL S5P_CLKREG(0xE81C) #define S5P_INFORM0 S5P_CLKREG(0xF000) #define S5P_INFORM1 S5P_CLKREG(0xF004) @@ -159,12 +609,25 @@ /* OTHERS Resgister */ #define S5P_OTHERS_USB_SIG_MASK (1 << 16) #define S5P_OTHERS_MIPI_DPHY_EN (1 << 28) +#define S5P_OTHERS_CLKOUT_SHIFT (8) +#define S5P_OTHERS_CLKOUT_MASK (0x3 << S5P_OTHERS_CLKOUT_SHIFT) +#define S5P_OTHERS_CLKOUT_SYSCON (0 << S5P_OTHERS_CLKOUT_SHIFT) +#define S5P_OTHERS_CLKOUT_RESERVED (1 << S5P_OTHERS_CLKOUT_SHIFT) +#define S5P_OTHERS_CLKOUT_XXTI (2 << S5P_OTHERS_CLKOUT_SHIFT) +#define S5P_OTHERS_CLKOUT_XUSBXTI (3 << S5P_OTHERS_CLKOUT_SHIFT) /* MIPI */ -#define S5P_MIPI_DPHY_EN (3) +#define S5P_MIPI_DPHY_EN (3 << 0) + +/* S5P_MIPI_PHY_CON0 */ +#define S5P_MIPI_M_RESETN (1 << 1) /* S5P_DAC_CONTROL */ #define S5P_DAC_ENABLE (1) #define S5P_DAC_DISABLE (0) +#define S5PC110_USB_PHY_CON S5P_CLKREG(0xE80c) +#define S5PC110_USB_PHY0_EN (1 << 0) +#define S5PC110_USB_PHY1_EN (1 << 1) + #endif /* __ASM_ARCH_REGS_CLOCK_H */ -- 1.6.3.3 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 3/6] S5PV210 added register mappings 2010-06-14 8:39 ` [PATCH 2/6] S5PV210 add clock registers " MyungJoo Ham @ 2010-06-14 8:39 ` MyungJoo Ham 2010-06-14 8:39 ` [PATCH 4/6] S5PV210 GPIO relataed registers are added MyungJoo Ham 2010-06-15 5:59 ` [PATCH 3/6] S5PV210 added register mappings Kukjin Kim 2010-06-15 4:20 ` [PATCH 2/6] S5PV210 add clock registers for the CPU Kukjin Kim 1 sibling, 2 replies; 11+ messages in thread From: MyungJoo Ham @ 2010-06-14 8:39 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: MyungJoo Ham <MyungJoo.Ham@samsung.com> --- arch/arm/mach-s5pv210/include/mach/map.h | 45 ++++++++++++++++++++++++++++++ 1 files changed, 45 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h index 34eb168..e1a6ff8 100644 --- a/arch/arm/mach-s5pv210/include/mach/map.h +++ b/arch/arm/mach-s5pv210/include/mach/map.h @@ -54,6 +54,9 @@ #define S5PV210_PA_SROMC (0xE8000000) +/* DMA */ +#define S5PV210_PA_DMA (0xFA200000) +#define S5PV210_PA_PDMA (0xE0900000) #define S5PV210_PA_MDMA 0xFA200000 #define S5PV210_PA_PDMA0 0xE0900000 #define S5PV210_PA_PDMA1 0xE0A00000 @@ -77,6 +80,25 @@ #define S5PV210_PA_SDRAM (0x20000000) #define S5P_PA_SDRAM S5PV210_PA_SDRAM +#define S5PV210_PA_RTC (0xE2800000) + +#define S5PV210_PA_PWR (0xE010C000) +#define S5P_PA_PWR S5PV210_PA_PWR +#define S5P_PA_INFORM0 (S5P_PA_PWR + 0x3000) + +/* USB HS OTG */ +#define S5PV210_PA_USB_HSOTG (0xEC000000) +#define S5PV210_PA_USB_HSPHY (0xEC100000) + +/* FIMC */ +#define S5PV210_PA_FIMC0 (0xFB200000) +#define S5PV210_PA_FIMC1 (0xFB300000) +#define S5PV210_PA_FIMC2 (0xFB400000) + +/* MFC */ +#define S5PV210_PA_MFC (0xF1700000) +#define S5PV210_SZ_MFC (0x0000FFFF) + /* I2S */ #define S5PV210_PA_IIS0 0xEEE30000 #define S5PV210_PA_IIS1 0xE2100000 @@ -87,6 +109,17 @@ #define S5PV210_PA_PCM1 0xE1200000 #define S5PV210_PA_PCM2 0xE2B00000 +/* Audio SubSystem */ +#define S5PV210_PA_AUDSS (0xEEE10000) + +/* TZPC */ +#define S5PV210_PA_TZPC0 (0xF1500000) +#define S5PV210_PA_TZPC1 (0xFAD00000) +#define S5PV210_PA_TZPC2 (0xE0600000) +#define S5PV210_PA_TZPC3 (0xE1C00000) + +#define S5PV210_VA_TZPC(x) (S3C_ADDR(0x01700000) + ((x) * 0x10000)) + /* AC97 */ #define S5PV210_PA_AC97 0xE2200000 @@ -101,6 +134,18 @@ #define S3C_PA_IIC1 S5PV210_PA_IIC1 #define S3C_PA_IIC2 S5PV210_PA_IIC2 #define S3C_PA_FB S5PV210_PA_FB +#define S3C_PA_USB_HSOTG S5PV210_PA_USB_HSOTG +#define S3C_PA_USB_HSPHY S5PV210_PA_USB_HSPHY +#define S3C_PA_RTC S5PV210_PA_RTC +#define S5P_PA_FIMC0 S5PV210_PA_FIMC0 +#define S5P_PA_FIMC1 S5PV210_PA_FIMC1 +#define S5P_PA_FIMC2 S5PV210_PA_FIMC2 +#define S3C_PA_DMA S5PV210_PA_DMA +#define S3C_PA_PDMA S5PV210_PA_PDMA +#define S3C_PA_IIS_V50 S5PV210_PA_IIS0 +#define S3C_PA_ADC S5PV210_PA_ADC(0) +#define S3C_PA_ADC0 S5PV210_PA_ADC(0) +#define S3C_PA_ADC1 S5PV210_PA_ADC(1) #define S3C_PA_WDT S5PV210_PA_WATCHDOG #define SAMSUNG_PA_ADC S5PV210_PA_ADC -- 1.6.3.3 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 4/6] S5PV210 GPIO relataed registers are added. 2010-06-14 8:39 ` [PATCH 3/6] S5PV210 added register mappings MyungJoo Ham @ 2010-06-14 8:39 ` MyungJoo Ham 2010-06-14 8:39 ` [PATCH 5/6] S5PV210 added EINT-GPIO register mappings MyungJoo Ham 2010-06-15 5:59 ` [PATCH 3/6] S5PV210 added register mappings Kukjin Kim 1 sibling, 1 reply; 11+ messages in thread From: MyungJoo Ham @ 2010-06-14 8:39 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: MyungJoo Ham <MyungJoo.Ham@samsung.com> --- arch/arm/mach-s5pv210/include/mach/regs-gpio.h | 121 ++++++++++++++++++++++++ 1 files changed, 121 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h index 49e029b..d0dc78f 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h @@ -45,4 +45,125 @@ #define EINT_GPIO_2(x) S5PV210_GPH2(x) #define EINT_GPIO_3(x) S5PV210_GPH3(x) +#define S5PV210_GPIO_BASE S5P_VA_GPIO + +#define S5PV210_ETC0PUD (S5PV210_GPIO_BASE + 0x0608) +#define S5PV210_ETC0DRV (S5PV210_GPIO_BASE + 0x060C) +#define S5PV210_ETC1PUD (S5PV210_GPIO_BASE + 0x0628) +#define S5PV210_ETC1DRV (S5PV210_GPIO_BASE + 0x062C) +#define S5PV210_ETC2PUD (S5PV210_GPIO_BASE + 0x0648) +#define S5PV210_ETC2DRV (S5PV210_GPIO_BASE + 0x064C) + +#define S5PV210_GPA0_INT_CON (S5PV210_GPIO_BASE + 0x0700) +#define S5PV210_GPA1_INT_CON (S5PV210_GPIO_BASE + 0x0704) +#define S5PV210_GPB_INT_CON (S5PV210_GPIO_BASE + 0x0708) +#define S5PV210_GPC0_INT_CON (S5PV210_GPIO_BASE + 0x070C) +#define S5PV210_GPC1_INT_CON (S5PV210_GPIO_BASE + 0x0710) +#define S5PV210_GPD0_INT_CON (S5PV210_GPIO_BASE + 0x0714) +#define S5PV210_GPD1_INT_CON (S5PV210_GPIO_BASE + 0x0718) +#define S5PV210_GPE0_INT_CON (S5PV210_GPIO_BASE + 0x071C) +#define S5PV210_GPE1_INT_CON (S5PV210_GPIO_BASE + 0x0720) +#define S5PV210_GPF0_INT_CON (S5PV210_GPIO_BASE + 0x0724) +#define S5PV210_GPF1_INT_CON (S5PV210_GPIO_BASE + 0x0728) +#define S5PV210_GPF2_INT_CON (S5PV210_GPIO_BASE + 0x072C) +#define S5PV210_GPF3_INT_CON (S5PV210_GPIO_BASE + 0x0730) +#define S5PV210_GPG0_INT_CON (S5PV210_GPIO_BASE + 0x0734) +#define S5PV210_GPG1_INT_CON (S5PV210_GPIO_BASE + 0x0738) +#define S5PV210_GPG2_INT_CON (S5PV210_GPIO_BASE + 0x073C) +#define S5PV210_GPG3_INT_CON (S5PV210_GPIO_BASE + 0x0740) +#define S5PV210_GPJ0_INT_CON (S5PV210_GPIO_BASE + 0x0744) +#define S5PV210_GPJ1_INT_CON (S5PV210_GPIO_BASE + 0x0748) +#define S5PV210_GPJ2_INT_CON (S5PV210_GPIO_BASE + 0x074C) +#define S5PV210_GPJ3_INT_CON (S5PV210_GPIO_BASE + 0x0750) +#define S5PV210_GPJ4_INT_CON (S5PV210_GPIO_BASE + 0x0754) + +#define S5PV210_GPA0_INT_MASK (S5PV210_GPIO_BASE + 0x0900) +#define S5PV210_GPA1_INT_MASK (S5PV210_GPIO_BASE + 0x0904) +#define S5PV210_GPB_INT_MASK (S5PV210_GPIO_BASE + 0x0908) +#define S5PV210_GPC0_INT_MASK (S5PV210_GPIO_BASE + 0x090C) +#define S5PV210_GPC1_INT_MASK (S5PV210_GPIO_BASE + 0x0910) +#define S5PV210_GPD0_INT_MASK (S5PV210_GPIO_BASE + 0x0914) +#define S5PV210_GPD1_INT_MASK (S5PV210_GPIO_BASE + 0x0918) +#define S5PV210_GPE0_INT_MASK (S5PV210_GPIO_BASE + 0x091C) +#define S5PV210_GPE1_INT_MASK (S5PV210_GPIO_BASE + 0x0920) +#define S5PV210_GPF0_INT_MASK (S5PV210_GPIO_BASE + 0x0924) +#define S5PV210_GPF1_INT_MASK (S5PV210_GPIO_BASE + 0x0928) +#define S5PV210_GPF2_INT_MASK (S5PV210_GPIO_BASE + 0x092C) +#define S5PV210_GPF3_INT_MASK (S5PV210_GPIO_BASE + 0x0930) +#define S5PV210_GPG0_INT_MASK (S5PV210_GPIO_BASE + 0x0934) +#define S5PV210_GPG1_INT_MASK (S5PV210_GPIO_BASE + 0x0938) +#define S5PV210_GPG2_INT_MASK (S5PV210_GPIO_BASE + 0x093C) +#define S5PV210_GPG3_INT_MASK (S5PV210_GPIO_BASE + 0x0940) +#define S5PV210_GPJ0_INT_MASK (S5PV210_GPIO_BASE + 0x0944) +#define S5PV210_GPJ1_INT_MASK (S5PV210_GPIO_BASE + 0x0948) +#define S5PV210_GPJ2_INT_MASK (S5PV210_GPIO_BASE + 0x094C) +#define S5PV210_GPJ3_INT_MASK (S5PV210_GPIO_BASE + 0x0950) +#define S5PV210_GPJ4_INT_MASK (S5PV210_GPIO_BASE + 0x0954) + +#define S5PV210_GPA0_INT_PEND (S5PV210_GPIO_BASE + 0x0a00) +#define S5PV210_GPA1_INT_PEND (S5PV210_GPIO_BASE + 0x0a04) +#define S5PV210_GPB_INT_PEND (S5PV210_GPIO_BASE + 0x0a08) +#define S5PV210_GPC0_INT_PEND (S5PV210_GPIO_BASE + 0x0a0C) +#define S5PV210_GPC1_INT_PEND (S5PV210_GPIO_BASE + 0x0a10) +#define S5PV210_GPD0_INT_PEND (S5PV210_GPIO_BASE + 0x0a14) +#define S5PV210_GPD1_INT_PEND (S5PV210_GPIO_BASE + 0x0a18) +#define S5PV210_GPE0_INT_PEND (S5PV210_GPIO_BASE + 0x0a1C) +#define S5PV210_GPE1_INT_PEND (S5PV210_GPIO_BASE + 0x0a20) +#define S5PV210_GPF0_INT_PEND (S5PV210_GPIO_BASE + 0x0a24) +#define S5PV210_GPF1_INT_PEND (S5PV210_GPIO_BASE + 0x0a28) +#define S5PV210_GPF2_INT_PEND (S5PV210_GPIO_BASE + 0x0a2C) +#define S5PV210_GPF3_INT_PEND (S5PV210_GPIO_BASE + 0x0a30) +#define S5PV210_GPG0_INT_PEND (S5PV210_GPIO_BASE + 0x0a34) +#define S5PV210_GPG1_INT_PEND (S5PV210_GPIO_BASE + 0x0a38) +#define S5PV210_GPG2_INT_PEND (S5PV210_GPIO_BASE + 0x0a3C) +#define S5PV210_GPG3_INT_PEND (S5PV210_GPIO_BASE + 0x0a40) +#define S5PV210_GPJ0_INT_PEND (S5PV210_GPIO_BASE + 0x0a44) +#define S5PV210_GPJ1_INT_PEND (S5PV210_GPIO_BASE + 0x0a48) +#define S5PV210_GPJ2_INT_PEND (S5PV210_GPIO_BASE + 0x0a4C) +#define S5PV210_GPJ3_INT_PEND (S5PV210_GPIO_BASE + 0x0a50) +#define S5PV210_GPJ4_INT_PEND (S5PV210_GPIO_BASE + 0x0a54) + +#define S5PV210_GPIO_INT_GRPPRI (S5PV210_GPIO_BASE + 0x0b00) +#define S5PV210_GPIO_INT_PRIORITY (S5PV210_GPIO_BASE + 0x0b04) +#define S5PV210_GPIO_INT_SERVICE (S5PV210_GPIO_BASE + 0x0b08) +#define S5PV210_GPIO_INT_SERVICE_PEND (S5PV210_GPIO_BASE + 0x0b0c) +#define S5PV210_GPIO_INT_GRPFIXPRI (S5PV210_GPIO_BASE + 0x0b10) + +#define S5PV210_GPA0_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b14) +#define S5PV210_GPA1_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b18) +#define S5PV210_GPB_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b1c) +#define S5PV210_GPC0_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b20) +#define S5PV210_GPC1_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b24) +#define S5PV210_GPD0_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b28) +#define S5PV210_GPD1_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b2c) +#define S5PV210_GPE0_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b30) +#define S5PV210_GPE1_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b34) +#define S5PV210_GPF0_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b38) +#define S5PV210_GPF1_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b3c) +#define S5PV210_GPF2_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b40) +#define S5PV210_GPF3_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b44) +#define S5PV210_GPG0_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b48) +#define S5PV210_GPG1_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b4c) +#define S5PV210_GPG2_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b50) +#define S5PV210_GPG3_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b54) +#define S5PV210_GPJ0_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b58) +#define S5PV210_GPJ1_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b5c) +#define S5PV210_GPJ2_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b60) +#define S5PV210_GPJ3_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b64) +#define S5PV210_GPJ4_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b68) + + +#define S5PV210_EXT_INT_BASE (S5PV210_GPIO_BASE + 0x0E00) +#define S5PV210_PDNEN (S5PV210_GPIO_BASE + 0x0F80) +#define S5PC100_PDNEN_NORMAL (0 << 0) + +#define S5PV210_PDNEN_CFG_PDNEN (1 << 1) +#define S5PV210_PDNEN_CFG_AUTO (0 << 1) +#define S5PV210_PDNEN_POWERDOWN (1 << 0) +#define S5PV210_PDNEN_NORMAL (0 << 0) + +/* Common part */ +#define S5P_EINT_BASE (S5PV210_EXT_INT_BASE) + + #endif /* __ASM_ARCH_REGS_GPIO_H */ -- 1.6.3.3 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 5/6] S5PV210 added EINT-GPIO register mappings 2010-06-14 8:39 ` [PATCH 4/6] S5PV210 GPIO relataed registers are added MyungJoo Ham @ 2010-06-14 8:39 ` MyungJoo Ham 2010-06-14 8:39 ` [PATCH 6/6] S5PV210 PM Support Main (suspend-to-mem) MyungJoo Ham 0 siblings, 1 reply; 11+ messages in thread From: MyungJoo Ham @ 2010-06-14 8:39 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: MyungJoo Ham <MyungJoo.Ham@samsung.com> --- arch/arm/plat-s5p/include/plat/gpio-ext.h | 44 +++++++++++++++++++++++++++++ 1 files changed, 44 insertions(+), 0 deletions(-) create mode 100644 arch/arm/plat-s5p/include/plat/gpio-ext.h diff --git a/arch/arm/plat-s5p/include/plat/gpio-ext.h b/arch/arm/plat-s5p/include/plat/gpio-ext.h new file mode 100644 index 0000000..b298335 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/gpio-ext.h @@ -0,0 +1,44 @@ +/* linux/arch/arm/plat-s5p/include/plat/gpio-eint.h + * + * Copyright 2009 Samsung Electronics Co. + * + * External Interrupt (GPH0 ~ GPH3) control register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S5P_WKUP_INT_CON0_7 (S5P_EINT_BASE + 0x0) +#define S5P_WKUP_INT_CON8_15 (S5P_EINT_BASE + 0x4) +#define S5P_WKUP_INT_CON16_23 (S5P_EINT_BASE + 0x8) +#define S5P_WKUP_INT_CON24_31 (S5P_EINT_BASE + 0xC) +#define S5P_WKUP_INT_CON(x) (S5P_WKUP_INT_CON0_7 + (x * 0x4)) + +#define S5P_WKUP_INT_FLTCON0_3 (S5P_EINT_BASE + 0x80) +#define S5P_WKUP_INT_FLTCON4_7 (S5P_EINT_BASE + 0x84) +#define S5P_WKUP_INT_FLTCON8_11 (S5P_EINT_BASE + 0x88) +#define S5P_WKUP_INT_FLTCON12_15 (S5P_EINT_BASE + 0x8C) +#define S5P_WKUP_INT_FLTCON16_19 (S5P_EINT_BASE + 0x90) +#define S5P_WKUP_INT_FLTCON20_23 (S5P_EINT_BASE + 0x94) +#define S5P_WKUP_INT_FLTCON24_27 (S5P_EINT_BASE + 0x98) +#define S5P_WKUP_INT_FLTCON28_31 (S5P_EINT_BASE + 0x9C) +#define S5P_WKUP_INT_FLTCON(x) (S5P_WKUP_INT_FLTCON0_3 + (x * 0x4)) + +#define S5P_WKUP_INT_MASK0_7 (S5P_EINT_BASE + 0x100) +#define S5P_WKUP_INT_MASK8_15 (S5P_EINT_BASE + 0x104) +#define S5P_WKUP_INT_MASK16_23 (S5P_EINT_BASE + 0x108) +#define S5P_WKUP_INT_MASK24_31 (S5P_EINT_BASE + 0x10C) +#define S5P_WKUP_INT_MASK(x) (S5P_WKUP_INT_MASK0_7 + (x * 0x4)) + +#define S5P_WKUP_INT_PEND0_7 (S5P_EINT_BASE + 0x140) +#define S5P_WKUP_INT_PEND8_15 (S5P_EINT_BASE + 0x144) +#define S5P_WKUP_INT_PEND16_23 (S5P_EINT_BASE + 0x148) +#define S5P_WKUP_INT_PEND24_31 (S5P_EINT_BASE + 0x14C) +#define S5P_WKUP_INT_PEND(x) (S5P_WKUP_INT_PEND0_7 + (x * 0x4)) + +#define S5P_WKUP_INT_LOWLEV (0x00) +#define S5P_WKUP_INT_HILEV (0x01) +#define S5P_WKUP_INT_FALLEDGE (0x02) +#define S5P_WKUP_INT_RISEEDGE (0x03) +#define S5P_WKUP_INT_BOTHEDGE (0x04) -- 1.6.3.3 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 6/6] S5PV210 PM Support Main (suspend-to-mem) 2010-06-14 8:39 ` [PATCH 5/6] S5PV210 added EINT-GPIO register mappings MyungJoo Ham @ 2010-06-14 8:39 ` MyungJoo Ham 0 siblings, 0 replies; 11+ messages in thread From: MyungJoo Ham @ 2010-06-14 8:39 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: MyungJoo Ham <MyungJoo.Ham@samsung.com> --- arch/arm/mach-s5pv210/Makefile | 4 + arch/arm/plat-s5p/Makefile | 3 + arch/arm/plat-s5p/include/plat/map-s5p.h | 1 + arch/arm/plat-s5p/sleep.S | 248 ++++++++++++++++++++++++++ arch/arm/plat-samsung/include/plat/pm-core.h | 53 ++++++ arch/arm/plat-samsung/include/plat/pm.h | 13 ++ arch/arm/plat-samsung/pm-gpio.c | 4 +- arch/arm/plat-samsung/pm.c | 75 +++++++- 8 files changed, 392 insertions(+), 9 deletions(-) create mode 100644 arch/arm/plat-s5p/sleep.S create mode 100644 arch/arm/plat-samsung/include/plat/pm-core.h diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile index 30be9a6..16ca1e9 100644 --- a/arch/arm/mach-s5pv210/Makefile +++ b/arch/arm/mach-s5pv210/Makefile @@ -33,3 +33,7 @@ obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o obj-$(CONFIG_S5PV210_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o + +# power management support + +obj-$(CONFIG_PM) += pm.o diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile index 39c242b..578a4e5 100644 --- a/arch/arm/plat-s5p/Makefile +++ b/arch/arm/plat-s5p/Makefile @@ -18,3 +18,6 @@ obj-y += clock.o obj-y += irq.o obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o +# CPU support + +obj-$(CONFIG_PM) += sleep.o diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h index 1482852..20b8524 100644 --- a/arch/arm/plat-s5p/include/plat/map-s5p.h +++ b/arch/arm/plat-s5p/include/plat/map-s5p.h @@ -24,6 +24,7 @@ #define S5P_VA_UART3 (S3C_VA_UART + 0xC00) #define S3C_UART_OFFSET (0x400) +#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) #define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000)) #define VA_VIC0 VA_VIC(0) diff --git a/arch/arm/plat-s5p/sleep.S b/arch/arm/plat-s5p/sleep.S new file mode 100644 index 0000000..a1e038b --- /dev/null +++ b/arch/arm/plat-s5p/sleep.S @@ -0,0 +1,248 @@ +/* linux/arch/arm/plat-s5pc1xx/sleep.S + * + * S5PC1XX Power Manager (Suspend-To-RAM) support + * + * Based on plat-s3c64xx sleep code + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <mach/hardware.h> +#include <mach/map.h> + +#include <mach/regs-gpio.h> +#include <mach/regs-clock.h> +#include <plat/regs-serial.h> +#include <asm/memory.h> + + .text + + /* s3c_cpu_save + * + * save enough of the CPU state to allow us to re-start + * pm.c code. as we store items like the sp/lr, we will + * end up returning from this function when the cpu resumes + * so the return value is set to mark this. + * + * This arangement means we avoid having to flush the cache + * from this code. + * + * entry: + * r0 = pointer to save block + * + */ + +ENTRY(s3c_cpu_save) + stmfd sp!, { r3 - r12, lr } + + mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID + mrc p15, 0, r5, c3, c0, 0 @ Domain ID + mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 + mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 + mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control + mrc p15, 0, r9, c1, c0, 0 @ Control register + mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register + mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls + mrc p15, 0, r12, c10, c2, 0 @ Read PRRR + mrc p15, 0, r3, c10, c2, 1 @ READ NMRR + + ARM( stmia r0, { r3 - r13 } ) @ Save CP registers and SP + THUMB( stmia r0, { r3 - r12 } ) @ Save CP registers and SP + THUMB( str sp, [ r0, #40 ] ) + + + /* save our state to ram */ + bl s3c_pm_cb_flushcache + + /* call final suspend code */ + ldr r0, =pm_cpu_sleep + @@ldr pc, [r0] + ldr r0, [r0] + mov pc, r0 + + @@ return to the caller, after having the MMU + @@ turned on, this restores the last bits from the + @@ stack + + .global resume_with_mmu +resume_with_mmu: + + /* delete added mmu table list */ + ldr r9 , =(PAGE_OFFSET - PHYS_OFFSET) + add r4, r4, r9 + str r12, [r4] + + ldmfd sp!, { r3 - r12, pc } @ return, from sp from s3c_cpu_save + + .ltorg + + @@ the next bits sit in the .data segment, even though they + @@ happen to be code... the s3c_sleep_save_phys needs to be + @@ accessed by the resume code before it can restore the MMU. + @@ This means that the variable has to be close enough for the + @@ code to read it... since the .text segment needs to be RO, + @@ the data segment can be the only place to put this code. + + .data + + .global s3c_sleep_save_phys +s3c_sleep_save_phys: + .word 0 + + /* sleep magic, to allow the bootloader to check for an valid + * image to resume to. Must be the first word before the + * s3c_cpu_resume entry. + */ + + .word 0x2bedf00d + + /* s3c_cpu_resume + * + * resume code entry for bootloader to call + * + * we must put this code here in the data segment as we have no + * other way of restoring the stack pointer after sleep, and we + * must not write to the code segment (code is read-only) + */ + +ENTRY(s3c_cpu_resume) + mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE + msr cpsr_c, r0 + + /* Debug + * + * Serial port configuration code + * Use when low-level debug functionality is needed before UARTs + * configuratio is restored + * It utilizes low-level kernel debug functions (printch,printhex), + * so please enable them at kernel config + * This code was used with S5PC110 !!! + */ +#ifdef CONFIG_SAMSUNG_PM_DEBUG + ldr r0, =S5P_PA_GPIO + ldr r1, =0x22222222 + str r1, [r0, #0x0] @S5PC1XX_GPIO_A0_OFFSET + ldr r1, =0x00002222 + str r1, [r0, #0x20] @S5PC1XX_GPIO_A1_OFFSET + + /* UART_SEL MP0_5[7] at S5PC110 */ + add r0, r0, #0x360 @S5PC1XX_GPIO_MP0_5_OFFSET + ldr r1, [r0, #0x0] @S5PC1XX_GPIO_CON_OFFSET + bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit + orr r1, r1, #(0x1 << 28) @ Output + str r1, [r0, #0x0] @S5PC1XX_GPIO_CON_OFFSET + + ldr r1, [r0, #0x8] @S5PC1XX_GPIO_PULL_OFFSET + bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit + orr r1, r1, #(0x2 << 14) @ Pull-up enabled + str r1, [r0, #0x8] @S5PC1XX_GPIO_PULL_OFFSET + + ldr r1, [r0, #0x4] @S5PC1XX_GPIO_DAT_OFFSET + orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit + str r1, [r0, #0x4] @S5PC1XX_GPIO_DAT_OFFSET + + ldr r0, =S3C_PA_UART @ S5PC110_PA_UART + add r0, r0, #(0x400 * CONFIG_DEBUG_S3C_UART) @ + mov r1, #0x3 + str r1, [r0, #0x000] @ ULCON + ldr r1, =0x245 + str r1, [r0, #0x004] @ UCON + mov r1, #0x23 + str r1, [r0, #0x028] @ UBRDIV + mov r1, #0x3 + str r1, [r0, #0x02C] @ UDIVSLOT + + mov r0, #'_' + bl printch + + mov r0, #'_' + bl printch + + mov r0, #'W' + bl printch + + mov r0, #'_' + bl printch + + mov r0, #'_' + bl printch + + mov r0, #'\n' + bl printch + +#endif + mov r1, #0 + mcr p15, 0, r1, c8, c7, 0 @ Invalidate TLBs + mcr p15, 0, r1, c7, c5, 0 @ Invalidate I Cache + + ARM( ldr r0, s3c_sleep_save_phys ) + THUMB( adr.w r0, s3c_sleep_save_phys ) + THUMB( ldr r0, [r0] ) + + ARM( ldmia r0, { r3 - r13 } ) @ reload regs and SPI + THUMB( ldmia r0, { r3 - r12 } ) @ reload regs and SPI + THUMB( ldr sp, [ r0, #40 ] ) + + mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID + mcr p15, 0, r5, c3, c0, 0 @ Domain ID + mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control + mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 + mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 + mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register + + mov r0, #0 + mcr p15, 0, r0, c8, c7, 0 @ Invalidate I & D TLB + + mov r0, #0 + mcr p15, 0, r11, c1, c0, 2 @ Co-processor access controls + mcr p15, 0, r0, c7, c5, 4 + + mcr p15, 0, r12, c10, c2, 0 @ write PRRR + mcr p15, 0, r3, c10, c2, 1 @ write NMRR + + + /* calculate first section address into r8 */ + mov r4, r6 + ldr r5, =0x3fff + bic r4, r4, r5 + /* read data from INFORM0 */ + ldr r11, =S5P_PA_INFORM0 + + ldr r10, [r11, #0] + mov r10, r10 ,LSR #18 + bic r10, r10, #0x3 + orr r4, r4, r10 + + /* calculate mmu list value into r9 */ + mov r10, r10, LSL #18 + ldr r5, =0x40e + orr r10, r10, r5 + + /* back up originally data */ + + ldr r12, [r4] + + /* Added list about mmu */ + str r10, [r4] + + ldr r2, =resume_with_mmu + mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, etc + + isb + mov pc, r2 @ go back to virtual address + + .ltorg diff --git a/arch/arm/plat-samsung/include/plat/pm-core.h b/arch/arm/plat-samsung/include/plat/pm-core.h new file mode 100644 index 0000000..df282c5 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/pm-core.h @@ -0,0 +1,53 @@ +/* linux/arch/arm/plat-s5pc1xx/include/plat/pm-core.h + * + * S5PC1XX - PM core support for arch/arm/plat-s3c/pm.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <mach/regs-gpio.h> +#include <mach/regs-clock.h> +#include <plat/cpu.h> + +#define s3c_irqwake_eintallow (ULONG_MAX) +#define s3c_irqwake_intallow (0) + +static inline void s3c_pm_debug_init_uart(void) +{ + u32 tmp = __raw_readl(S5P_CLKGATE_IP3); + + /* As a note, since the S5PC1XX UARTs generally have multiple + * clock sources, we simply enable PCLK at the moment and hope + * that the resume settings for the UART are suitable for the + * use with PCLK. + */ + + tmp |= S5P_CLKGATE_IP3_UART0; + tmp |= S5P_CLKGATE_IP3_UART1; + tmp |= S5P_CLKGATE_IP3_UART2; + tmp |= S5P_CLKGATE_IP3_UART3; + + __raw_writel(tmp, S5P_CLKGATE_IP3); + udelay(10); +} + +static inline void s3c_pm_arch_prepare_irqs(void) +{ +} + +static inline void s3c_pm_arch_stop_clocks(void) +{ +} + +static inline void s3c_pm_arch_show_resume_irqs(void) +{ + S3C_PMDBG("sleep: wakeup source (WAKEUP_STAT): %8.8xh\n", + __raw_readl(S5P_WAKEUP_STAT)); +} + +static inline void s3c_pm_arch_update_uart(void __iomem *regs, + struct pm_uart_save *save) +{ +} diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index 245836d..ac0bc65 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -39,6 +39,7 @@ extern unsigned long s3c_irqwake_eintallow; extern void (*pm_cpu_prep)(void); extern void (*pm_cpu_sleep)(void); +extern void (*pm_cpu_finish)(void); /* Flags for PM Control */ @@ -73,6 +74,12 @@ struct sleep_save { #define SAVE_ITEM(x) \ { .reg = (x) } +#define SAVE_GPIO_INT(x) \ + SAVE_ITEM((x)), \ + SAVE_ITEM((x) + 0x100), \ + SAVE_ITEM((x) + 0x200), \ + SAVE_ITEM((x) + 0x300) + /** * struct pm_uart_save - save block for core UART * @ulcon: Save value for S3C2410_ULCON @@ -161,6 +168,9 @@ extern void s3c_pm_check_store(void); */ extern void s3c_pm_configure_extint(void); +extern void s3c_pm_configure_int(void); + + /** * s3c_pm_restore_gpios() - restore the state of the gpios after sleep. * @@ -187,3 +197,6 @@ extern void s3c_pm_cb_flushcache(void); extern void s3c_pm_save_core(void); extern void s3c_pm_restore_core(void); + +extern void s3c_pm_wakeup_source(unsigned int *internal, + unsigned int *external); diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c index 7df03f8..1b9529a 100644 --- a/arch/arm/plat-samsung/pm-gpio.c +++ b/arch/arm/plat-samsung/pm-gpio.c @@ -192,7 +192,7 @@ struct s3c_gpio_pm s3c_gpio_pm_2bit = { .resume = s3c_gpio_pm_2bit_resume, }; -#ifdef CONFIG_ARCH_S3C64XX +#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_ARCH_S5PV210) static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip) { chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); @@ -302,7 +302,7 @@ struct s3c_gpio_pm s3c_gpio_pm_4bit = { .save = s3c_gpio_pm_4bit_save, .resume = s3c_gpio_pm_4bit_resume, }; -#endif /* CONFIG_ARCH_S3C64XX */ +#endif /* CONFIG_ARCH_S3C64XX || CONFIG_ARCH_S5PV210 */ /** * s3c_pm_save_gpio() - save gpio chip data for suspend diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index 27cfca5..503e3bd 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c @@ -26,10 +26,16 @@ #include <plat/regs-serial.h> #include <mach/regs-clock.h> #include <mach/regs-irq.h> +#include <mach/irqs.h> #include <asm/irq.h> #include <plat/pm.h> +#ifdef CONFIG_CPU_S5PV210 +#include <plat/pm-core.h> +#else #include <mach/pm-core.h> +#endif +#include <plat/gpio-ext.h> /* for external use */ @@ -231,6 +237,27 @@ static void s3c_pm_show_resume_irqs(int start, unsigned long which, void (*pm_cpu_prep)(void); void (*pm_cpu_sleep)(void); +void (*pm_cpu_finish)(void); + +unsigned int s3c_pm_wakeup_source_save_int; +unsigned int s3c_pm_wakeup_source_save_ext; +static void s3c_pm_wakeup_source_set(unsigned int internal, + unsigned int external) +{ + s3c_pm_wakeup_source_save_int = internal & ~s3c_irqwake_intmask; + if (internal & 0x01) + s3c_pm_wakeup_source_save_ext = external & + ~s3c_irqwake_eintmask; + else + s3c_pm_wakeup_source_save_ext = 0; +} + +void s3c_pm_wakeup_source(unsigned int *internal, + unsigned int *external) +{ + *internal = s3c_pm_wakeup_source_save_int; + *external = s3c_pm_wakeup_source_save_ext; +} #define any_allowed(mask, allow) (((mask) & (allow)) != (allow)) @@ -259,6 +286,11 @@ static int s3c_pm_enter(suspend_state_t state) * require a full power-cycle) */ + /* set the irq configuration for wake */ + s3c_irqwake_intmask = 0xFFDD; + s3c_pm_configure_int(); + s3c_pm_configure_extint(); + if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) && !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) { printk(KERN_ERR "%s: No wake-up sources!\n", __func__); @@ -270,19 +302,20 @@ static int s3c_pm_enter(suspend_state_t state) s3c_sleep_save_phys = virt_to_phys(regs_save); - S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys); - /* save all necessary core registers not covered by the drivers */ s3c_pm_save_gpios(); s3c_pm_save_uarts(); s3c_pm_save_core(); - /* set the irq configuration for wake */ - s3c_pm_configure_extint(); + /* For the future use with deep idle */ + __raw_writel(virt_to_phys(regs_save), S5P_INFORM2); + __raw_writel(0, S5P_INFORM1); + + S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys); - S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n", + S3C_PMDBG("sleep: IRQ wakeup masks: %08lx,%08lx\n", s3c_irqwake_intmask, s3c_irqwake_eintmask); s3c_pm_arch_prepare_irqs(); @@ -312,11 +345,11 @@ static int s3c_pm_enter(suspend_state_t state) cpu_init(); /* restore the system state */ - s3c_pm_restore_core(); s3c_pm_restore_uarts(); s3c_pm_restore_gpios(); + s3c_pm_debug_init(); /* check what irq (if any) restored the system */ @@ -325,11 +358,36 @@ static int s3c_pm_enter(suspend_state_t state) S3C_PMDBG("%s: post sleep, preparing to return\n", __func__); + __raw_writel(__raw_readl(S5P_OTHERS) | (1<<31) | (1<<30) | (1<<29) | + (1<<28), S5P_OTHERS); + + /* WAKEUP STAT */ + printk(KERN_INFO "Wakeup Stat: %8.8xh\n", __raw_readl(S5P_WAKEUP_STAT)); + /* LEDs should now be 1110 */ s3c_pm_debug_smdkled(1 << 1, 0); s3c_pm_check_restore(); + /* If ext int is the wakeup source... */ + if (__raw_readl(S5P_WAKEUP_STAT) & 0x01) { /* EXTINT */ + /* If HOME or HOLD key pressed, trigger an event manually */ + + S3C_PMDBG("EXT INT SOURCE = %2.2x %2.2x %2.2x %2.2x\n", + __raw_readl(S5P_WKUP_INT_PEND24_31), + __raw_readl(S5P_WKUP_INT_PEND16_23), + __raw_readl(S5P_WKUP_INT_PEND8_15), + __raw_readl(S5P_WKUP_INT_PEND0_7)); + + s3c_pm_wakeup_source_set(__raw_readl(S5P_WAKEUP_STAT), + __raw_readl(S5P_WKUP_INT_PEND24_31)<<24 | + __raw_readl(S5P_WKUP_INT_PEND16_23)<<16 | + __raw_readl(S5P_WKUP_INT_PEND8_15)<<8 | + __raw_readl(S5P_WKUP_INT_PEND0_7)<<0); + } + else + s3c_pm_wakeup_source_set(__raw_readl(S5P_WAKEUP_STAT), 0); + /* ok, let's return from sleep */ S3C_PMDBG("S3C PM Resume (post-restore)\n"); @@ -353,11 +411,14 @@ static int s3c_pm_prepare(void) static void s3c_pm_finish(void) { s3c_pm_check_cleanup(); + + if (pm_cpu_finish) + pm_cpu_finish(); } static struct platform_suspend_ops s3c_pm_ops = { - .enter = s3c_pm_enter, .prepare = s3c_pm_prepare, + .enter = s3c_pm_enter, .finish = s3c_pm_finish, .valid = suspend_valid_only_mem, }; -- 1.6.3.3 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 3/6] S5PV210 added register mappings 2010-06-14 8:39 ` [PATCH 3/6] S5PV210 added register mappings MyungJoo Ham 2010-06-14 8:39 ` [PATCH 4/6] S5PV210 GPIO relataed registers are added MyungJoo Ham @ 2010-06-15 5:59 ` Kukjin Kim 1 sibling, 0 replies; 11+ messages in thread From: Kukjin Kim @ 2010-06-15 5:59 UTC (permalink / raw) To: linux-arm-kernel MyungJoo Ham wrote: > Where is commit message? Needs comment why this patch needs. > Signed-off-by: MyungJoo Ham <MyungJoo.Ham@samsung.com> > --- > arch/arm/mach-s5pv210/include/mach/map.h | 45 > ++++++++++++++++++++++++++++++ > 1 files changed, 45 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach- > s5pv210/include/mach/map.h > index 34eb168..e1a6ff8 100644 > --- a/arch/arm/mach-s5pv210/include/mach/map.h > +++ b/arch/arm/mach-s5pv210/include/mach/map.h > @@ -54,6 +54,9 @@ > > #define S5PV210_PA_SROMC (0xE8000000) > > +/* DMA */ No need above comment. We know _PA_DMA means physical address of DMA. > +#define S5PV210_PA_DMA (0xFA200000) > +#define S5PV210_PA_PDMA (0xE0900000) > #define S5PV210_PA_MDMA 0xFA200000 > #define S5PV210_PA_PDMA0 0xE0900000 > #define S5PV210_PA_PDMA1 0xE0A00000 > @@ -77,6 +80,25 @@ > #define S5PV210_PA_SDRAM (0x20000000) > #define S5P_PA_SDRAM S5PV210_PA_SDRAM > > +#define S5PV210_PA_RTC (0xE2800000) > + > +#define S5PV210_PA_PWR (0xE010C000) > +#define S5P_PA_PWR S5PV210_PA_PWR > +#define S5P_PA_INFORM0 (S5P_PA_PWR + 0x3000) > + > +/* USB HS OTG */ > +#define S5PV210_PA_USB_HSOTG (0xEC000000) > +#define S5PV210_PA_USB_HSPHY (0xEC100000) > + > +/* FIMC */ > +#define S5PV210_PA_FIMC0 (0xFB200000) > +#define S5PV210_PA_FIMC1 (0xFB300000) > +#define S5PV210_PA_FIMC2 (0xFB400000) > + > +/* MFC */ > +#define S5PV210_PA_MFC (0xF1700000) > +#define S5PV210_SZ_MFC (0x0000FFFF) > + > /* I2S */ > #define S5PV210_PA_IIS0 0xEEE30000 > #define S5PV210_PA_IIS1 0xE2100000 > @@ -87,6 +109,17 @@ > #define S5PV210_PA_PCM1 0xE1200000 > #define S5PV210_PA_PCM2 0xE2B00000 > > +/* Audio SubSystem */ > +#define S5PV210_PA_AUDSS (0xEEE10000) > + > +/* TZPC */ > +#define S5PV210_PA_TZPC0 (0xF1500000) > +#define S5PV210_PA_TZPC1 (0xFAD00000) > +#define S5PV210_PA_TZPC2 (0xE0600000) > +#define S5PV210_PA_TZPC3 (0xE1C00000) > + > +#define S5PV210_VA_TZPC(x) (S3C_ADDR(0x01700000) + ((x) * 0x10000)) > + > /* AC97 */ > #define S5PV210_PA_AC97 0xE2200000 > > @@ -101,6 +134,18 @@ > #define S3C_PA_IIC1 S5PV210_PA_IIC1 > #define S3C_PA_IIC2 S5PV210_PA_IIC2 > #define S3C_PA_FB S5PV210_PA_FB > +#define S3C_PA_USB_HSOTG S5PV210_PA_USB_HSOTG > +#define S3C_PA_USB_HSPHY S5PV210_PA_USB_HSPHY > +#define S3C_PA_RTC S5PV210_PA_RTC > +#define S5P_PA_FIMC0 S5PV210_PA_FIMC0 > +#define S5P_PA_FIMC1 S5PV210_PA_FIMC1 > +#define S5P_PA_FIMC2 S5PV210_PA_FIMC2 > +#define S3C_PA_DMA S5PV210_PA_DMA > +#define S3C_PA_PDMA S5PV210_PA_PDMA > +#define S3C_PA_IIS_V50 S5PV210_PA_IIS0 > +#define S3C_PA_ADC S5PV210_PA_ADC(0) > +#define S3C_PA_ADC0 S5PV210_PA_ADC(0) > +#define S3C_PA_ADC1 S5PV210_PA_ADC(1) > #define S3C_PA_WDT S5PV210_PA_WATCHDOG > > #define SAMSUNG_PA_ADC S5PV210_PA_ADC > -- I don't know why above mappings need now. Thanks. Best regards, Kgene. -- Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 2/6] S5PV210 add clock registers for the CPU. 2010-06-14 8:39 ` [PATCH 2/6] S5PV210 add clock registers " MyungJoo Ham 2010-06-14 8:39 ` [PATCH 3/6] S5PV210 added register mappings MyungJoo Ham @ 2010-06-15 4:20 ` Kukjin Kim 1 sibling, 0 replies; 11+ messages in thread From: Kukjin Kim @ 2010-06-15 4:20 UTC (permalink / raw) To: linux-arm-kernel MyungJoo Ham wrote: > > Besides, renamed a register name "BUS0" into "IP5" as EVT1 uses > "IP5" instead of BUS0 (of EVT0) Please make sure that your patch has no problem by using scripts/checkpatch.pl before submitting. Following is from script/checkpatch.pl: 'total: 33 errors, 6 warnings, 513 lines checked' :-( And could you specify a reason for adding these register definitions if they are not being used. > > Signed-off-by: MyungJoo Ham <MyungJoo.Ham@samsung.com> > --- > arch/arm/mach-s5pv210/include/mach/regs-clock.h | 467 > ++++++++++++++++++++++- > 1 files changed, 465 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach- > s5pv210/include/mach/regs-clock.h > index 2a25ab4..9652338 100644 > --- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h > +++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h > @@ -25,6 +25,8 @@ > #define S5P_APLL_CON S5P_CLKREG(0x100) > #define S5P_MPLL_CON S5P_CLKREG(0x108) > #define S5P_EPLL_CON S5P_CLKREG(0x110) > +#define S5P_EPLL_CON1 S5P_CLKREG(0x114) > +#define S5P_EPLL_CON1_MASK (0xFFFF << 0) > #define S5P_VPLL_CON S5P_CLKREG(0x120) > > #define S5P_CLK_SRC0 S5P_CLKREG(0x200) > @@ -63,14 +65,139 @@ > #define S5P_CLKGATE_IP4 S5P_CLKREG(0x470) > > #define S5P_CLKGATE_BLOCK S5P_CLKREG(0x480) > -#define S5P_CLKGATE_BUS0 S5P_CLKREG(0x484) > +#define S5P_CLKGATE_IP5 S5P_CLKREG(0x484) > #define S5P_CLKGATE_BUS1 S5P_CLKREG(0x488) > #define S5P_CLK_OUT S5P_CLKREG(0x500) > +#define S5P_CLK_DIV_STAT0 S5P_CLKREG(0x1000) > +#define S5P_CLK_DIV_STAT1 S5P_CLKREG(0x1004) > +#define S5P_CLK_MUX_STAT0 S5P_CLKREG(0x1100) > +#define S5P_CLK_MUX_STAT1 S5P_CLKREG(0x1104) > +#define S5P_MIXER_OUT_SEL S5P_CLKREG(0x7004) > +#define S5P_MDNIE_SEL S5P_CLKREG(0x7008) > +#define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200) > +#define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204) > + > +#define S5P_DCGIDX_MAP0 S5P_CLKREG(0x3000) > +#define S5P_DCGIDX_MAP1 S5P_CLKREG(0x3004) > +#define S5P_DCGIDX_MAP2 S5P_CLKREG(0x3008) > +#define S5P_DCGPERF_MAP0 S5P_CLKREG(0x3020) > +#define S5P_DCGPERF_MAP1 S5P_CLKREG(0x3024) > +#define S5P_DVCIDX_MAP S5P_CLKREG(0x3040) > +#define S5P_FREQ_CPU S5P_CLKREG(0x3060) > +#define S5P_FREQ_DPM S5P_CLKREG(0x3064) > +#define S5P_DVSEMCLK_EN S5P_CLKREG(0x3080) > +#define S5P_MAXPERF S5P_CLKREG(0x3084) > + > +#define S5P_EPLL_EN (1<<31) > +#define S5P_EPLL_MASK 0xffffffff > +#define S5P_EPLLVAL(_v,_m,_p,_s) ((_v) << 27 | (_m) << 16 | ((_p) << 8) | ((_s))) > > /* CLKSRC0 */ > +#define S5P_CLKSRC0_APLL_MASK (0x1<<0) > +#define S5P_CLKSRC0_APLL_SHIFT (0) > +#define S5P_CLKSRC0_MPLL_MASK (0x1<<4) > +#define S5P_CLKSRC0_MPLL_SHIFT (4) > +#define S5P_CLKSRC0_EPLL_MASK (0x1<<8) > +#define S5P_CLKSRC0_EPLL_SHIFT (8) > +#define S5P_CLKSRC0_VPLL_MASK (0x1<<12) > +#define S5P_CLKSRC0_VPLL_SHIFT (12) > #define S5P_CLKSRC0_MUX200_MASK (0x1<<16) > +#define S5P_CLKSRC0_MUX200_SHIFT (16) > #define S5P_CLKSRC0_MUX166_MASK (0x1<<20) > +#define S5P_CLKSRC0_MUX166_SHIFT (20) > #define S5P_CLKSRC0_MUX133_MASK (0x1<<24) > +#define S5P_CLKSRC0_MUX133_SHIFT (24) > +#define S5P_CLKSRC0_ONENAND_MASK (0x1<<28) > +#define S5P_CLKSRC0_ONENAND_SHIFT (28) > + > +/* CLKSRC1 */ > +#define S5P_CLKSRC1_HDMI_MASK (0x1<<0) > +#define S5P_CLKSRC1_HDMI_SHIFT (0) > +#define S5P_CLKSRC1_MIXER_MASK (0x1<<4) > +#define S5P_CLKSRC1_MIXER_SHIFT (4) > +#define S5P_CLKSRC1_DAC_MASK (0x1<<8) > +#define S5P_CLKSRC1_DAC_SHIFT (8) > +#define S5P_CLKSRC1_CAM0_MASK (0xF<<12) > +#define S5P_CLKSRC1_CAM0_SHIFT (12) > +#define S5P_CLKSRC1_CAM1_MASK (0xF<<16) > +#define S5P_CLKSRC1_CAM1_SHIFT (16) > +#define S5P_CLKSRC1_FIMD_MASK (0xF<<20) > +#define S5P_CLKSRC1_FIMD_SHIFT (20) > +#define S5P_CLKSRC1_CSIS_MASK (0xF<<24) > +#define S5P_CLKSRC1_CSIS_SHIFT (24) > +#define S5P_CLKSRC1_VPLLSRC_MASK (0x1<<28) > +#define S5P_CLKSRC1_VPLLSRC_SHIFT (28) > + > +/* CLKSRC2 */ > +#define S5P_CLKSRC2_G3D_MASK (0x3<<0) > +#define S5P_CLKSRC2_G3D_SHIFT (0) > +#define S5P_CLKSRC2_MFC_MASK (0x3<<4) > +#define S5P_CLKSRC2_MFC_SHIFT (4) > +#define S5P_CLKSRC2_G2D_MASK (0x3<<8) > +#define S5P_CLKSRC2_G2D_SHIFT (8) > + > +/* CLKSRC3 */ > +#define S5P_CLKSRC3_MDNIE_MASK (0xF<<0) > +#define S5P_CLKSRC3_MDNIE_SHIFT (0) > +#define S5P_CLKSRC3_MDNIE_PWMCLK_MASK (0xF<<4) > +#define S5P_CLKSRC3_MDNIE_PWMCLK_SHIFT (4) > +#define S5P_CLKSRC3_FIMC0_LCLK_MASK (0xF<<12) > +#define S5P_CLKSRC3_FIMC0_LCLK_SHIFT (12) > +#define S5P_CLKSRC3_FIMC1_LCLK_MASK (0xF<<16) > +#define S5P_CLKSRC3_FIMC1_LCLK_SHIFT (16) > +#define S5P_CLKSRC3_FIMC2_LCLK_MASK (0xF<<20) > +#define S5P_CLKSRC3_FIMC2_LCLK_SHIFT (20) > + > +/* CLKSRC4 */ > +#define S5P_CLKSRC4_MMC0_MASK (0xF<<0) > +#define S5P_CLKSRC4_MMC0_SHIFT (0) > +#define S5P_CLKSRC4_MMC1_MASK (0xF<<4) > +#define S5P_CLKSRC4_MMC1_SHIFT (4) > +#define S5P_CLKSRC4_MMC2_MASK (0xF<<8) > +#define S5P_CLKSRC4_MMC2_SHIFT (8) > +#define S5P_CLKSRC4_MMC3_MASK (0xF<<12) > +#define S5P_CLKSRC4_MMC3_SHIFT (12) > +#define S5P_CLKSRC4_UART0_MASK (0xF<<16) > +#define S5P_CLKSRC4_UART0_SHIFT (16) > +#define S5P_CLKSRC4_UART1_MASK (0xF<<20) > +#define S5P_CLKSRC4_UART1_SHIFT (20) > +#define S5P_CLKSRC4_UART2_MASK (0xF<<24) > +#define S5P_CLKSRC4_UART2_SHIFT (24) > +#define S5P_CLKSRC4_UART3_MASK (0xF<<28) > +#define S5P_CLKSRC4_UART3_SHIFT (28) > + > +/* CLKSRC5 */ > +#define S5P_CLKSRC5_SPI0_MASK (0xF<<0) > +#define S5P_CLKSRC5_SPI0_SHIFT (0) > +#define S5P_CLKSRC5_SPI1_MASK (0xF<<4) > +#define S5P_CLKSRC5_SPI1_SHIFT (4) > +#define S5P_CLKSRC5_SPI2_MASK (0xF<<8) > +#define S5P_CLKSRC5_SPI2_SHIFT (8) > +#define S5P_CLKSRC5_PWM_MASK (0xF<<12) > +#define S5P_CLKSRC5_PWM_SHIFT (12) > + > +/* CLKSRC6 */ > +#define S5P_CLKSRC6_AUDIO0_MASK (0xF<<0) > +#define S5P_CLKSRC6_AUDIO0_SHIFT (0) > +#define S5P_CLKSRC6_AUDIO1_MASK (0xF<<4) > +#define S5P_CLKSRC6_AUDIO1_SHIFT (4) > +#define S5P_CLKSRC6_AUDIO2_MASK (0xF<<8) > +#define S5P_CLKSRC6_AUDIO2_SHIFT (8) > +#define S5P_CLKSRC6_SPDIF_MASK (0x3<<12) > +#define S5P_CLKSRC6_SPDIF_SHIFT (12) > +#define S5P_CLKSRC6_HPM_MASK (0x1<<16) > +#define S5P_CLKSRC6_HPM_SHIFT (16) > +#define S5P_CLKSRC6_PWI_MASK (0xF<<20) > +#define S5P_CLKSRC6_PWI_SHIFT (20) > +#define S5P_CLKSRC6_ONEDRAM_MASK (0x3<<24) > +#define S5P_CLKSRC6_ONEDRAM_SHIFT (24) > + > +/* CLKSRC_MASK0 - To be defined */ > +#define S5P_CLKSRC_MASK0_HDMI (1<<0) > +#define S5P_CLKSRC_MASK0_MIXER (1<<1) > + > +/* CLKSRC_MASK1 - To be defined */ > + > > /* CLKDIV0 */ > #define S5P_CLKDIV0_APLL_SHIFT (0) > @@ -90,7 +217,325 @@ > #define S5P_CLKDIV0_PCLK66_SHIFT (28) > #define S5P_CLKDIV0_PCLK66_MASK (0x7 << > S5P_CLKDIV0_PCLK66_SHIFT) > > +/* CLKDIV1 */ > +#define S5P_CLKDIV1_TBLK_MASK (0xF<<0) > +#define S5P_CLKDIV1_TBLK_SHIFT (0) > +#define S5P_CLKDIV1_FIMC_MASK (0xF<<8) > +#define S5P_CLKDIV1_FIMC_SHIFT (8) > +#define S5P_CLKDIV1_CAM0_MASK (0xF<<12) > +#define S5P_CLKDIV1_CAM0_SHIFT (12) > +#define S5P_CLKDIV1_CAM1_MASK (0xF<<16) > +#define S5P_CLKDIV1_CAM1_SHIFT (16) > +#define S5P_CLKDIV1_FIMD_MASK (0xF<<20) > +#define S5P_CLKDIV1_FIMD_SHIFT (20) > +#define S5P_CLKDIV1_CSIS_MASK (0xF<<28) > +#define S5P_CLKDIV1_CSIS_SHIFT (28) > + > +/* CLKDIV2 */ > +#define S5P_CLKDIV2_G3D_MASK (0xF<<0) > +#define S5P_CLKDIV2_G3D_SHIFT (0) > +#define S5P_CLKDIV2_MFC_MASK (0xF<<4) > +#define S5P_CLKDIV2_MFC_SHIFT (4) > +#define S5P_CLKDIV2_G2D_MASK (0xF<<8) > +#define S5P_CLKDIV2_G2D_SHIFT (8) > + > +/* CLKDIV3 */ > +#define S5P_CLKDIV3_MDNIE_MASK (0xf<<0) > +#define S5P_CLKDIV3_MDNIE_SHIFT (0) > +#define S5P_CLKDIV3_MDNIE_PWM_MASK (0x3f<<4) > +#define S5P_CLKDIV3_MDNIE_PWM_SHIFT (4) > +#define S5P_CLKDIV3_FIMC0_LCLK_MASK (0xf<<12) > +#define S5P_CLKDIV3_FIMC0_LCLK_SHIFT (12) > +#define S5P_CLKDIV3_FIMC1_LCLK_MASK (0xf<<16) > +#define S5P_CLKDIV3_FIMC1_LCLK_SHIFT (16) > +#define S5P_CLKDIV3_FIMC2_LCLK_MASK (0xf<<20) > +#define S5P_CLKDIV3_FIMC2_LCLK_SHIFT (20) > + > +/* CLKDIV4 */ > +#define S5P_CLKDIV4_MMC0_MASK (0xF<<0) > +#define S5P_CLKDIV4_MMC0_SHIFT (0) > +#define S5P_CLKDIV4_MMC1_MASK (0xF<<4) > +#define S5P_CLKDIV4_MMC1_SHIFT (4) > +#define S5P_CLKDIV4_MMC2_MASK (0xF<<8) > +#define S5P_CLKDIV4_MMC2_SHIFT (8) > +#define S5P_CLKDIV4_MMC3_MASK (0xF<<12) > +#define S5P_CLKDIV4_MMC3_SHIFT (12) > +#define S5P_CLKDIV4_UART0_MASK (0xF<<16) > +#define S5P_CLKDIV4_UART0_SHIFT (16) > +#define S5P_CLKDIV4_UART1_MASK (0xf<<20) > +#define S5P_CLKDIV4_UART1_SHIFT (20) > +#define S5P_CLKDIV4_UART2_MASK (0xf<<24) > +#define S5P_CLKDIV4_UART2_SHIFT (24) > +#define S5P_CLKDIV4_UART3_MASK (0xf<<28) > +#define S5P_CLKDIV4_UART3_SHIFT (28) > + > +/* CLKDIV5 */ > +#define S5P_CLKDIV5_SPI0_MASK (0xF<<0) > +#define S5P_CLKDIV5_SPI0_SHIFT (0) > +#define S5P_CLKDIV5_SPI1_MASK (0xF<<4) > +#define S5P_CLKDIV5_SPI1_SHIFT (4) > +#define S5P_CLKDIV5_SPI2_MASK (0xF<<8) > +#define S5P_CLKDIV5_SPI2_SHIFT (8) > +#define S5P_CLKDIV5_PWM_MASK (0xF<<12) > +#define S5P_CLKDIV5_PWM_SHIFT (12) > + > +/* CLKDIV6 */ > +#define S5P_CLKDIV6_AUDIO0_MASK (0xF<<0) > +#define S5P_CLKDIV6_AUDIO0_SHIFT (0) > +#define S5P_CLKDIV6_AUDIO1_MASK (0xF<<4) > +#define S5P_CLKDIV6_AUDIO1_SHIFT (4) > +#define S5P_CLKDIV6_AUDIO2_MASK (0xF<<8) > +#define S5P_CLKDIV6_AUDIO2_SHIFT (8) > +#define S5P_CLKDIV6_ONENAND_MASK (0x7<<12) > +#define S5P_CLKDIV6_ONENAND_SHIFT (12) > +#define S5P_CLKDIV6_COPY_MASK (0x7<<16) > +#define S5P_CLKDIV6_COPY_SHIFT (16) > +#define S5P_CLKDIV6_HPM_MASK (0x7<<20) > +#define S5P_CLKDIV6_HPM_SHIFT (20) > +#define S5P_CLKDIV6_PWI_MASK (0xf<<24) > +#define S5P_CLKDIV6_PWI_SHIFT (24) > +#define S5P_CLKDIV6_ONEDRAM_MASK (0xf<<28) > +#define S5P_CLKDIV6_ONEDRAM_SHIFT (28) > + > +/* IP Clock Gate 0 Registers */ > +#define S5P_CLKGATE_IP0_CSIS (1<<31) > +#define S5P_CLKGATE_IP0_IPC (1<<30) > +#define S5P_CLKGATE_IP0_ROTATOR (1<<29) > +#define S5P_CLKGATE_IP0_JPEG (1<<28) > +#define S5P_CLKGATE_IP0_FIMC2 (1<<26) > +#define S5P_CLKGATE_IP0_FIMC1 (1<<25) > +#define S5P_CLKGATE_IP0_FIMC0 (1<<24) > +#define S5P_CLKGATE_IP0_MFC (1<<16) > +#define S5P_CLKGATE_IP0_G2D (1<<12) > +#define S5P_CLKGATE_IP0_G3D (1<<8) > +#define S5P_CLKGATE_IP0_IMEM (1<<5) > +#define S5P_CLKGATE_IP0_PDMA1 (1<<4) > +#define S5P_CLKGATE_IP0_PDMA0 (1<<3) > +#define S5P_CLKGATE_IP0_MDMA (1<<2) > +#define S5P_CLKGATE_IP0_DMC1 (1<<1) > +#define S5P_CLKGATE_IP0_DMC0 (1<<0) > +#define S5P_CLKGATE_IP0_RESERVED (0x08feeec0) > +#define S5P_CLKGATE_IP0_ALWAYS_ON ( S5P_CLKGATE_IP0_DMC1 |\ > + S5P_CLKGATE_IP0_DMC0 |\ > + S5P_CLKGATE_IP0_IMEM ) > +#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING > +#define S5P_CLKGATE_IP0_BOOT_ON ( S5P_CLKGATE_IP0_PDMA0 > |\ > + S5P_CLKGATE_IP0_PDMA1) > +#else > +#define S5P_CLKGATE_IP0_BOOT_ON ( S5P_CLKGATE_IP0_PDMA0 > |\ > + S5P_CLKGATE_IP0_PDMA1 |\ > + S5P_CLKGATE_IP0_G2D) > +#endif > + > +/* IP Clock Gate 1 Registers */ > +#define S5P_CLKGATE_IP1_NFCON (1<<28) > +#define S5P_CLKGATE_IP1_SROMC (1<<26) > +#define S5P_CLKGATE_IP1_CFCON (1<<25) > +#define S5P_CLKGATE_IP1_NANDXL (1<<24) > +#define S5P_CLKGATE_IP1_USBHOST (1<<17) > +#define S5P_CLKGATE_IP1_USBOTG (1<<16) > +#define S5P_CLKGATE_IP1_HDMI (1<<11) > +#define S5P_CLKGATE_IP1_TVENC (1<<10) > +#define S5P_CLKGATE_IP1_MIXER (1<<9) > +#define S5P_CLKGATE_IP1_VP (1<<8) > +#define S5P_CLKGATE_IP1_DSIM (1<<2) > +#define S5P_CLKGATE_IP1_MIE (1<<1) > +#define S5P_CLKGATE_IP1_FIMD (1<<0) > +#define S5P_CLKGATE_IP1_RESERVED (0xe8fcf0f8) > +#define S5P_CLKGATE_IP1_ALWAYS_ON ( 0 ) > +#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING > +#define S5P_CLKGATE_IP1_BOOT_ON ( S5P_CLKGATE_IP1_FIMD |\ > + S5P_CLKGATE_IP1_NANDXL) > +#else > +#define S5P_CLKGATE_IP1_BOOT_ON ( S5P_CLKGATE_IP1_FIMD |\ > + S5P_CLKGATE_IP1_NANDXL |\ > + S5P_CLKGATE_IP1_USBOTG) > +#endif > + > + > +/* IP Clock Gate 2 Registers */ > +#define S5P_CLKGATE_IP2_TZIC3 (1<<31) > +#define S5P_CLKGATE_IP2_TZIC2 (1<<30) > +#define S5P_CLKGATE_IP2_TZIC1 (1<<29) > +#define S5P_CLKGATE_IP2_TZIC0 (1<<28) > +#define S5P_CLKGATE_IP2_VIC3 (1<<27) > +#define S5P_CLKGATE_IP2_VIC2 (1<<26) > +#define S5P_CLKGATE_IP2_VIC1 (1<<25) > +#define S5P_CLKGATE_IP2_VIC0 (1<<24) > +#define S5P_CLKGATE_IP2_TSI (1<<20) > +#define S5P_CLKGATE_IP2_HSMMC3 (1<<19) > +#define S5P_CLKGATE_IP2_HSMMC2 (1<<18) > +#define S5P_CLKGATE_IP2_HSMMC1 (1<<17) > +#define S5P_CLKGATE_IP2_HSMMC0 (1<<16) > +#define S5P_CLKGATE_IP2_SECJTAG (1<<11) > +#define S5P_CLKGATE_IP2_HOSTIF (1<<10) > +#define S5P_CLKGATE_IP2_MODEM (1<<9) > +#define S5P_CLKGATE_IP2_CORESIGHT (1<<8) > +#define S5P_CLKGATE_IP2_SDM (1<<1) > +#define S5P_CLKGATE_IP2_SECSS (1<<0) > +#define S5P_CLKGATE_IP2_RESERVED (0xe0f0fc) > +#define S5P_CLKGATE_IP2_ALWAYS_ON ( S5P_CLKGATE_IP2_TZIC3 | > S5P_CLKGATE_IP2_TZIC2 |\ > + S5P_CLKGATE_IP2_TZIC1 | > S5P_CLKGATE_IP2_TZIC0 |\ > + S5P_CLKGATE_IP2_VIC3 | > S5P_CLKGATE_IP2_VIC2 |\ > + S5P_CLKGATE_IP2_VIC1 | > S5P_CLKGATE_IP2_VIC0 |\ > + S5P_CLKGATE_IP2_SECJTAG | > S5P_CLKGATE_IP2_CORESIGHT |\ > + S5P_CLKGATE_IP2_SDM | > S5P_CLKGATE_IP2_SECSS ) > +#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING > +#define S5P_CLKGATE_IP2_BOOT_ON ( 0 ) > +#else > +#define S5P_CLKGATE_IP2_BOOT_ON ( S5P_CLKGATE_IP2_TSI |\ > + S5P_CLKGATE_IP2_HSMMC2 |\ > + S5P_CLKGATE_IP2_HSMMC0 |\ > + S5P_CLKGATE_IP2_HOSTIF |\ > + S5P_CLKGATE_IP2_MODEM) > +#endif > + > + > +/* IP Clock Gate 3 Registers */ > +#define S5P_CLKGATE_IP3_PCM2 (1<<30) > +#define S5P_CLKGATE_IP3_PCM1 (1<<29) > +#define S5P_CLKGATE_IP3_PCM0 (1<<28) > +#define S5P_CLKGATE_IP3_SYSCON (1<<27) > +#define S5P_CLKGATE_IP3_GPIO (1<<26) > +#define S5P_CLKGATE_IP3_TSADC (1<<24) > +#define S5P_CLKGATE_IP3_PWM (1<<23) > +#define S5P_CLKGATE_IP3_WDT (1<<22) > +#define S5P_CLKGATE_IP3_KEYIF (1<<21) > +#define S5P_CLKGATE_IP3_UART3 (1<<20) > +#define S5P_CLKGATE_IP3_UART2 (1<<19) > +#define S5P_CLKGATE_IP3_UART1 (1<<18) > +#define S5P_CLKGATE_IP3_UART0 (1<<17) > +#define S5P_CLKGATE_IP3_SYSTIMER (1<<16) > +#define S5P_CLKGATE_IP3_RTC (1<<15) > +#define S5P_CLKGATE_IP3_SPI2 (1<<14) > +#define S5P_CLKGATE_IP3_SPI1 (1<<13) > +#define S5P_CLKGATE_IP3_SPI0 (1<<12) > +#define S5P_CLKGATE_IP3_I2C_HDMI_PHY (1<<11) > +#define S5P_CLKGATE_IP3_I2C_HDMI_DDC (1<<10) > +#define S5P_CLKGATE_IP3_I2C2 (1<<9) > +#define S5P_CLKGATE_IP3_I2C1 (1<<8) > +#define S5P_CLKGATE_IP3_I2C0 (1<<7) > +#define S5P_CLKGATE_IP3_I2S2 (1<<6) > +#define S5P_CLKGATE_IP3_I2S1 (1<<5) > +#define S5P_CLKGATE_IP3_I2S0 (1<<4) > +#define S5P_CLKGATE_IP3_AC97 (1<<1) > +#define S5P_CLKGATE_IP3_SPDIF (1<<0) > +#define S5P_CLKGATE_IP3_RESERVED (0x8200000c) > +#define S5P_CLKGATE_IP3_ALWAYS_ON ( S5P_CLKGATE_IP3_SYSCON |\ > + S5P_CLKGATE_IP3_GPIO |\ > + S5P_CLKGATE_IP3_PWM |\ > + S5P_CLKGATE_IP3_UART0 |\ > + S5P_CLKGATE_IP3_UART1 |\ > + S5P_CLKGATE_IP3_UART2 |\ > + S5P_CLKGATE_IP3_UART3 |\ > + S5P_CLKGATE_IP3_SYSTIMER |\ > + S5P_CLKGATE_IP3_I2C0 |\ > + S5P_CLKGATE_IP3_I2C1 |\ > + S5P_CLKGATE_IP3_I2C2 |\ > + S5P_CLKGATE_IP3_RTC ) > +#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING > +#define S5P_CLKGATE_IP3_BOOT_ON ( 0 ) > +#else > +#define S5P_CLKGATE_IP3_BOOT_ON ( S5P_CLKGATE_IP3_WDT |\ > + S5P_CLKGATE_IP3_KEYIF |\ > + S5P_CLKGATE_IP3_I2C_HDMI_PHY ) > +#endif > + > + > +/* IP Clock Gate 4 Registers */ > +#define S5P_CLKGATE_IP4_TZPC3 (1<<8) > +#define S5P_CLKGATE_IP4_TZPC2 (1<<7) > +#define S5P_CLKGATE_IP4_TZPC1 (1<<6) > +#define S5P_CLKGATE_IP4_TZPC0 (1<<5) > +#define S5P_CLKGATE_IP4_SECKEY (1<<3) > +#define S5P_CLKGATE_IP4_IEM_APC (1<<2) > +#define S5P_CLKGATE_IP4_IEM_IEC (1<<1) > +#define S5P_CLKGATE_IP4_CHIP_ID (1<<0) > +#define S5P_CLKGATE_IP4_RESERVED (0xfffffe10) > +#define S5P_CLKGATE_IP4_ALWAYS_ON ( S5P_CLKGATE_IP4_TZPC3 |\ > + S5P_CLKGATE_IP4_TZPC2 |\ > + S5P_CLKGATE_IP4_TZPC1 |\ > + S5P_CLKGATE_IP4_TZPC0 ) > +#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING > +#define S5P_CLKGATE_IP4_BOOT_ON ( 0 ) > +#else > +#define S5P_CLKGATE_IP4_BOOT_ON > ( S5P_CLKGATE_IP4_CHIP_ID ) > +#endif > + > + > +/* Block Clock Gate Registers */ > +#define S5P_CLKGATE_BLOCK_INTC (1<<10) > +#define S5P_CLKGATE_BLOCK_HSMMC (1<<9) > +#define S5P_CLKGATE_BLOCK_DEBUG (1<<8) > +#define S5P_CLKGATE_BLOCK_SECURITY (1<<7) > +#define S5P_CLKGATE_BLOCK_MEMORY (1<<6) > +#define S5P_CLKGATE_BLOCK_USB (1<<5) > +#define S5P_CLKGATE_BLOCK_TV (1<<4) > +#define S5P_CLKGATE_BLOCK_LCD (1<<3) > +#define S5P_CLKGATE_BLOCK_IMG (1<<2) > +#define S5P_CLKGATE_BLOCK_MFC (1<<1) > +#define S5P_CLKGATE_BLOCK_G3D (1<<0) > + > +/* IP Clock Gate 5 Registers */ > +#define S5P_CLKGATE_IP5_JPEG (1<<29) > +#define S5P_CLKGATE_IP5_RESERVED (0xdfffffff) > +#define S5P_CLKGATE_IP5_ALWAYS_ON (0) > +#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING > +#define S5P_CLKGATE_IP5_BOOT_ON (0) > +#else > +#define S5P_CLKGATE_IP5_BOOT_ON ( S5P_CLKGATE_IP5_JPEG ) > +#endif > + > +/* Bus Clock Gate Registers (hidden) */ > + > + > +/* CLK_OUT Registers */ > +#define S5P_CLKOUT_DIV_SHIFT (20) > +#define S5P_CLKOUT_DIV_MASK (0xf << > S5P_CLKOUT_DIV_SHIFT) > +#define S5P_CLKOUT_CLKSEL_SHIFT (12) > +#define S5P_CLKOUT_CLKSEL_MASK (0x1f << > S5P_CLKOUT_CLKSEL_SHIFT) > +#define S5P_CLKOUT_CLKSEL_APLL (0 << > S5P_CLKOUT_CLKSEL_SHIFT) > +#define S5P_CLKOUT_CLKSEL_MPLL (1 << > S5P_CLKOUT_CLKSEL_SHIFT) > +#define S5P_CLKOUT_CLKSEL_EPLL (2 << > S5P_CLKOUT_CLKSEL_SHIFT) > +#define S5P_CLKOUT_CLKSEL_VPLL (3 << > S5P_CLKOUT_CLKSEL_SHIFT) > +#define S5P_CLKOUT_CLKSEL_SCLK_USBPHY0 (4 << > S5P_CLKOUT_CLKSEL_SHIFT) > +#define S5P_CLKOUT_CLKSEL_SCLK_USBPHY1 (5 << > S5P_CLKOUT_CLKSEL_SHIFT) > +#define S5P_CLKOUT_CLKSEL_SCLK_HDMIPHY (6 << > S5P_CLKOUT_CLKSEL_SHIFT) > +#define S5P_CLKOUT_CLKSEL_RTC (7 << > S5P_CLKOUT_CLKSEL_SHIFT) > +#define S5P_CLKOUT_CLKSEL_TICK (8 << > S5P_CLKOUT_CLKSEL_SHIFT) > +#define S5P_CLKOUT_CLKSEL_HCLK200 (9 << S5P_CLKOUT_CLKSEL_SHIFT) > +#define S5P_CLKOUT_CLKSEL_PCLK100 (10 << S5P_CLKOUT_CLKSEL_SHIFT) > +#define S5P_CLKOUT_CLKSEL_HCLK166 (11 << S5P_CLKOUT_CLKSEL_SHIFT) > +#define S5P_CLKOUT_CLKSEL_PCLK83 (12 << S5P_CLKOUT_CLKSEL_SHIFT) > +#define S5P_CLKOUT_CLKSEL_HCLK133 (13 << S5P_CLKOUT_CLKSEL_SHIFT) > +#define S5P_CLKOUT_CLKSEL_PCLK66 (14 << S5P_CLKOUT_CLKSEL_SHIFT) > +#define S5P_CLKOUT_CLKSEL_ARMCLK (15 << S5P_CLKOUT_CLKSEL_SHIFT) > +#define S5P_CLKOUT_CLKSEL_SCLK_HPM (16 << > S5P_CLKOUT_CLKSEL_SHIFT) > +#define S5P_CLKOUT_CLKSEL_XXTI (17 << > S5P_CLKOUT_CLKSEL_SHIFT) > +#define S5P_CLKOUT_CLKSEL_XUSBXTI (18 << S5P_CLKOUT_CLKSEL_SHIFT) > +#define S5P_CLKOUT_CLKSEL_DOUT (19 << > S5P_CLKOUT_CLKSEL_SHIFT) > +#define S5P_CLKOUT_DCLKCMP_SHIFT (8) > +#define S5P_CLKOUT_DCLKCMP_MASK (0xf << > S5P_CLKOUT_DCLKCMP_SHIFT) > +#define S5P_CLKOUT_DCLKDIV_SHIFT (4) > +#define S5P_CLKOUT_DCLKDIV_MASK (0xf << > S5P_CLKOUT_DCLKDIV_SHIFT) > +#define S5P_CLKOUT_DCLKSEL_SHIFT (1) > +#define S5P_CLKOUT_DCLKSEL_MASK (0x7 << > S5P_CLKOUT_DCLKSEL_SHIFT) > +#define S5P_CLKOUT_DCLKSEL_XXTI (0 << > S5P_CLKOUT_DCLKSEL_SHIFT) > +#define S5P_CLKOUT_DCLKSEL_XUSBXTI (1 << > S5P_CLKOUT_DCLKSEL_SHIFT) > +#define S5P_CLKOUT_DCLKSEL_HDMI27M (2 << > S5P_CLKOUT_DCLKSEL_SHIFT) > +#define S5P_CLKOUT_DCLKSEL_USBPHY0 (3 << > S5P_CLKOUT_DCLKSEL_SHIFT) > +#define S5P_CLKOUT_DCLKSEL_USBPHY1 (4 << > S5P_CLKOUT_DCLKSEL_SHIFT) > +#define S5P_CLKOUT_DCLKSEL_HDMIPHY (5 << > S5P_CLKOUT_DCLKSEL_SHIFT) > +#define S5P_CLKOUT_DCLKSEL_FOUTEPLL (6 << > S5P_CLKOUT_DCLKSEL_SHIFT) > +#define S5P_CLKOUT_DCLKSEL_SCLKEPLL (7 << > S5P_CLKOUT_DCLKSEL_SHIFT) > +#define S5P_CLKOUT_DCLKEN_SHIFT (0) > +#define S5P_CLKOUT_DCLKEN_MASK (0x1 << > S5P_CLKOUT_DCLKEN_SHIFT) > +#define S5P_CLKOUT_DCLKEN_ENABLE (1 << S5P_CLKOUT_DCLKEN_SHIFT) > +#define S5P_CLKOUT_DCLKEN_DISABLE (0 << S5P_CLKOUT_DCLKEN_SHIFT) > + > /* Registers related to power management */ > +#define S5P_SWRESET S5P_CLKREG(0x2000) > + > #define S5P_PWR_CFG S5P_CLKREG(0xC000) > #define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0xC004) > #define S5P_WAKEUP_MASK S5P_CLKREG(0xC008) > @@ -112,8 +557,13 @@ > > #define S5P_OTHERS S5P_CLKREG(0xE000) > #define S5P_OM_STAT S5P_CLKREG(0xE100) > +#define S5P_MIE_CONTROL S5P_CLKREG(0xE800) > +#define S5P_HDMI_PHY_CONTROL S5P_CLKREG(0xE804) > #define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE80C) > #define S5P_DAC_CONTROL S5P_CLKREG(0xE810) > +#define S5P_MIPI_DPHY_CONTROL S5P_CLKREG(0xE814) > +#define S5P_ADC_CONTROL S5P_CLKREG(0xE818) > +#define S5P_PS_HOLD_CONTROL S5P_CLKREG(0xE81C) > > #define S5P_INFORM0 S5P_CLKREG(0xF000) > #define S5P_INFORM1 S5P_CLKREG(0xF004) > @@ -159,12 +609,25 @@ > /* OTHERS Resgister */ > #define S5P_OTHERS_USB_SIG_MASK (1 << 16) > #define S5P_OTHERS_MIPI_DPHY_EN (1 << 28) > +#define S5P_OTHERS_CLKOUT_SHIFT (8) > +#define S5P_OTHERS_CLKOUT_MASK (0x3 << > S5P_OTHERS_CLKOUT_SHIFT) > +#define S5P_OTHERS_CLKOUT_SYSCON (0 << S5P_OTHERS_CLKOUT_SHIFT) > +#define S5P_OTHERS_CLKOUT_RESERVED (1 << > S5P_OTHERS_CLKOUT_SHIFT) > +#define S5P_OTHERS_CLKOUT_XXTI (2 << > S5P_OTHERS_CLKOUT_SHIFT) > +#define S5P_OTHERS_CLKOUT_XUSBXTI (3 << S5P_OTHERS_CLKOUT_SHIFT) > > /* MIPI */ > -#define S5P_MIPI_DPHY_EN (3) > +#define S5P_MIPI_DPHY_EN (3 << 0) > + > +/* S5P_MIPI_PHY_CON0 */ > +#define S5P_MIPI_M_RESETN (1 << 1) > > /* S5P_DAC_CONTROL */ > #define S5P_DAC_ENABLE (1) > #define S5P_DAC_DISABLE (0) > > +#define S5PC110_USB_PHY_CON S5P_CLKREG(0xE80c) > +#define S5PC110_USB_PHY0_EN (1 << 0) > +#define S5PC110_USB_PHY1_EN (1 << 1) > + > #endif /* __ASM_ARCH_REGS_CLOCK_H */ > -- Thanks. Best regards, Kgene. -- Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/6] S5PV210 Add IRQ/EINT register information for the CPU. 2010-06-14 8:39 ` [PATCH 1/6] S5PV210 Add IRQ/EINT register information for the CPU MyungJoo Ham 2010-06-14 8:39 ` [PATCH 2/6] S5PV210 add clock registers " MyungJoo Ham @ 2010-06-15 6:05 ` Kukjin Kim 1 sibling, 0 replies; 11+ messages in thread From: Kukjin Kim @ 2010-06-15 6:05 UTC (permalink / raw) To: linux-arm-kernel MyungJoo Ham wrote: > > Signed-off-by: MyungJoo Ham <MyungJoo.Ham@samsung.com> Is above your e-mail right? myungjoo.ham or MyungJoo.Ham? > --- > arch/arm/mach-s5pv210/include/mach/irqs.h | 9 +++++++++ > arch/arm/mach-s5pv210/include/mach/regs-irq.h | 6 ++++++ > 2 files changed, 15 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach- > s5pv210/include/mach/irqs.h > index 9689537..6c5f491 100644 > --- a/arch/arm/mach-s5pv210/include/mach/irqs.h > +++ b/arch/arm/mach-s5pv210/include/mach/irqs.h > @@ -118,9 +118,18 @@ > #define IRQ_MDNIE3 S5P_IRQ_VIC3(8) > #define IRQ_VIC_END S5P_IRQ_VIC3(31) > > +/* External interrupt */ > + No need above comment. Because xxx_EINT_xxx means External Interrupt blah... > #define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) > #define S5P_EINT_BASE2 (IRQ_VIC_END + 1) > > +#define S5P_EINT(x) (S5P_EINT_BASE2 + ((x) - 16)) > +#define IRQ_EINT_BIT(x) ((x) < IRQ_EINT16_31 ? (x) - S5P_VIC0_BASE : (x) - > S5P_EINT(0)) > + IRQ_EINT_BIT is same as EINT_OFFSET. In your patch set, could not find where you has used IRQ_EINT_BIT!! > +/* GPIO interrupt */ > +#define S5P_IRQ_GPIO_BASE (IRQ_EINT(31) + 1) > +#define S5P_IRQ_GPIO(x) (S5P_IRQ_GPIO_BASE + (x)) > + > /* Set the default NR_IRQS */ > #define NR_IRQS (IRQ_EINT(31) + 1) > > diff --git a/arch/arm/mach-s5pv210/include/mach/regs-irq.h b/arch/arm/mach- > s5pv210/include/mach/regs-irq.h > index 5c3b104..139604f 100644 > --- a/arch/arm/mach-s5pv210/include/mach/regs-irq.h > +++ b/arch/arm/mach-s5pv210/include/mach/regs-irq.h > @@ -16,4 +16,10 @@ > #include <asm/hardware/vic.h> > #include <mach/map.h> > > +/* interrupt controller */ > +#define S5PV210_VIC0REG(x) ((x) + VA_VIC0) > +#define S5PV210_VIC1REG(x) ((x) + VA_VIC1) > +#define S5PV210_VIC2REG(x) ((x) + VA_VIC2) > +#define S5PV210_VIC3REG(x) ((x) + VA_VIC3) > + Also not used anywhere in your patch set... > #endif /* __ASM_ARCH_REGS_IRQ_H */ > -- > 1.6.3.3 > > Thanks. Best regards, Kgene. -- Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 0/6] S5PV210 PM Support (suspend-to-mem) 2010-06-14 8:39 [PATCH 0/6] S5PV210 PM Support (suspend-to-mem) MyungJoo Ham 2010-06-14 8:39 ` [PATCH 1/6] S5PV210 Add IRQ/EINT register information for the CPU MyungJoo Ham @ 2010-06-15 3:45 ` Kukjin Kim 1 sibling, 0 replies; 11+ messages in thread From: Kukjin Kim @ 2010-06-15 3:45 UTC (permalink / raw) To: linux-arm-kernel Myungjoo Ham wrote: > > This patch set supports S5PV210/S5PC110 PM (suspend-to-mem). > Please include Ben Dooks for Samsung SoC patch - his address is in MAINTAINERS. And If this patch set is for S5PV210/S5PC110 PM, please make sure that includes for PM code. Seems to be added unnecessary codes. > MyungJoo Ham (8): > S5PV210 Add IRQ/EINT register information for the CPU. > S5PV210 add clock registers for the CPU. > S5PV210 added register mappings > S5PV210 GPIO relataed registers are added. > S5PV210 added EINT-GPIO register mappings > S5PV210 PM Support (suspend-to-mem) > > arch/arm/mach-s5pv210/Makefile | 4 + > arch/arm/mach-s5pv210/include/mach/irqs.h | 9 + > arch/arm/mach-s5pv210/include/mach/map.h | 45 +++ > arch/arm/mach-s5pv210/include/mach/regs-clock.h | 467 > ++++++++++++++++++++++- > arch/arm/mach-s5pv210/include/mach/regs-gpio.h | 121 ++++++ > arch/arm/mach-s5pv210/include/mach/regs-irq.h | 6 + > arch/arm/plat-s5p/Makefile | 3 + > arch/arm/plat-s5p/include/plat/gpio-ext.h | 44 +++ > arch/arm/plat-s5p/include/plat/map-s5p.h | 1 + > arch/arm/plat-s5p/sleep.S | 248 ++++++++++++ > arch/arm/plat-samsung/include/plat/pm-core.h | 53 +++ > arch/arm/plat-samsung/include/plat/pm.h | 13 + > arch/arm/plat-samsung/pm-gpio.c | 4 +- > arch/arm/plat-samsung/pm.c | 75 ++++- > 14 files changed, 1082 insertions(+), 11 deletions(-) > create mode 100644 arch/arm/plat-s5p/include/plat/gpio-ext.h > create mode 100644 arch/arm/plat-s5p/sleep.S > create mode 100644 arch/arm/plat-samsung/include/plat/pm-core.h > > Thanks. Best regards, Kgene. -- Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2010-06-15 6:05 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2010-06-14 8:39 [PATCH 0/6] S5PV210 PM Support (suspend-to-mem) MyungJoo Ham 2010-06-14 8:39 ` [PATCH 1/6] S5PV210 Add IRQ/EINT register information for the CPU MyungJoo Ham 2010-06-14 8:39 ` [PATCH 2/6] S5PV210 add clock registers " MyungJoo Ham 2010-06-14 8:39 ` [PATCH 3/6] S5PV210 added register mappings MyungJoo Ham 2010-06-14 8:39 ` [PATCH 4/6] S5PV210 GPIO relataed registers are added MyungJoo Ham 2010-06-14 8:39 ` [PATCH 5/6] S5PV210 added EINT-GPIO register mappings MyungJoo Ham 2010-06-14 8:39 ` [PATCH 6/6] S5PV210 PM Support Main (suspend-to-mem) MyungJoo Ham 2010-06-15 5:59 ` [PATCH 3/6] S5PV210 added register mappings Kukjin Kim 2010-06-15 4:20 ` [PATCH 2/6] S5PV210 add clock registers for the CPU Kukjin Kim 2010-06-15 6:05 ` [PATCH 1/6] S5PV210 Add IRQ/EINT register information " Kukjin Kim 2010-06-15 3:45 ` [PATCH 0/6] S5PV210 PM Support (suspend-to-mem) Kukjin Kim
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