[PATCH v3 00/11] clk: qcom: update MSM8974 clock controller drivers

[PATCH v3 00/11] clk: qcom: update MSM8974 clock controller drivers

[Dmitry Baryshkov]

Modernize drivers for global and multimedia clock controllers on the
MSM8974 platform. Switch them to using parent_hws/parent_data, use
clocks through the DT links rather than fetching them from the system
clocks list, update schema and platform DT files.

Changes since v2:
- Fix typos in the commit messages (Niel)

Changes since v1:
- Fix typos in the commit messages (Niel)
- Change bindings license to dual GPL + BSD (Krzysztof)
- Fix issues in gcc bindigns pointed out by Krzysztof
- Fix Taniyas's email (Krzysztof)
- Removed dsi-names and changed dsi-phy node in the patch adding the
  second DSI host+PHY (Krzysztof)

Dmitry Baryshkov (11):
  dt-bindings: clock: split qcom,gcc-msm8974,-msm8226 to the separate
    file
  dt-bindings: clocks: qcom,mmcc: define clocks/clock-names for MSM8974
  clk: qcom: gcc-msm8974: use ARRAY_SIZE instead of specifying
    num_parents
  clk: qcom: gcc-msm8974: move clock parent tables down
  clk: qcom: gcc-msm8974: use parent_hws/_data instead of parent_names
  clk: qcom: mmcc-msm8974: use ARRAY_SIZE instead of specifying
    num_parents
  clk: qcom: mmcc-msm8974: move clock parent tables down
  clk: qcom: mmcc-msm8974: use parent_hws/_data instead of parent_names
  ARM: dts: qcom: msm8974: add second DSI host and PHY
  ARM: dts: qcom: msm8974: add clocks and clock-names to gcc device
  ARM: dts: qcom: msm8974: add clocks and clock-names to mmcc device

 .../bindings/clock/qcom,gcc-msm8974.yaml      |  64 ++
 .../bindings/clock/qcom,gcc-other.yaml        |   9 +-
 .../devicetree/bindings/clock/qcom,mmcc.yaml  |  38 +
 arch/arm/boot/dts/qcom-msm8974.dtsi           | 105 +++
 drivers/clk/qcom/gcc-msm8974.c                | 682 ++++++++--------
 drivers/clk/qcom/mmcc-msm8974.c               | 736 +++++++++---------
 6 files changed, 930 insertions(+), 704 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml

-- 
2.35.1

[PATCH v3 01/11] dt-bindings: clock: split qcom,gcc-msm8974,-msm8226 to the separate file

[Dmitry Baryshkov]

Move schema for the GCC on MSM8974 and MSM8226 platforms to a separate
file to be able to define device-specific clock properties.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../bindings/clock/qcom,gcc-msm8974.yaml      | 64 +++++++++++++++++++
 .../bindings/clock/qcom,gcc-other.yaml        |  9 +--
 2 files changed, 65 insertions(+), 8 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml
new file mode 100644
index 000000000000..a92a60f8c1af
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8974.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm MSM8974 (including Pro) and MSM8226 Global Clock & Reset
+  Controller
+
+maintainers:
+  - Stephen Boyd <sboyd@kernel.org>
+  - Taniya Das <quic_tdas@quicinc.com>
+
+description: |
+  Qualcomm global clock control module which supports the clocks, resets and
+  power domains on MSM8974 (all variants) and MSM8226.
+
+  See also:
+  - dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
+  - dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
+
+$ref: qcom,gcc.yaml#
+
+properties:
+  compatible:
+    enum:
+      - qcom,gcc-msm8226
+      - qcom,gcc-msm8974
+      - qcom,gcc-msm8974pro
+      - qcom,gcc-msm8974pro-ac
+
+  clocks:
+    items:
+      - description: XO source
+      - description: Sleep clock source
+
+  clock-names:
+    items:
+      - const: xo
+      - const: sleep_clk
+
+  power-domains:
+    maxItems: 1
+
+required:
+  - compatible
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    clock-controller@fc400000 {
+        compatible = "qcom,gcc-msm8974";
+        reg = <0x00100000 0x94000>;
+        #clock-cells = <1>;
+        #reset-cells = <1>;
+        #power-domain-cells = <1>;
+
+        clock-names = "xo", "sleep_clk";
+        clocks = <&xo_board>,
+                 <&sleep_clk>;
+    };
+...
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
index 35fc22a19000..0ec8ff215007 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
@@ -19,8 +19,6 @@ description: |
   - dt-bindings/clock/qcom,gcc-ipq6018.h
   - dt-bindings/reset/qcom,gcc-ipq6018.h
   - dt-bindings/clock/qcom,gcc-msm8953.h
-  - dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
-  - dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
   - dt-bindings/clock/qcom,gcc-mdm9607.h
   - dt-bindings/clock/qcom,gcc-mdm9615.h
   - dt-bindings/reset/qcom,gcc-mdm9615.h
@@ -34,11 +32,7 @@ properties:
       - qcom,gcc-ipq4019
       - qcom,gcc-ipq6018
       - qcom,gcc-mdm9607
-      - qcom,gcc-msm8226
       - qcom,gcc-msm8953
-      - qcom,gcc-msm8974
-      - qcom,gcc-msm8974pro
-      - qcom,gcc-msm8974pro-ac
       - qcom,gcc-mdm9615
 
 required:
@@ -47,10 +41,9 @@ required:
 unevaluatedProperties: false
 
 examples:
-  # Example for GCC for MSM8974:
   - |
     clock-controller@900000 {
-      compatible = "qcom,gcc-msm8974";
+      compatible = "qcom,gcc-mdm9607";
       reg = <0x900000 0x4000>;
       #clock-cells = <1>;
       #reset-cells = <1>;
-- 
2.35.1

[PATCH v3 02/11] dt-bindings: clocks: qcom,mmcc: define clocks/clock-names for MSM8974

[Dmitry Baryshkov]

Define clock/clock-names properties of the MMCC device node to be used
on MSM8974 platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../devicetree/bindings/clock/qcom,mmcc.yaml  | 38 +++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
index 03faab5b6a41..78473475c68d 100644
--- a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
@@ -99,6 +99,44 @@ allOf:
             - const: dsi2pllbyte
             - const: hdmipll
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,mmcc-msm8974
+    then:
+      properties:
+        clocks:
+          items:
+            - description: Board XO source
+            - description: MMSS GPLL0 voted clock
+            - description: GPLL0 voted clock
+            - description: GPLL1 voted clock
+            - description: GFX3D clock source
+            - description: DSI phy instance 0 dsi clock
+            - description: DSI phy instance 0 byte clock
+            - description: DSI phy instance 1 dsi clock
+            - description: DSI phy instance 1 byte clock
+            - description: HDMI phy PLL clock
+            - description: eDP phy PLL link clock
+            - description: eDP phy PLL vco clock
+
+        clock-names:
+          items:
+            - const: xo
+            - const: mmss_gpll0_vote
+            - const: gpll0_vote
+            - const: gpll1_vote
+            - const: gfx3d_clk_src
+            - const: dsi0pll
+            - const: dsi0pllbyte
+            - const: dsi1pll
+            - const: dsi1pllbyte
+            - const: hdmipll
+            - const: edp_link_clk
+            - const: edp_vco_div
+
   - if:
       properties:
         compatible:
-- 
2.35.1

[PATCH v3 03/11] clk: qcom: gcc-msm8974: use ARRAY_SIZE instead of specifying num_parents

[Dmitry Baryshkov]

Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/gcc-msm8974.c | 110 ++++++++++++++++-----------------
 1 file changed, 55 insertions(+), 55 deletions(-)

diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
index bf305fa9e522..b847ce852ef8 100644
--- a/drivers/clk/qcom/gcc-msm8974.c
+++ b/drivers/clk/qcom/gcc-msm8974.c
@@ -88,7 +88,7 @@ static struct clk_rcg2 config_noc_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "config_noc_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -100,7 +100,7 @@ static struct clk_rcg2 periph_noc_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "periph_noc_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -112,7 +112,7 @@ static struct clk_rcg2 system_noc_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "system_noc_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -185,7 +185,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "usb30_master_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -205,7 +205,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup1_i2c_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -230,7 +230,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup1_spi_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -243,7 +243,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup2_i2c_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -257,7 +257,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup2_spi_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -270,7 +270,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup3_i2c_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -284,7 +284,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup3_spi_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -297,7 +297,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup4_i2c_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -311,7 +311,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup4_spi_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -324,7 +324,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup5_i2c_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -338,7 +338,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup5_spi_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -351,7 +351,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup6_i2c_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -365,7 +365,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup6_spi_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -398,7 +398,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart1_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -412,7 +412,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart2_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -426,7 +426,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart3_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -440,7 +440,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart4_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -454,7 +454,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart5_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -468,7 +468,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart6_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -481,7 +481,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup1_i2c_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -495,7 +495,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup1_spi_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -508,7 +508,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup2_i2c_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -522,7 +522,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup2_spi_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -535,7 +535,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup3_i2c_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -549,7 +549,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup3_spi_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -562,7 +562,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup4_i2c_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -576,7 +576,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup4_spi_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -589,7 +589,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup5_i2c_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -603,7 +603,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup5_spi_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -616,7 +616,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup6_i2c_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -630,7 +630,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup6_spi_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -644,7 +644,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart1_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -658,7 +658,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart2_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -672,7 +672,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart3_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -686,7 +686,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart4_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -700,7 +700,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart5_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -714,7 +714,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart6_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -741,7 +741,7 @@ static struct clk_rcg2 ce1_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "ce1_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -762,7 +762,7 @@ static struct clk_rcg2 ce2_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "ce2_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -794,7 +794,7 @@ static struct clk_rcg2 gp1_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gp1_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -808,7 +808,7 @@ static struct clk_rcg2 gp2_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gp2_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -822,7 +822,7 @@ static struct clk_rcg2 gp3_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gp3_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -840,7 +840,7 @@ static struct clk_rcg2 pdm2_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pdm2_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -872,7 +872,7 @@ static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_pro[] = {
 static struct clk_init_data sdcc1_apps_clk_src_init = {
 	.name = "sdcc1_apps_clk_src",
 	.parent_names = gcc_xo_gpll0,
-	.num_parents = 2,
+	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 	.ops = &clk_rcg2_floor_ops,
 };
 
@@ -894,7 +894,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "sdcc2_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_floor_ops,
 	},
 };
@@ -908,7 +908,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "sdcc3_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_floor_ops,
 	},
 };
@@ -922,7 +922,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "sdcc4_apps_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_floor_ops,
 	},
 };
@@ -941,7 +941,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "tsif_ref_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -959,7 +959,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "usb30_mock_utmi_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -978,7 +978,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "usb_hs_system_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -1022,7 +1022,7 @@ static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "usb_hsic_io_cal_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 1,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -1041,7 +1041,7 @@ static struct clk_rcg2 usb_hsic_system_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "usb_hsic_system_clk_src",
 		.parent_names = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
-- 
2.35.1

[PATCH v3 04/11] clk: qcom: gcc-msm8974: move clock parent tables down

[Dmitry Baryshkov]

Rearrage clock parent tables and PLL declarations (pull parents down
and gpll4 up), so that we can use pll hw clock fields in the next
commit.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/gcc-msm8974.c | 98 +++++++++++++++++-----------------
 1 file changed, 49 insertions(+), 49 deletions(-)

diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
index b847ce852ef8..77f3497265a0 100644
--- a/drivers/clk/qcom/gcc-msm8974.c
+++ b/drivers/clk/qcom/gcc-msm8974.c
@@ -32,28 +32,6 @@ enum {
 	P_GPLL4,
 };
 
-static const struct parent_map gcc_xo_gpll0_map[] = {
-	{ P_XO, 0 },
-	{ P_GPLL0, 1 }
-};
-
-static const char * const gcc_xo_gpll0[] = {
-	"xo",
-	"gpll0_vote",
-};
-
-static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
-	{ P_XO, 0 },
-	{ P_GPLL0, 1 },
-	{ P_GPLL4, 5 }
-};
-
-static const char * const gcc_xo_gpll0_gpll4[] = {
-	"xo",
-	"gpll0_vote",
-	"gpll4_vote",
-};
-
 static struct clk_pll gpll0 = {
 	.l_reg = 0x0004,
 	.m_reg = 0x0008,
@@ -81,6 +59,55 @@ static struct clk_regmap gpll0_vote = {
 	},
 };
 
+static struct clk_pll gpll4 = {
+	.l_reg = 0x1dc4,
+	.m_reg = 0x1dc8,
+	.n_reg = 0x1dcc,
+	.config_reg = 0x1dd4,
+	.mode_reg = 0x1dc0,
+	.status_reg = 0x1ddc,
+	.status_bit = 17,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "gpll4",
+		.parent_names = (const char *[]){ "xo" },
+		.num_parents = 1,
+		.ops = &clk_pll_ops,
+	},
+};
+
+static struct clk_regmap gpll4_vote = {
+	.enable_reg = 0x1480,
+	.enable_mask = BIT(4),
+	.hw.init = &(struct clk_init_data){
+		.name = "gpll4_vote",
+		.parent_names = (const char *[]){ "gpll4" },
+		.num_parents = 1,
+		.ops = &clk_pll_vote_ops,
+	},
+};
+
+static const struct parent_map gcc_xo_gpll0_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL0, 1 }
+};
+
+static const char * const gcc_xo_gpll0[] = {
+	"xo",
+	"gpll0_vote",
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL0, 1 },
+	{ P_GPLL4, 5 }
+};
+
+static const char * const gcc_xo_gpll0_gpll4[] = {
+	"xo",
+	"gpll0_vote",
+	"gpll4_vote",
+};
+
 static struct clk_rcg2 config_noc_clk_src = {
 	.cmd_rcgr = 0x0150,
 	.hid_width = 5,
@@ -144,33 +171,6 @@ static struct clk_regmap gpll1_vote = {
 	},
 };
 
-static struct clk_pll gpll4 = {
-	.l_reg = 0x1dc4,
-	.m_reg = 0x1dc8,
-	.n_reg = 0x1dcc,
-	.config_reg = 0x1dd4,
-	.mode_reg = 0x1dc0,
-	.status_reg = 0x1ddc,
-	.status_bit = 17,
-	.clkr.hw.init = &(struct clk_init_data){
-		.name = "gpll4",
-		.parent_names = (const char *[]){ "xo" },
-		.num_parents = 1,
-		.ops = &clk_pll_ops,
-	},
-};
-
-static struct clk_regmap gpll4_vote = {
-	.enable_reg = 0x1480,
-	.enable_mask = BIT(4),
-	.hw.init = &(struct clk_init_data){
-		.name = "gpll4_vote",
-		.parent_names = (const char *[]){ "gpll4" },
-		.num_parents = 1,
-		.ops = &clk_pll_vote_ops,
-	},
-};
-
 static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = {
 	F(125000000, P_GPLL0, 1, 5, 24),
 	{ }
-- 
2.35.1

[PATCH v3 05/11] clk: qcom: gcc-msm8974: use parent_hws/_data instead of parent_names

[Dmitry Baryshkov]

Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.

Note, the system names for xo clocks were changed from "xo" to
"xo_board" to follow the example of other platforms.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/gcc-msm8974.c | 492 +++++++++++++++++----------------
 1 file changed, 253 insertions(+), 239 deletions(-)

diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
index 77f3497265a0..025cc9a20dbb 100644
--- a/drivers/clk/qcom/gcc-msm8974.c
+++ b/drivers/clk/qcom/gcc-msm8974.c
@@ -42,7 +42,9 @@ static struct clk_pll gpll0 = {
 	.status_bit = 17,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gpll0",
-		.parent_names = (const char *[]){ "xo" },
+		.parent_data = &(const struct clk_parent_data){
+			.fw_name = "xo", .name = "xo_board",
+		},
 		.num_parents = 1,
 		.ops = &clk_pll_ops,
 	},
@@ -53,7 +55,9 @@ static struct clk_regmap gpll0_vote = {
 	.enable_mask = BIT(0),
 	.hw.init = &(struct clk_init_data){
 		.name = "gpll0_vote",
-		.parent_names = (const char *[]){ "gpll0" },
+		.parent_hws = (const struct clk_hw*[]){
+			&gpll0.clkr.hw,
+		},
 		.num_parents = 1,
 		.ops = &clk_pll_vote_ops,
 	},
@@ -69,7 +73,9 @@ static struct clk_pll gpll4 = {
 	.status_bit = 17,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gpll4",
-		.parent_names = (const char *[]){ "xo" },
+		.parent_data = &(const struct clk_parent_data){
+			.fw_name = "xo", .name = "xo_board",
+		},
 		.num_parents = 1,
 		.ops = &clk_pll_ops,
 	},
@@ -80,7 +86,9 @@ static struct clk_regmap gpll4_vote = {
 	.enable_mask = BIT(4),
 	.hw.init = &(struct clk_init_data){
 		.name = "gpll4_vote",
-		.parent_names = (const char *[]){ "gpll4" },
+		.parent_hws = (const struct clk_hw*[]){
+			&gpll4.clkr.hw,
+		},
 		.num_parents = 1,
 		.ops = &clk_pll_vote_ops,
 	},
@@ -91,9 +99,9 @@ static const struct parent_map gcc_xo_gpll0_map[] = {
 	{ P_GPLL0, 1 }
 };
 
-static const char * const gcc_xo_gpll0[] = {
-	"xo",
-	"gpll0_vote",
+static const struct clk_parent_data gcc_xo_gpll0[] = {
+	{ .fw_name = "xo", .name = "xo_board" },
+	{ .hw = &gpll0_vote.hw },
 };
 
 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
@@ -102,10 +110,10 @@ static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
 	{ P_GPLL4, 5 }
 };
 
-static const char * const gcc_xo_gpll0_gpll4[] = {
-	"xo",
-	"gpll0_vote",
-	"gpll4_vote",
+static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
+	{ .fw_name = "xo", .name = "xo_board" },
+	{ .hw = &gpll0_vote.hw },
+	{ .hw = &gpll4_vote.hw },
 };
 
 static struct clk_rcg2 config_noc_clk_src = {
@@ -114,7 +122,7 @@ static struct clk_rcg2 config_noc_clk_src = {
 	.parent_map = gcc_xo_gpll0_map,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "config_noc_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -126,7 +134,7 @@ static struct clk_rcg2 periph_noc_clk_src = {
 	.parent_map = gcc_xo_gpll0_map,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "periph_noc_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -138,7 +146,7 @@ static struct clk_rcg2 system_noc_clk_src = {
 	.parent_map = gcc_xo_gpll0_map,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "system_noc_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -154,7 +162,9 @@ static struct clk_pll gpll1 = {
 	.status_bit = 17,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gpll1",
-		.parent_names = (const char *[]){ "xo" },
+		.parent_data = &(const struct clk_parent_data){
+			.fw_name = "xo", .name = "xo_board",
+		},
 		.num_parents = 1,
 		.ops = &clk_pll_ops,
 	},
@@ -165,7 +175,9 @@ static struct clk_regmap gpll1_vote = {
 	.enable_mask = BIT(1),
 	.hw.init = &(struct clk_init_data){
 		.name = "gpll1_vote",
-		.parent_names = (const char *[]){ "gpll1" },
+		.parent_hws = (const struct clk_hw*[]){
+			&gpll1.clkr.hw,
+		},
 		.num_parents = 1,
 		.ops = &clk_pll_vote_ops,
 	},
@@ -184,7 +196,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
 	.freq_tbl = ftbl_gcc_usb30_master_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "usb30_master_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -204,7 +216,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup1_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -229,7 +241,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup1_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -242,7 +254,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup2_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -256,7 +268,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup2_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -269,7 +281,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup3_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -283,7 +295,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup3_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -296,7 +308,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup4_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -310,7 +322,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup4_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -323,7 +335,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup5_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -337,7 +349,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup5_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -350,7 +362,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup6_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -364,7 +376,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup6_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -397,7 +409,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart1_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -411,7 +423,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart2_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -425,7 +437,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart3_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -439,7 +451,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart4_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -453,7 +465,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart5_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -467,7 +479,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart6_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -480,7 +492,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup1_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -494,7 +506,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup1_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -507,7 +519,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup2_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -521,7 +533,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup2_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -534,7 +546,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup3_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -548,7 +560,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup3_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -561,7 +573,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup4_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -575,7 +587,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup4_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -588,7 +600,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup5_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -602,7 +614,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup5_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -615,7 +627,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup6_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -629,7 +641,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup6_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -643,7 +655,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart1_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -657,7 +669,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart2_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -671,7 +683,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart3_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -685,7 +697,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart4_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -699,7 +711,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart5_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -713,7 +725,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart6_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -740,7 +752,7 @@ static struct clk_rcg2 ce1_clk_src = {
 	.freq_tbl = ftbl_gcc_ce1_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "ce1_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -761,7 +773,7 @@ static struct clk_rcg2 ce2_clk_src = {
 	.freq_tbl = ftbl_gcc_ce2_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "ce2_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -793,7 +805,7 @@ static struct clk_rcg2 gp1_clk_src = {
 	.freq_tbl = ftbl_gcc_gp_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gp1_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -807,7 +819,7 @@ static struct clk_rcg2 gp2_clk_src = {
 	.freq_tbl = ftbl_gcc_gp_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gp2_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -821,7 +833,7 @@ static struct clk_rcg2 gp3_clk_src = {
 	.freq_tbl = ftbl_gcc_gp_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gp3_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -839,7 +851,7 @@ static struct clk_rcg2 pdm2_clk_src = {
 	.freq_tbl = ftbl_gcc_pdm2_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pdm2_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -871,7 +883,7 @@ static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_pro[] = {
 
 static struct clk_init_data sdcc1_apps_clk_src_init = {
 	.name = "sdcc1_apps_clk_src",
-	.parent_names = gcc_xo_gpll0,
+	.parent_data = gcc_xo_gpll0,
 	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 	.ops = &clk_rcg2_floor_ops,
 };
@@ -893,7 +905,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "sdcc2_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_floor_ops,
 	},
@@ -907,7 +919,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "sdcc3_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_floor_ops,
 	},
@@ -921,7 +933,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
 	.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "sdcc4_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_floor_ops,
 	},
@@ -940,7 +952,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
 	.freq_tbl = ftbl_gcc_tsif_ref_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "tsif_ref_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -958,7 +970,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
 	.freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "usb30_mock_utmi_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -977,7 +989,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = {
 	.freq_tbl = ftbl_gcc_usb_hs_system_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "usb_hs_system_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -1000,9 +1012,9 @@ static struct clk_rcg2 usb_hsic_clk_src = {
 	.freq_tbl = ftbl_gcc_usb_hsic_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "usb_hsic_clk_src",
-		.parent_names = (const char *[]){
-			"xo",
-			"gpll1_vote",
+		.parent_data = (const struct clk_parent_data[]){
+			{ .fw_name = "xo", .name = "xo_board" },
+			{ .hw = &gpll1_vote.hw },
 		},
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
@@ -1021,7 +1033,7 @@ static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
 	.freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "usb_hsic_io_cal_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -1040,7 +1052,7 @@ static struct clk_rcg2 usb_hsic_system_clk_src = {
 	.freq_tbl = ftbl_gcc_usb_hsic_system_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "usb_hsic_system_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -1051,8 +1063,8 @@ static struct clk_regmap gcc_mmss_gpll0_clk_src = {
 	.enable_mask = BIT(26),
 	.hw.init = &(struct clk_init_data){
 		.name = "mmss_gpll0_vote",
-		.parent_names = (const char *[]){
-			"gpll0_vote",
+		.parent_hws = (const struct clk_hw*[]){
+			&gpll0_vote.hw,
 		},
 		.num_parents = 1,
 		.ops = &clk_branch_simple_ops,
@@ -1067,8 +1079,8 @@ static struct clk_branch gcc_bam_dma_ahb_clk = {
 		.enable_mask = BIT(12),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_bam_dma_ahb_clk",
-			.parent_names = (const char *[]){
-				"periph_noc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&periph_noc_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1084,8 +1096,8 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
 		.enable_mask = BIT(17),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_ahb_clk",
-			.parent_names = (const char *[]){
-				"periph_noc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&periph_noc_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1100,8 +1112,8 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup1_i2c_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp1_qup1_i2c_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1117,8 +1129,8 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup1_spi_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp1_qup1_spi_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup1_spi_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1134,8 +1146,8 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup2_i2c_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp1_qup2_i2c_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1151,8 +1163,8 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup2_spi_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp1_qup2_spi_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup2_spi_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1168,8 +1180,8 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup3_i2c_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp1_qup3_i2c_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1185,8 +1197,8 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup3_spi_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp1_qup3_spi_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup3_spi_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1202,8 +1214,8 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup4_i2c_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp1_qup4_i2c_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup4_i2c_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1219,8 +1231,8 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup4_spi_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp1_qup4_spi_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup4_spi_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1236,8 +1248,8 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup5_i2c_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp1_qup5_i2c_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup5_i2c_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1253,8 +1265,8 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup5_spi_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp1_qup5_spi_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup5_spi_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1270,8 +1282,8 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup6_i2c_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp1_qup6_i2c_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup6_i2c_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1287,8 +1299,8 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup6_spi_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp1_qup6_spi_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup6_spi_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1304,8 +1316,8 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_uart1_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp1_uart1_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_uart1_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1321,8 +1333,8 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_uart2_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp1_uart2_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_uart2_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1338,8 +1350,8 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_uart3_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp1_uart3_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_uart3_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1355,8 +1367,8 @@ static struct clk_branch gcc_blsp1_uart4_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_uart4_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp1_uart4_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_uart4_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1372,8 +1384,8 @@ static struct clk_branch gcc_blsp1_uart5_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_uart5_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp1_uart5_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_uart5_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1389,8 +1401,8 @@ static struct clk_branch gcc_blsp1_uart6_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_uart6_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp1_uart6_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_uart6_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1407,8 +1419,8 @@ static struct clk_branch gcc_blsp2_ahb_clk = {
 		.enable_mask = BIT(15),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_ahb_clk",
-			.parent_names = (const char *[]){
-				"periph_noc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&periph_noc_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1423,8 +1435,8 @@ static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup1_i2c_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp2_qup1_i2c_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup1_i2c_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1440,8 +1452,8 @@ static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup1_spi_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp2_qup1_spi_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup1_spi_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1457,8 +1469,8 @@ static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup2_i2c_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp2_qup2_i2c_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup2_i2c_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1474,8 +1486,8 @@ static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup2_spi_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp2_qup2_spi_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup2_spi_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1491,8 +1503,8 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup3_i2c_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp2_qup3_i2c_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup3_i2c_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1508,8 +1520,8 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup3_spi_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp2_qup3_spi_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup3_spi_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1525,8 +1537,8 @@ static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup4_i2c_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp2_qup4_i2c_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup4_i2c_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1542,8 +1554,8 @@ static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup4_spi_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp2_qup4_spi_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup4_spi_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1559,8 +1571,8 @@ static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup5_i2c_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp2_qup5_i2c_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup5_i2c_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1576,8 +1588,8 @@ static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup5_spi_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp2_qup5_spi_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup5_spi_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1593,8 +1605,8 @@ static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup6_i2c_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp2_qup6_i2c_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup6_i2c_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1610,8 +1622,8 @@ static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup6_spi_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp2_qup6_spi_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup6_spi_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1627,8 +1639,8 @@ static struct clk_branch gcc_blsp2_uart1_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_uart1_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp2_uart1_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_uart1_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1644,8 +1656,8 @@ static struct clk_branch gcc_blsp2_uart2_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_uart2_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp2_uart2_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_uart2_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1661,8 +1673,8 @@ static struct clk_branch gcc_blsp2_uart3_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_uart3_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp2_uart3_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_uart3_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1678,8 +1690,8 @@ static struct clk_branch gcc_blsp2_uart4_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_uart4_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp2_uart4_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_uart4_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1695,8 +1707,8 @@ static struct clk_branch gcc_blsp2_uart5_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_uart5_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp2_uart5_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_uart5_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1712,8 +1724,8 @@ static struct clk_branch gcc_blsp2_uart6_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_uart6_apps_clk",
-			.parent_names = (const char *[]){
-				"blsp2_uart6_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_uart6_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1730,8 +1742,8 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
 		.enable_mask = BIT(10),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_boot_rom_ahb_clk",
-			.parent_names = (const char *[]){
-				"config_noc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&config_noc_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1747,8 +1759,8 @@ static struct clk_branch gcc_ce1_ahb_clk = {
 		.enable_mask = BIT(3),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_ce1_ahb_clk",
-			.parent_names = (const char *[]){
-				"config_noc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&config_noc_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1764,8 +1776,8 @@ static struct clk_branch gcc_ce1_axi_clk = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_ce1_axi_clk",
-			.parent_names = (const char *[]){
-				"system_noc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&system_noc_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1781,8 +1793,8 @@ static struct clk_branch gcc_ce1_clk = {
 		.enable_mask = BIT(5),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_ce1_clk",
-			.parent_names = (const char *[]){
-				"ce1_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&ce1_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1799,8 +1811,8 @@ static struct clk_branch gcc_ce2_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_ce2_ahb_clk",
-			.parent_names = (const char *[]){
-				"config_noc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&config_noc_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1816,8 +1828,8 @@ static struct clk_branch gcc_ce2_axi_clk = {
 		.enable_mask = BIT(1),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_ce2_axi_clk",
-			.parent_names = (const char *[]){
-				"system_noc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&system_noc_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1833,8 +1845,8 @@ static struct clk_branch gcc_ce2_clk = {
 		.enable_mask = BIT(2),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_ce2_clk",
-			.parent_names = (const char *[]){
-				"ce2_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&ce2_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1850,8 +1862,8 @@ static struct clk_branch gcc_gp1_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_gp1_clk",
-			.parent_names = (const char *[]){
-				"gp1_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&gp1_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1867,8 +1879,8 @@ static struct clk_branch gcc_gp2_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_gp2_clk",
-			.parent_names = (const char *[]){
-				"gp2_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&gp2_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1884,8 +1896,8 @@ static struct clk_branch gcc_gp3_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_gp3_clk",
-			.parent_names = (const char *[]){
-				"gp3_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&gp3_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1901,8 +1913,8 @@ static struct clk_branch gcc_lpass_q6_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_lpass_q6_axi_clk",
-			.parent_names = (const char *[]){
-				"system_noc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&system_noc_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1917,8 +1929,8 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_mmss_noc_cfg_ahb_clk",
-			.parent_names = (const char *[]){
-				"config_noc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&config_noc_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1934,8 +1946,8 @@ static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_ocmem_noc_cfg_ahb_clk",
-			.parent_names = (const char *[]){
-				"config_noc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&config_noc_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1950,8 +1962,8 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_mss_cfg_ahb_clk",
-			.parent_names = (const char *[]){
-				"config_noc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&config_noc_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1966,8 +1978,8 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_mss_q6_bimc_axi_clk",
-			.parent_names = (const char *[]){
-				"system_noc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&system_noc_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1982,8 +1994,8 @@ static struct clk_branch gcc_pdm2_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pdm2_clk",
-			.parent_names = (const char *[]){
-				"pdm2_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&pdm2_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1999,8 +2011,8 @@ static struct clk_branch gcc_pdm_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pdm_ahb_clk",
-			.parent_names = (const char *[]){
-				"periph_noc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&periph_noc_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2015,7 +2027,9 @@ static struct clk_branch gcc_pdm_xo4_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pdm_xo4_clk",
-			.parent_names = (const char *[]){ "xo" },
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "xo", .name = "xo_board",
+			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
 		},
@@ -2030,8 +2044,8 @@ static struct clk_branch gcc_prng_ahb_clk = {
 		.enable_mask = BIT(13),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_prng_ahb_clk",
-			.parent_names = (const char *[]){
-				"periph_noc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&periph_noc_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2046,8 +2060,8 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_sdcc1_ahb_clk",
-			.parent_names = (const char *[]){
-				"periph_noc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&periph_noc_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2062,8 +2076,8 @@ static struct clk_branch gcc_sdcc1_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_sdcc1_apps_clk",
-			.parent_names = (const char *[]){
-				"sdcc1_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&sdcc1_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2079,8 +2093,8 @@ static struct clk_branch gcc_sdcc1_cdccal_ff_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_sdcc1_cdccal_ff_clk",
-			.parent_names = (const char *[]){
-				"xo"
+			.parent_data = (const struct clk_parent_data[]){
+				{ .fw_name = "xo", .name = "xo_board" }
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2095,8 +2109,8 @@ static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_sdcc1_cdccal_sleep_clk",
-			.parent_names = (const char *[]){
-				"sleep_clk_src"
+			.parent_data = (const struct clk_parent_data[]){
+				{ .fw_name = "sleep_clk", .name = "sleep_clk_src" }
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2111,8 +2125,8 @@ static struct clk_branch gcc_sdcc2_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_sdcc2_ahb_clk",
-			.parent_names = (const char *[]){
-				"periph_noc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&periph_noc_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2127,8 +2141,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_sdcc2_apps_clk",
-			.parent_names = (const char *[]){
-				"sdcc2_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&sdcc2_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2144,8 +2158,8 @@ static struct clk_branch gcc_sdcc3_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_sdcc3_ahb_clk",
-			.parent_names = (const char *[]){
-				"periph_noc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&periph_noc_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2160,8 +2174,8 @@ static struct clk_branch gcc_sdcc3_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_sdcc3_apps_clk",
-			.parent_names = (const char *[]){
-				"sdcc3_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&sdcc3_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2177,8 +2191,8 @@ static struct clk_branch gcc_sdcc4_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_sdcc4_ahb_clk",
-			.parent_names = (const char *[]){
-				"periph_noc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&periph_noc_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2193,8 +2207,8 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_sdcc4_apps_clk",
-			.parent_names = (const char *[]){
-				"sdcc4_apps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&sdcc4_apps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2210,8 +2224,8 @@ static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_sys_noc_usb3_axi_clk",
-			.parent_names = (const char *[]){
-				"usb30_master_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&usb30_master_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2227,8 +2241,8 @@ static struct clk_branch gcc_tsif_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_tsif_ahb_clk",
-			.parent_names = (const char *[]){
-				"periph_noc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&periph_noc_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2243,8 +2257,8 @@ static struct clk_branch gcc_tsif_ref_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_tsif_ref_clk",
-			.parent_names = (const char *[]){
-				"tsif_ref_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&tsif_ref_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2260,8 +2274,8 @@ static struct clk_branch gcc_usb2a_phy_sleep_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_usb2a_phy_sleep_clk",
-			.parent_names = (const char *[]){
-				"sleep_clk_src",
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "sleep_clk", .name = "sleep_clk_src",
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2276,8 +2290,8 @@ static struct clk_branch gcc_usb2b_phy_sleep_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_usb2b_phy_sleep_clk",
-			.parent_names = (const char *[]){
-				"sleep_clk_src",
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "sleep_clk", .name = "sleep_clk_src",
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2292,8 +2306,8 @@ static struct clk_branch gcc_usb30_master_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_usb30_master_clk",
-			.parent_names = (const char *[]){
-				"usb30_master_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&usb30_master_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2309,8 +2323,8 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_usb30_mock_utmi_clk",
-			.parent_names = (const char *[]){
-				"usb30_mock_utmi_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&usb30_mock_utmi_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2326,8 +2340,8 @@ static struct clk_branch gcc_usb30_sleep_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_usb30_sleep_clk",
-			.parent_names = (const char *[]){
-				"sleep_clk_src",
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "sleep_clk", .name = "sleep_clk_src",
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2342,8 +2356,8 @@ static struct clk_branch gcc_usb_hs_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_usb_hs_ahb_clk",
-			.parent_names = (const char *[]){
-				"periph_noc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&periph_noc_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2358,8 +2372,8 @@ static struct clk_branch gcc_usb_hs_system_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_usb_hs_system_clk",
-			.parent_names = (const char *[]){
-				"usb_hs_system_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&usb_hs_system_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2375,8 +2389,8 @@ static struct clk_branch gcc_usb_hsic_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_usb_hsic_ahb_clk",
-			.parent_names = (const char *[]){
-				"periph_noc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&periph_noc_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2391,8 +2405,8 @@ static struct clk_branch gcc_usb_hsic_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_usb_hsic_clk",
-			.parent_names = (const char *[]){
-				"usb_hsic_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&usb_hsic_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2408,8 +2422,8 @@ static struct clk_branch gcc_usb_hsic_io_cal_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_usb_hsic_io_cal_clk",
-			.parent_names = (const char *[]){
-				"usb_hsic_io_cal_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&usb_hsic_io_cal_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2425,8 +2439,8 @@ static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_usb_hsic_io_cal_sleep_clk",
-			.parent_names = (const char *[]){
-				"sleep_clk_src",
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "sleep_clk", .name = "sleep_clk_src",
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2441,8 +2455,8 @@ static struct clk_branch gcc_usb_hsic_system_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_usb_hsic_system_clk",
-			.parent_names = (const char *[]){
-				"usb_hsic_system_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&usb_hsic_system_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2844,7 +2858,7 @@ static void msm8226_clock_override(void)
 
 static void msm8974_pro_clock_override(void)
 {
-	sdcc1_apps_clk_src_init.parent_names = gcc_xo_gpll0_gpll4;
+	sdcc1_apps_clk_src_init.parent_data = gcc_xo_gpll0_gpll4;
 	sdcc1_apps_clk_src_init.num_parents = 3;
 	sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_pro;
 	sdcc1_apps_clk_src.parent_map = gcc_xo_gpll0_gpll4_map;
-- 
2.35.1

[PATCH v3 06/11] clk: qcom: mmcc-msm8974: use ARRAY_SIZE instead of specifying num_parents

[Dmitry Baryshkov]

Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/mmcc-msm8974.c | 74 ++++++++++++++++-----------------
 1 file changed, 37 insertions(+), 37 deletions(-)

diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index f74662925a58..9008df2305df 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -252,7 +252,7 @@ static struct clk_rcg2 mmss_ahb_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "mmss_ahb_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -289,7 +289,7 @@ static struct clk_rcg2 mmss_axi_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "mmss_axi_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -313,7 +313,7 @@ static struct clk_rcg2 ocmemnoc_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "ocmemnoc_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -332,7 +332,7 @@ static struct clk_rcg2 csi0_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "csi0_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -345,7 +345,7 @@ static struct clk_rcg2 csi1_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "csi1_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -358,7 +358,7 @@ static struct clk_rcg2 csi2_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "csi2_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -371,7 +371,7 @@ static struct clk_rcg2 csi3_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "csi3_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -418,7 +418,7 @@ static struct clk_rcg2 vfe0_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "vfe0_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -431,7 +431,7 @@ static struct clk_rcg2 vfe1_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "vfe1_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -472,7 +472,7 @@ static struct clk_rcg2 mdp_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "mdp_clk_src",
 		.parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
-		.num_parents = 6,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -495,7 +495,7 @@ static struct clk_rcg2 jpeg0_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "jpeg0_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -508,7 +508,7 @@ static struct clk_rcg2 jpeg1_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "jpeg1_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -521,7 +521,7 @@ static struct clk_rcg2 jpeg2_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "jpeg2_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -534,7 +534,7 @@ static struct clk_rcg2 pclk0_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pclk0_clk_src",
 		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
-		.num_parents = 6,
+		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
 		.ops = &clk_pixel_ops,
 		.flags = CLK_SET_RATE_PARENT,
 	},
@@ -548,7 +548,7 @@ static struct clk_rcg2 pclk1_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pclk1_clk_src",
 		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
-		.num_parents = 6,
+		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
 		.ops = &clk_pixel_ops,
 		.flags = CLK_SET_RATE_PARENT,
 	},
@@ -581,7 +581,7 @@ static struct clk_rcg2 vcodec0_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "vcodec0_clk_src",
 		.parent_names = mmcc_xo_mmpll0_1_3_gpll0,
-		.num_parents = 5,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -599,7 +599,7 @@ static struct clk_rcg2 cci_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cci_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -623,7 +623,7 @@ static struct clk_rcg2 camss_gp0_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "camss_gp0_clk_src",
 		.parent_names = mmcc_xo_mmpll0_1_gpll1_0,
-		.num_parents = 5,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -637,7 +637,7 @@ static struct clk_rcg2 camss_gp1_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "camss_gp1_clk_src",
 		.parent_names = mmcc_xo_mmpll0_1_gpll1_0,
-		.num_parents = 5,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -672,7 +672,7 @@ static struct clk_rcg2 mclk0_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "mclk0_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -685,7 +685,7 @@ static struct clk_rcg2 mclk1_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "mclk1_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -698,7 +698,7 @@ static struct clk_rcg2 mclk2_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "mclk2_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -711,7 +711,7 @@ static struct clk_rcg2 mclk3_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "mclk3_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -730,7 +730,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "csi0phytimer_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -743,7 +743,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "csi1phytimer_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -756,7 +756,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "csi2phytimer_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -787,7 +787,7 @@ static struct clk_rcg2 cpp_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cpp_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -805,7 +805,7 @@ static struct clk_rcg2 byte0_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "byte0_clk_src",
 		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
-		.num_parents = 6,
+		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
 		.ops = &clk_byte2_ops,
 		.flags = CLK_SET_RATE_PARENT,
 	},
@@ -819,7 +819,7 @@ static struct clk_rcg2 byte1_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "byte1_clk_src",
 		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
-		.num_parents = 6,
+		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
 		.ops = &clk_byte2_ops,
 		.flags = CLK_SET_RATE_PARENT,
 	},
@@ -838,7 +838,7 @@ static struct clk_rcg2 edpaux_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "edpaux_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -857,7 +857,7 @@ static struct clk_rcg2 edplink_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "edplink_clk_src",
 		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
-		.num_parents = 6,
+		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
 		.ops = &clk_rcg2_ops,
 		.flags = CLK_SET_RATE_PARENT,
 	},
@@ -877,7 +877,7 @@ static struct clk_rcg2 edppixel_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "edppixel_clk_src",
 		.parent_names = mmcc_xo_dsi_hdmi_edp,
-		.num_parents = 6,
+		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp),
 		.ops = &clk_edp_pixel_ops,
 	},
 };
@@ -895,7 +895,7 @@ static struct clk_rcg2 esc0_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "esc0_clk_src",
 		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
-		.num_parents = 6,
+		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -908,7 +908,7 @@ static struct clk_rcg2 esc1_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "esc1_clk_src",
 		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
-		.num_parents = 6,
+		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -926,7 +926,7 @@ static struct clk_rcg2 extpclk_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "extpclk_clk_src",
 		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
-		.num_parents = 6,
+		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
 		.ops = &clk_byte_ops,
 		.flags = CLK_SET_RATE_PARENT,
 	},
@@ -945,7 +945,7 @@ static struct clk_rcg2 hdmi_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "hdmi_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -963,7 +963,7 @@ static struct clk_rcg2 vsync_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "vsync_clk_src",
 		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
-- 
2.35.1

[PATCH v3 07/11] clk: qcom: mmcc-msm8974: move clock parent tables down

[Dmitry Baryshkov]

Move clock parent tables down, after the PLL declarataions, so that we
can use pll hw clock fields in the next commit.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/mmcc-msm8974.c | 170 ++++++++++++++++----------------
 1 file changed, 85 insertions(+), 85 deletions(-)

diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index 9008df2305df..57f1a351c8f6 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -42,6 +42,91 @@ enum {
 	P_DSI1PLL_BYTE,
 };
 
+static struct clk_pll mmpll0 = {
+	.l_reg = 0x0004,
+	.m_reg = 0x0008,
+	.n_reg = 0x000c,
+	.config_reg = 0x0014,
+	.mode_reg = 0x0000,
+	.status_reg = 0x001c,
+	.status_bit = 17,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mmpll0",
+                .parent_names = (const char *[]){ "xo" },
+                .num_parents = 1,
+                .ops = &clk_pll_ops,
+        },
+};
+
+static struct clk_regmap mmpll0_vote = {
+	.enable_reg = 0x0100,
+	.enable_mask = BIT(0),
+	.hw.init = &(struct clk_init_data){
+		.name = "mmpll0_vote",
+		.parent_names = (const char *[]){ "mmpll0" },
+		.num_parents = 1,
+		.ops = &clk_pll_vote_ops,
+	},
+};
+
+static struct clk_pll mmpll1 = {
+	.l_reg = 0x0044,
+	.m_reg = 0x0048,
+	.n_reg = 0x004c,
+	.config_reg = 0x0050,
+	.mode_reg = 0x0040,
+	.status_reg = 0x005c,
+	.status_bit = 17,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mmpll1",
+                .parent_names = (const char *[]){ "xo" },
+                .num_parents = 1,
+                .ops = &clk_pll_ops,
+        },
+};
+
+static struct clk_regmap mmpll1_vote = {
+	.enable_reg = 0x0100,
+	.enable_mask = BIT(1),
+	.hw.init = &(struct clk_init_data){
+		.name = "mmpll1_vote",
+		.parent_names = (const char *[]){ "mmpll1" },
+		.num_parents = 1,
+		.ops = &clk_pll_vote_ops,
+	},
+};
+
+static struct clk_pll mmpll2 = {
+	.l_reg = 0x4104,
+	.m_reg = 0x4108,
+	.n_reg = 0x410c,
+	.config_reg = 0x4110,
+	.mode_reg = 0x4100,
+	.status_reg = 0x411c,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mmpll2",
+                .parent_names = (const char *[]){ "xo" },
+                .num_parents = 1,
+                .ops = &clk_pll_ops,
+        },
+};
+
+static struct clk_pll mmpll3 = {
+	.l_reg = 0x0084,
+	.m_reg = 0x0088,
+	.n_reg = 0x008c,
+	.config_reg = 0x0090,
+	.mode_reg = 0x0080,
+	.status_reg = 0x009c,
+	.status_bit = 17,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mmpll3",
+                .parent_names = (const char *[]){ "xo" },
+                .num_parents = 1,
+                .ops = &clk_pll_ops,
+        },
+};
+
 static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
 	{ P_XO, 0 },
 	{ P_MMPLL0, 1 },
@@ -160,91 +245,6 @@ static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
 	"dsi1pllbyte",
 };
 
-static struct clk_pll mmpll0 = {
-	.l_reg = 0x0004,
-	.m_reg = 0x0008,
-	.n_reg = 0x000c,
-	.config_reg = 0x0014,
-	.mode_reg = 0x0000,
-	.status_reg = 0x001c,
-	.status_bit = 17,
-        .clkr.hw.init = &(struct clk_init_data){
-                .name = "mmpll0",
-                .parent_names = (const char *[]){ "xo" },
-                .num_parents = 1,
-                .ops = &clk_pll_ops,
-        },
-};
-
-static struct clk_regmap mmpll0_vote = {
-	.enable_reg = 0x0100,
-	.enable_mask = BIT(0),
-	.hw.init = &(struct clk_init_data){
-		.name = "mmpll0_vote",
-		.parent_names = (const char *[]){ "mmpll0" },
-		.num_parents = 1,
-		.ops = &clk_pll_vote_ops,
-	},
-};
-
-static struct clk_pll mmpll1 = {
-	.l_reg = 0x0044,
-	.m_reg = 0x0048,
-	.n_reg = 0x004c,
-	.config_reg = 0x0050,
-	.mode_reg = 0x0040,
-	.status_reg = 0x005c,
-	.status_bit = 17,
-        .clkr.hw.init = &(struct clk_init_data){
-                .name = "mmpll1",
-                .parent_names = (const char *[]){ "xo" },
-                .num_parents = 1,
-                .ops = &clk_pll_ops,
-        },
-};
-
-static struct clk_regmap mmpll1_vote = {
-	.enable_reg = 0x0100,
-	.enable_mask = BIT(1),
-	.hw.init = &(struct clk_init_data){
-		.name = "mmpll1_vote",
-		.parent_names = (const char *[]){ "mmpll1" },
-		.num_parents = 1,
-		.ops = &clk_pll_vote_ops,
-	},
-};
-
-static struct clk_pll mmpll2 = {
-	.l_reg = 0x4104,
-	.m_reg = 0x4108,
-	.n_reg = 0x410c,
-	.config_reg = 0x4110,
-	.mode_reg = 0x4100,
-	.status_reg = 0x411c,
-        .clkr.hw.init = &(struct clk_init_data){
-                .name = "mmpll2",
-                .parent_names = (const char *[]){ "xo" },
-                .num_parents = 1,
-                .ops = &clk_pll_ops,
-        },
-};
-
-static struct clk_pll mmpll3 = {
-	.l_reg = 0x0084,
-	.m_reg = 0x0088,
-	.n_reg = 0x008c,
-	.config_reg = 0x0090,
-	.mode_reg = 0x0080,
-	.status_reg = 0x009c,
-	.status_bit = 17,
-        .clkr.hw.init = &(struct clk_init_data){
-                .name = "mmpll3",
-                .parent_names = (const char *[]){ "xo" },
-                .num_parents = 1,
-                .ops = &clk_pll_ops,
-        },
-};
-
 static struct clk_rcg2 mmss_ahb_clk_src = {
 	.cmd_rcgr = 0x5000,
 	.hid_width = 5,
-- 
2.35.1

[PATCH v3 08/11] clk: qcom: mmcc-msm8974: use parent_hws/_data instead of parent_names

[Dmitry Baryshkov]

Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.

Note, the system names for xo clocks were changed from "xo" to
"xo_board" to follow the example of other platforms.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/mmcc-msm8974.c | 516 ++++++++++++++++----------------
 1 file changed, 264 insertions(+), 252 deletions(-)

diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index 57f1a351c8f6..4273fce9a4a4 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -52,7 +52,9 @@ static struct clk_pll mmpll0 = {
 	.status_bit = 17,
         .clkr.hw.init = &(struct clk_init_data){
                 .name = "mmpll0",
-                .parent_names = (const char *[]){ "xo" },
+                .parent_data = (const struct clk_parent_data[]){
+			{ .fw_name = "xo", .name = "xo_board" },
+		},
                 .num_parents = 1,
                 .ops = &clk_pll_ops,
         },
@@ -63,7 +65,9 @@ static struct clk_regmap mmpll0_vote = {
 	.enable_mask = BIT(0),
 	.hw.init = &(struct clk_init_data){
 		.name = "mmpll0_vote",
-		.parent_names = (const char *[]){ "mmpll0" },
+		.parent_hws = (const struct clk_hw*[]){
+			&mmpll0.clkr.hw
+		},
 		.num_parents = 1,
 		.ops = &clk_pll_vote_ops,
 	},
@@ -79,7 +83,9 @@ static struct clk_pll mmpll1 = {
 	.status_bit = 17,
         .clkr.hw.init = &(struct clk_init_data){
                 .name = "mmpll1",
-                .parent_names = (const char *[]){ "xo" },
+                .parent_data = (const struct clk_parent_data[]){
+			{ .fw_name = "xo", .name = "xo_board" },
+		},
                 .num_parents = 1,
                 .ops = &clk_pll_ops,
         },
@@ -90,7 +96,9 @@ static struct clk_regmap mmpll1_vote = {
 	.enable_mask = BIT(1),
 	.hw.init = &(struct clk_init_data){
 		.name = "mmpll1_vote",
-		.parent_names = (const char *[]){ "mmpll1" },
+		.parent_hws = (const struct clk_hw*[]){
+			&mmpll1.clkr.hw
+		},
 		.num_parents = 1,
 		.ops = &clk_pll_vote_ops,
 	},
@@ -105,7 +113,9 @@ static struct clk_pll mmpll2 = {
 	.status_reg = 0x411c,
         .clkr.hw.init = &(struct clk_init_data){
                 .name = "mmpll2",
-                .parent_names = (const char *[]){ "xo" },
+                .parent_data = (const struct clk_parent_data[]){
+			{ .fw_name = "xo", .name = "xo_board" },
+		},
                 .num_parents = 1,
                 .ops = &clk_pll_ops,
         },
@@ -121,7 +131,9 @@ static struct clk_pll mmpll3 = {
 	.status_bit = 17,
         .clkr.hw.init = &(struct clk_init_data){
                 .name = "mmpll3",
-                .parent_names = (const char *[]){ "xo" },
+                .parent_data = (const struct clk_parent_data[]){
+			{ .fw_name = "xo", .name = "xo_board" },
+		},
                 .num_parents = 1,
                 .ops = &clk_pll_ops,
         },
@@ -134,11 +146,11 @@ static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
 	{ P_GPLL0, 5 }
 };
 
-static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
-	"xo",
-	"mmpll0_vote",
-	"mmpll1_vote",
-	"mmss_gpll0_vote",
+static const struct clk_parent_data mmcc_xo_mmpll0_mmpll1_gpll0[] = {
+	{ .fw_name = "xo", .name = "xo_board" },
+	{ .hw = &mmpll0_vote.hw },
+	{ .hw = &mmpll1_vote.hw },
+	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
 };
 
 static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
@@ -150,13 +162,13 @@ static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
 	{ P_DSI1PLL, 3 }
 };
 
-static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
-	"xo",
-	"mmpll0_vote",
-	"hdmipll",
-	"mmss_gpll0_vote",
-	"dsi0pll",
-	"dsi1pll",
+static const struct clk_parent_data mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
+	{ .fw_name = "xo", .name = "xo_board" },
+	{ .hw = &mmpll0_vote.hw },
+	{ .fw_name = "hdmipll", .name = "hdmipll" },
+	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
+	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
+	{ .fw_name = "dsi1pll", .name = "dsi1pll" },
 };
 
 static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
@@ -167,12 +179,12 @@ static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
 	{ P_MMPLL3, 3 }
 };
 
-static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
-	"xo",
-	"mmpll0_vote",
-	"mmpll1_vote",
-	"mmss_gpll0_vote",
-	"mmpll3",
+static const struct clk_parent_data mmcc_xo_mmpll0_1_3_gpll0[] = {
+	{ .fw_name = "xo", .name = "xo_board" },
+	{ .hw = &mmpll0_vote.hw },
+	{ .hw = &mmpll1_vote.hw },
+	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
+	{ .hw = &mmpll3.clkr.hw },
 };
 
 static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
@@ -183,12 +195,12 @@ static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
 	{ P_GPLL1, 4 }
 };
 
-static const char * const mmcc_xo_mmpll0_1_gpll1_0[] = {
-	"xo",
-	"mmpll0_vote",
-	"mmpll1_vote",
-	"mmss_gpll0_vote",
-	"gpll1_vote",
+static const struct clk_parent_data mmcc_xo_mmpll0_1_gpll1_0[] = {
+	{ .fw_name = "xo", .name = "xo_board" },
+	{ .hw = &mmpll0_vote.hw },
+	{ .hw = &mmpll1_vote.hw },
+	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
+	{ .fw_name = "gpll1_vote", .name = "gpll1_vote" },
 };
 
 static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
@@ -200,13 +212,13 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
 	{ P_DSI1PLL, 2 }
 };
 
-static const char * const mmcc_xo_dsi_hdmi_edp[] = {
-	"xo",
-	"edp_link_clk",
-	"hdmipll",
-	"edp_vco_div",
-	"dsi0pll",
-	"dsi1pll",
+static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp[] = {
+	{ .fw_name = "xo", .name = "xo_board" },
+	{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
+	{ .fw_name = "hdmipll", .name = "hdmipll" },
+	{ .fw_name = "edp_vco_div", .name = "edp_vco_div" },
+	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
+	{ .fw_name = "dsi1pll", .name = "dsi1pll" },
 };
 
 static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
@@ -218,13 +230,13 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
 	{ P_DSI1PLL, 2 }
 };
 
-static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
-	"xo",
-	"edp_link_clk",
-	"hdmipll",
-	"gpll0_vote",
-	"dsi0pll",
-	"dsi1pll",
+static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp_gpll0[] = {
+	{ .fw_name = "xo", .name = "xo_board" },
+	{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
+	{ .fw_name = "hdmipll", .name = "hdmipll" },
+	{ .fw_name = "gpll0_vote", .name = "gpll0_vote" },
+	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
+	{ .fw_name = "dsi1pll", .name = "dsi1pll" },
 };
 
 static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
@@ -236,13 +248,13 @@ static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
 	{ P_DSI1PLL_BYTE, 2 }
 };
 
-static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
-	"xo",
-	"edp_link_clk",
-	"hdmipll",
-	"gpll0_vote",
-	"dsi0pllbyte",
-	"dsi1pllbyte",
+static const struct clk_parent_data mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
+	{ .fw_name = "xo", .name = "xo_board" },
+	{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
+	{ .fw_name = "hdmipll", .name = "hdmipll" },
+	{ .fw_name = "gpll0_vote", .name = "gpll0_vote" },
+	{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
+	{ .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" },
 };
 
 static struct clk_rcg2 mmss_ahb_clk_src = {
@@ -251,7 +263,7 @@ static struct clk_rcg2 mmss_ahb_clk_src = {
 	.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "mmss_ahb_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -288,7 +300,7 @@ static struct clk_rcg2 mmss_axi_clk_src = {
 	.freq_tbl = ftbl_mmss_axi_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "mmss_axi_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -312,7 +324,7 @@ static struct clk_rcg2 ocmemnoc_clk_src = {
 	.freq_tbl = ftbl_ocmemnoc_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "ocmemnoc_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -331,7 +343,7 @@ static struct clk_rcg2 csi0_clk_src = {
 	.freq_tbl = ftbl_camss_csi0_3_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "csi0_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -344,7 +356,7 @@ static struct clk_rcg2 csi1_clk_src = {
 	.freq_tbl = ftbl_camss_csi0_3_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "csi1_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -357,7 +369,7 @@ static struct clk_rcg2 csi2_clk_src = {
 	.freq_tbl = ftbl_camss_csi0_3_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "csi2_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -370,7 +382,7 @@ static struct clk_rcg2 csi3_clk_src = {
 	.freq_tbl = ftbl_camss_csi0_3_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "csi3_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -417,7 +429,7 @@ static struct clk_rcg2 vfe0_clk_src = {
 	.freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "vfe0_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -430,7 +442,7 @@ static struct clk_rcg2 vfe1_clk_src = {
 	.freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "vfe1_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -471,7 +483,7 @@ static struct clk_rcg2 mdp_clk_src = {
 	.freq_tbl = ftbl_mdss_mdp_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "mdp_clk_src",
-		.parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
+		.parent_data = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -494,7 +506,7 @@ static struct clk_rcg2 jpeg0_clk_src = {
 	.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "jpeg0_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -507,7 +519,7 @@ static struct clk_rcg2 jpeg1_clk_src = {
 	.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "jpeg1_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -520,7 +532,7 @@ static struct clk_rcg2 jpeg2_clk_src = {
 	.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "jpeg2_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -533,7 +545,7 @@ static struct clk_rcg2 pclk0_clk_src = {
 	.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pclk0_clk_src",
-		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
+		.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
 		.ops = &clk_pixel_ops,
 		.flags = CLK_SET_RATE_PARENT,
@@ -547,7 +559,7 @@ static struct clk_rcg2 pclk1_clk_src = {
 	.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pclk1_clk_src",
-		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
+		.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
 		.ops = &clk_pixel_ops,
 		.flags = CLK_SET_RATE_PARENT,
@@ -580,7 +592,7 @@ static struct clk_rcg2 vcodec0_clk_src = {
 	.freq_tbl = ftbl_venus0_vcodec0_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "vcodec0_clk_src",
-		.parent_names = mmcc_xo_mmpll0_1_3_gpll0,
+		.parent_data = mmcc_xo_mmpll0_1_3_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -598,7 +610,7 @@ static struct clk_rcg2 cci_clk_src = {
 	.freq_tbl = ftbl_camss_cci_cci_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cci_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -622,7 +634,7 @@ static struct clk_rcg2 camss_gp0_clk_src = {
 	.freq_tbl = ftbl_camss_gp0_1_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "camss_gp0_clk_src",
-		.parent_names = mmcc_xo_mmpll0_1_gpll1_0,
+		.parent_data = mmcc_xo_mmpll0_1_gpll1_0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -636,7 +648,7 @@ static struct clk_rcg2 camss_gp1_clk_src = {
 	.freq_tbl = ftbl_camss_gp0_1_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "camss_gp1_clk_src",
-		.parent_names = mmcc_xo_mmpll0_1_gpll1_0,
+		.parent_data = mmcc_xo_mmpll0_1_gpll1_0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -671,7 +683,7 @@ static struct clk_rcg2 mclk0_clk_src = {
 	.freq_tbl = ftbl_camss_mclk0_3_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "mclk0_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -684,7 +696,7 @@ static struct clk_rcg2 mclk1_clk_src = {
 	.freq_tbl = ftbl_camss_mclk0_3_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "mclk1_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -697,7 +709,7 @@ static struct clk_rcg2 mclk2_clk_src = {
 	.freq_tbl = ftbl_camss_mclk0_3_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "mclk2_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -710,7 +722,7 @@ static struct clk_rcg2 mclk3_clk_src = {
 	.freq_tbl = ftbl_camss_mclk0_3_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "mclk3_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -729,7 +741,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = {
 	.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "csi0phytimer_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -742,7 +754,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = {
 	.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "csi1phytimer_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -755,7 +767,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = {
 	.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "csi2phytimer_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -786,7 +798,7 @@ static struct clk_rcg2 cpp_clk_src = {
 	.freq_tbl = ftbl_camss_vfe_cpp_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cpp_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -804,7 +816,7 @@ static struct clk_rcg2 byte0_clk_src = {
 	.freq_tbl = byte_freq_tbl,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "byte0_clk_src",
-		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
+		.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
 		.ops = &clk_byte2_ops,
 		.flags = CLK_SET_RATE_PARENT,
@@ -818,7 +830,7 @@ static struct clk_rcg2 byte1_clk_src = {
 	.freq_tbl = byte_freq_tbl,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "byte1_clk_src",
-		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
+		.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
 		.ops = &clk_byte2_ops,
 		.flags = CLK_SET_RATE_PARENT,
@@ -837,7 +849,7 @@ static struct clk_rcg2 edpaux_clk_src = {
 	.freq_tbl = ftbl_mdss_edpaux_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "edpaux_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -856,7 +868,7 @@ static struct clk_rcg2 edplink_clk_src = {
 	.freq_tbl = ftbl_mdss_edplink_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "edplink_clk_src",
-		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
+		.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
 		.ops = &clk_rcg2_ops,
 		.flags = CLK_SET_RATE_PARENT,
@@ -876,7 +888,7 @@ static struct clk_rcg2 edppixel_clk_src = {
 	.freq_tbl = edp_pixel_freq_tbl,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "edppixel_clk_src",
-		.parent_names = mmcc_xo_dsi_hdmi_edp,
+		.parent_data = mmcc_xo_dsi_hdmi_edp,
 		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp),
 		.ops = &clk_edp_pixel_ops,
 	},
@@ -894,7 +906,7 @@ static struct clk_rcg2 esc0_clk_src = {
 	.freq_tbl = ftbl_mdss_esc0_1_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "esc0_clk_src",
-		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
+		.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -907,7 +919,7 @@ static struct clk_rcg2 esc1_clk_src = {
 	.freq_tbl = ftbl_mdss_esc0_1_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "esc1_clk_src",
-		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
+		.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -925,7 +937,7 @@ static struct clk_rcg2 extpclk_clk_src = {
 	.freq_tbl = extpclk_freq_tbl,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "extpclk_clk_src",
-		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
+		.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
 		.ops = &clk_byte_ops,
 		.flags = CLK_SET_RATE_PARENT,
@@ -944,7 +956,7 @@ static struct clk_rcg2 hdmi_clk_src = {
 	.freq_tbl = ftbl_mdss_hdmi_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "hdmi_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -962,7 +974,7 @@ static struct clk_rcg2 vsync_clk_src = {
 	.freq_tbl = ftbl_mdss_vsync_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "vsync_clk_src",
-		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
@@ -975,8 +987,8 @@ static struct clk_branch camss_cci_cci_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_cci_cci_ahb_clk",
-			.parent_names = (const char *[]){
-				"mmss_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_ahb_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -991,8 +1003,8 @@ static struct clk_branch camss_cci_cci_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_cci_cci_clk",
-			.parent_names = (const char *[]){
-				"cci_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cci_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1008,8 +1020,8 @@ static struct clk_branch camss_csi0_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_csi0_ahb_clk",
-			.parent_names = (const char *[]){
-				"mmss_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_ahb_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1024,8 +1036,8 @@ static struct clk_branch camss_csi0_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_csi0_clk",
-			.parent_names = (const char *[]){
-				"csi0_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&csi0_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1041,8 +1053,8 @@ static struct clk_branch camss_csi0phy_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_csi0phy_clk",
-			.parent_names = (const char *[]){
-				"csi0_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&csi0_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1058,8 +1070,8 @@ static struct clk_branch camss_csi0pix_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_csi0pix_clk",
-			.parent_names = (const char *[]){
-				"csi0_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&csi0_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1075,8 +1087,8 @@ static struct clk_branch camss_csi0rdi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_csi0rdi_clk",
-			.parent_names = (const char *[]){
-				"csi0_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&csi0_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1092,8 +1104,8 @@ static struct clk_branch camss_csi1_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_csi1_ahb_clk",
-			.parent_names = (const char *[]){
-				"mmss_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_ahb_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1108,8 +1120,8 @@ static struct clk_branch camss_csi1_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_csi1_clk",
-			.parent_names = (const char *[]){
-				"csi1_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&csi1_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1125,8 +1137,8 @@ static struct clk_branch camss_csi1phy_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_csi1phy_clk",
-			.parent_names = (const char *[]){
-				"csi1_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&csi1_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1142,8 +1154,8 @@ static struct clk_branch camss_csi1pix_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_csi1pix_clk",
-			.parent_names = (const char *[]){
-				"csi1_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&csi1_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1159,8 +1171,8 @@ static struct clk_branch camss_csi1rdi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_csi1rdi_clk",
-			.parent_names = (const char *[]){
-				"csi1_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&csi1_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1176,8 +1188,8 @@ static struct clk_branch camss_csi2_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_csi2_ahb_clk",
-			.parent_names = (const char *[]){
-				"mmss_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_ahb_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1192,8 +1204,8 @@ static struct clk_branch camss_csi2_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_csi2_clk",
-			.parent_names = (const char *[]){
-				"csi2_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&csi2_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1209,8 +1221,8 @@ static struct clk_branch camss_csi2phy_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_csi2phy_clk",
-			.parent_names = (const char *[]){
-				"csi2_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&csi2_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1226,8 +1238,8 @@ static struct clk_branch camss_csi2pix_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_csi2pix_clk",
-			.parent_names = (const char *[]){
-				"csi2_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&csi2_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1243,8 +1255,8 @@ static struct clk_branch camss_csi2rdi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_csi2rdi_clk",
-			.parent_names = (const char *[]){
-				"csi2_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&csi2_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1260,8 +1272,8 @@ static struct clk_branch camss_csi3_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_csi3_ahb_clk",
-			.parent_names = (const char *[]){
-				"mmss_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_ahb_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1276,8 +1288,8 @@ static struct clk_branch camss_csi3_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_csi3_clk",
-			.parent_names = (const char *[]){
-				"csi3_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&csi3_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1293,8 +1305,8 @@ static struct clk_branch camss_csi3phy_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_csi3phy_clk",
-			.parent_names = (const char *[]){
-				"csi3_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&csi3_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1310,8 +1322,8 @@ static struct clk_branch camss_csi3pix_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_csi3pix_clk",
-			.parent_names = (const char *[]){
-				"csi3_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&csi3_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1327,8 +1339,8 @@ static struct clk_branch camss_csi3rdi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_csi3rdi_clk",
-			.parent_names = (const char *[]){
-				"csi3_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&csi3_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1344,8 +1356,8 @@ static struct clk_branch camss_csi_vfe0_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_csi_vfe0_clk",
-			.parent_names = (const char *[]){
-				"vfe0_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&vfe0_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1361,8 +1373,8 @@ static struct clk_branch camss_csi_vfe1_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_csi_vfe1_clk",
-			.parent_names = (const char *[]){
-				"vfe1_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&vfe1_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1378,8 +1390,8 @@ static struct clk_branch camss_gp0_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_gp0_clk",
-			.parent_names = (const char *[]){
-				"camss_gp0_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&camss_gp0_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1395,8 +1407,8 @@ static struct clk_branch camss_gp1_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_gp1_clk",
-			.parent_names = (const char *[]){
-				"camss_gp1_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&camss_gp1_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1412,8 +1424,8 @@ static struct clk_branch camss_ispif_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_ispif_ahb_clk",
-			.parent_names = (const char *[]){
-				"mmss_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_ahb_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1428,8 +1440,8 @@ static struct clk_branch camss_jpeg_jpeg0_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_jpeg_jpeg0_clk",
-			.parent_names = (const char *[]){
-				"jpeg0_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&jpeg0_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1445,8 +1457,8 @@ static struct clk_branch camss_jpeg_jpeg1_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_jpeg_jpeg1_clk",
-			.parent_names = (const char *[]){
-				"jpeg1_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&jpeg1_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1462,8 +1474,8 @@ static struct clk_branch camss_jpeg_jpeg2_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_jpeg_jpeg2_clk",
-			.parent_names = (const char *[]){
-				"jpeg2_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&jpeg2_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1479,8 +1491,8 @@ static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_jpeg_jpeg_ahb_clk",
-			.parent_names = (const char *[]){
-				"mmss_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_ahb_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1495,8 +1507,8 @@ static struct clk_branch camss_jpeg_jpeg_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_jpeg_jpeg_axi_clk",
-			.parent_names = (const char *[]){
-				"mmss_axi_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_axi_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1511,8 +1523,8 @@ static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_jpeg_jpeg_ocmemnoc_clk",
-			.parent_names = (const char *[]){
-				"ocmemnoc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&ocmemnoc_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1528,8 +1540,8 @@ static struct clk_branch camss_mclk0_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_mclk0_clk",
-			.parent_names = (const char *[]){
-				"mclk0_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mclk0_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1545,8 +1557,8 @@ static struct clk_branch camss_mclk1_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_mclk1_clk",
-			.parent_names = (const char *[]){
-				"mclk1_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mclk1_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1562,8 +1574,8 @@ static struct clk_branch camss_mclk2_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_mclk2_clk",
-			.parent_names = (const char *[]){
-				"mclk2_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mclk2_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1579,8 +1591,8 @@ static struct clk_branch camss_mclk3_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_mclk3_clk",
-			.parent_names = (const char *[]){
-				"mclk3_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mclk3_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1596,8 +1608,8 @@ static struct clk_branch camss_micro_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_micro_ahb_clk",
-			.parent_names = (const char *[]){
-				"mmss_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_ahb_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1612,8 +1624,8 @@ static struct clk_branch camss_phy0_csi0phytimer_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_phy0_csi0phytimer_clk",
-			.parent_names = (const char *[]){
-				"csi0phytimer_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&csi0phytimer_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1629,8 +1641,8 @@ static struct clk_branch camss_phy1_csi1phytimer_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_phy1_csi1phytimer_clk",
-			.parent_names = (const char *[]){
-				"csi1phytimer_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&csi1phytimer_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1646,8 +1658,8 @@ static struct clk_branch camss_phy2_csi2phytimer_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_phy2_csi2phytimer_clk",
-			.parent_names = (const char *[]){
-				"csi2phytimer_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&csi2phytimer_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1663,8 +1675,8 @@ static struct clk_branch camss_top_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_top_ahb_clk",
-			.parent_names = (const char *[]){
-				"mmss_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_ahb_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1679,8 +1691,8 @@ static struct clk_branch camss_vfe_cpp_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_vfe_cpp_ahb_clk",
-			.parent_names = (const char *[]){
-				"mmss_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_ahb_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1695,8 +1707,8 @@ static struct clk_branch camss_vfe_cpp_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_vfe_cpp_clk",
-			.parent_names = (const char *[]){
-				"cpp_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cpp_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1712,8 +1724,8 @@ static struct clk_branch camss_vfe_vfe0_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_vfe_vfe0_clk",
-			.parent_names = (const char *[]){
-				"vfe0_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&vfe0_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1729,8 +1741,8 @@ static struct clk_branch camss_vfe_vfe1_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_vfe_vfe1_clk",
-			.parent_names = (const char *[]){
-				"vfe1_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&vfe1_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1746,8 +1758,8 @@ static struct clk_branch camss_vfe_vfe_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_vfe_vfe_ahb_clk",
-			.parent_names = (const char *[]){
-				"mmss_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_ahb_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1762,8 +1774,8 @@ static struct clk_branch camss_vfe_vfe_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_vfe_vfe_axi_clk",
-			.parent_names = (const char *[]){
-				"mmss_axi_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_axi_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1778,8 +1790,8 @@ static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "camss_vfe_vfe_ocmemnoc_clk",
-			.parent_names = (const char *[]){
-				"ocmemnoc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&ocmemnoc_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1795,8 +1807,8 @@ static struct clk_branch mdss_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "mdss_ahb_clk",
-			.parent_names = (const char *[]){
-				"mmss_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_ahb_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1811,8 +1823,8 @@ static struct clk_branch mdss_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "mdss_axi_clk",
-			.parent_names = (const char *[]){
-				"mmss_axi_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_axi_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1828,8 +1840,8 @@ static struct clk_branch mdss_byte0_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "mdss_byte0_clk",
-			.parent_names = (const char *[]){
-				"byte0_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&byte0_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1845,8 +1857,8 @@ static struct clk_branch mdss_byte1_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "mdss_byte1_clk",
-			.parent_names = (const char *[]){
-				"byte1_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&byte1_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1862,8 +1874,8 @@ static struct clk_branch mdss_edpaux_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "mdss_edpaux_clk",
-			.parent_names = (const char *[]){
-				"edpaux_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&edpaux_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1879,8 +1891,8 @@ static struct clk_branch mdss_edplink_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "mdss_edplink_clk",
-			.parent_names = (const char *[]){
-				"edplink_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&edplink_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1896,8 +1908,8 @@ static struct clk_branch mdss_edppixel_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "mdss_edppixel_clk",
-			.parent_names = (const char *[]){
-				"edppixel_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&edppixel_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1913,8 +1925,8 @@ static struct clk_branch mdss_esc0_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "mdss_esc0_clk",
-			.parent_names = (const char *[]){
-				"esc0_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&esc0_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1930,8 +1942,8 @@ static struct clk_branch mdss_esc1_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "mdss_esc1_clk",
-			.parent_names = (const char *[]){
-				"esc1_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&esc1_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1947,8 +1959,8 @@ static struct clk_branch mdss_extpclk_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "mdss_extpclk_clk",
-			.parent_names = (const char *[]){
-				"extpclk_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&extpclk_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1964,8 +1976,8 @@ static struct clk_branch mdss_hdmi_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "mdss_hdmi_ahb_clk",
-			.parent_names = (const char *[]){
-				"mmss_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_ahb_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1980,8 +1992,8 @@ static struct clk_branch mdss_hdmi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "mdss_hdmi_clk",
-			.parent_names = (const char *[]){
-				"hdmi_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&hdmi_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1997,8 +2009,8 @@ static struct clk_branch mdss_mdp_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "mdss_mdp_clk",
-			.parent_names = (const char *[]){
-				"mdp_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mdp_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2014,8 +2026,8 @@ static struct clk_branch mdss_mdp_lut_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "mdss_mdp_lut_clk",
-			.parent_names = (const char *[]){
-				"mdp_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mdp_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2031,8 +2043,8 @@ static struct clk_branch mdss_pclk0_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "mdss_pclk0_clk",
-			.parent_names = (const char *[]){
-				"pclk0_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&pclk0_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2048,8 +2060,8 @@ static struct clk_branch mdss_pclk1_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "mdss_pclk1_clk",
-			.parent_names = (const char *[]){
-				"pclk1_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&pclk1_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2065,8 +2077,8 @@ static struct clk_branch mdss_vsync_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "mdss_vsync_clk",
-			.parent_names = (const char *[]){
-				"vsync_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&vsync_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2082,8 +2094,8 @@ static struct clk_branch mmss_misc_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "mmss_misc_ahb_clk",
-			.parent_names = (const char *[]){
-				"mmss_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_ahb_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2098,8 +2110,8 @@ static struct clk_branch mmss_mmssnoc_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "mmss_mmssnoc_ahb_clk",
-			.parent_names = (const char *[]){
-				"mmss_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_ahb_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2115,8 +2127,8 @@ static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "mmss_mmssnoc_bto_ahb_clk",
-			.parent_names = (const char *[]){
-				"mmss_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_ahb_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2132,8 +2144,8 @@ static struct clk_branch mmss_mmssnoc_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "mmss_mmssnoc_axi_clk",
-			.parent_names = (const char *[]){
-				"mmss_axi_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_axi_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
@@ -2149,8 +2161,8 @@ static struct clk_branch mmss_s0_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "mmss_s0_axi_clk",
-			.parent_names = (const char *[]){
-				"mmss_axi_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_axi_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2166,8 +2178,8 @@ static struct clk_branch ocmemcx_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "ocmemcx_ahb_clk",
-			.parent_names = (const char *[]){
-				"mmss_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_ahb_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2182,8 +2194,8 @@ static struct clk_branch ocmemcx_ocmemnoc_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "ocmemcx_ocmemnoc_clk",
-			.parent_names = (const char *[]){
-				"ocmemnoc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&ocmemnoc_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2199,8 +2211,8 @@ static struct clk_branch oxili_ocmemgx_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "oxili_ocmemgx_clk",
-			.parent_names = (const char *[]){
-				"gfx3d_clk_src",
+			.parent_data = (const struct clk_parent_data[]){
+				{ .fw_name = "gfx3d_clk_src", .name = "gfx3d_clk_src" },
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2216,8 +2228,8 @@ static struct clk_branch ocmemnoc_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "ocmemnoc_clk",
-			.parent_names = (const char *[]){
-				"ocmemnoc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&ocmemnoc_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2233,8 +2245,8 @@ static struct clk_branch oxili_gfx3d_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "oxili_gfx3d_clk",
-			.parent_names = (const char *[]){
-				"gfx3d_clk_src",
+			.parent_data = (const struct clk_parent_data[]){
+				{ .fw_name = "gfx3d_clk_src", .name = "gfx3d_clk_src" },
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2250,8 +2262,8 @@ static struct clk_branch oxilicx_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "oxilicx_ahb_clk",
-			.parent_names = (const char *[]){
-				"mmss_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_ahb_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2266,8 +2278,8 @@ static struct clk_branch oxilicx_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "oxilicx_axi_clk",
-			.parent_names = (const char *[]){
-				"mmss_axi_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_axi_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2282,8 +2294,8 @@ static struct clk_branch venus0_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "venus0_ahb_clk",
-			.parent_names = (const char *[]){
-				"mmss_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_ahb_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2298,8 +2310,8 @@ static struct clk_branch venus0_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "venus0_axi_clk",
-			.parent_names = (const char *[]){
-				"mmss_axi_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&mmss_axi_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -2314,8 +2326,8 @@ static struct clk_branch venus0_ocmemnoc_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "venus0_ocmemnoc_clk",
-			.parent_names = (const char *[]){
-				"ocmemnoc_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&ocmemnoc_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2331,8 +2343,8 @@ static struct clk_branch venus0_vcodec0_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "venus0_vcodec0_clk",
-			.parent_names = (const char *[]){
-				"vcodec0_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&vcodec0_clk_src.clkr.hw
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
-- 
2.35.1

[PATCH v3 09/11] ARM: dts: qcom: msm8974: add second DSI host and PHY

[Dmitry Baryshkov]

Add second DSI host and PHY available on the msm8974 platform.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm/boot/dts/qcom-msm8974.dtsi | 77 +++++++++++++++++++++++++++++
 1 file changed, 77 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 7647cf9f2f76..7f8b4356ccdb 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1542,6 +1542,13 @@ mdp5_intf1_out: endpoint {
 							remote-endpoint = <&dsi0_in>;
 						};
 					};
+
+					port@1 {
+						reg = <1>;
+						mdp5_intf2_out: endpoint {
+							remote-endpoint = <&dsi1_in>;
+						};
+					};
 				};
 			};
 
@@ -1614,6 +1621,76 @@ dsi0_phy: phy@fd922a00 {
 
 				status = "disabled";
 			};
+
+			dsi1: dsi@fd922e00 {
+				compatible = "qcom,mdss-dsi-ctrl";
+				reg = <0xfd922e00 0x1f8>;
+				reg-names = "dsi_ctrl";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <4>;
+
+				assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
+				assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
+
+				clocks = <&mmcc MDSS_MDP_CLK>,
+					 <&mmcc MDSS_AHB_CLK>,
+					 <&mmcc MDSS_AXI_CLK>,
+					 <&mmcc MDSS_BYTE1_CLK>,
+					 <&mmcc MDSS_PCLK1_CLK>,
+					 <&mmcc MDSS_ESC1_CLK>,
+					 <&mmcc MMSS_MISC_AHB_CLK>;
+				clock-names = "mdp_core",
+					      "iface",
+					      "bus",
+					      "byte",
+					      "pixel",
+					      "core",
+					      "core_mmss";
+
+				phys = <&dsi1_phy>;
+
+				status = "disabled";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						dsi1_in: endpoint {
+							remote-endpoint = <&mdp5_intf2_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						dsi1_out: endpoint {
+						};
+					};
+				};
+			};
+
+			dsi1_phy: phy@fd923000 {
+				compatible = "qcom,dsi-phy-28nm-hpm";
+				reg = <0xfd923000 0xd4>,
+				      <0xfd923100 0x280>,
+				      <0xfd923380 0x30>;
+				reg-names = "dsi_pll",
+					    "dsi_phy",
+					    "dsi_phy_regulator";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
+				clock-names = "iface", "ref";
+
+				status = "disabled";
+			};
 		};
 
 		gpu: adreno@fdb00000 {
-- 
2.35.1

[PATCH v3 10/11] ARM: dts: qcom: msm8974: add clocks and clock-names to gcc device

[Dmitry Baryshkov]

Add clocks and clock-names nodes to the gcc device to bind clocks using
the DT links.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm/boot/dts/qcom-msm8974.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 7f8b4356ccdb..4e70f51c8750 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1054,6 +1054,10 @@ gcc: clock-controller@fc400000 {
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
 			reg = <0xfc400000 0x4000>;
+
+			clock-names = "xo", "sleep_clk";
+			clocks = <&xo_board>,
+				 <&sleep_clk>;
 		};
 
 		rpm_msg_ram: sram@fc428000 {
-- 
2.35.1

[PATCH v3 11/11] ARM: dts: qcom: msm8974: add clocks and clock-names to mmcc device

[Dmitry Baryshkov]

Add clocks and clock-names nodes to the mmcc device to bind clocks using
the DT links.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm/boot/dts/qcom-msm8974.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 4e70f51c8750..21abbff2a4df 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1494,6 +1494,30 @@ mmcc: clock-controller@fd8c0000 {
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
 			reg = <0xfd8c0000 0x6000>;
+			clocks = <&xo_board>,
+				 <&gcc GCC_MMSS_GPLL0_CLK_SRC>,
+				 <&gcc GPLL0_VOTE>,
+				 <&gcc GPLL1_VOTE>,
+				 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
+				 <&dsi0_phy 1>,
+				 <&dsi0_phy 0>,
+				 <&dsi1_phy 1>,
+				 <&dsi1_phy 0>,
+				 <0>,
+				 <0>,
+				 <0>;
+			clock-names = "xo",
+				      "mmss_gpll0_vote",
+				      "gpll0_vote",
+				      "gpll1_vote",
+				      "gfx3d_clk_src",
+				      "dsi0pll",
+				      "dsi0pllbyte",
+				      "dsi1pll",
+				      "dsi1pllbyte",
+				      "hdmipll",
+				      "edp_link_clk",
+				      "edp_vco_div";
 		};
 
 		mdss: mdss@fd900000 {
-- 
2.35.1

Re: [PATCH v3 11/11] ARM: dts: qcom: msm8974: add clocks and clock-names to mmcc device

[Konrad Dybcio]

On 30.10.2022 16:55, Dmitry Baryshkov wrote:
> Add clocks and clock-names nodes to the mmcc device to bind clocks using
> the DT links.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>

Konrad
>  arch/arm/boot/dts/qcom-msm8974.dtsi | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
> index 4e70f51c8750..21abbff2a4df 100644
> --- a/arch/arm/boot/dts/qcom-msm8974.dtsi
> +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
> @@ -1494,6 +1494,30 @@ mmcc: clock-controller@fd8c0000 {
>  			#reset-cells = <1>;
>  			#power-domain-cells = <1>;
>  			reg = <0xfd8c0000 0x6000>;
> +			clocks = <&xo_board>,
> +				 <&gcc GCC_MMSS_GPLL0_CLK_SRC>,
> +				 <&gcc GPLL0_VOTE>,
> +				 <&gcc GPLL1_VOTE>,
> +				 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
> +				 <&dsi0_phy 1>,
> +				 <&dsi0_phy 0>,
> +				 <&dsi1_phy 1>,
> +				 <&dsi1_phy 0>,
> +				 <0>,
> +				 <0>,
> +				 <0>;
> +			clock-names = "xo",
> +				      "mmss_gpll0_vote",
> +				      "gpll0_vote",
> +				      "gpll1_vote",
> +				      "gfx3d_clk_src",
> +				      "dsi0pll",
> +				      "dsi0pllbyte",
> +				      "dsi1pll",
> +				      "dsi1pllbyte",
> +				      "hdmipll",
> +				      "edp_link_clk",
> +				      "edp_vco_div";
>  		};
>  
>  		mdss: mdss@fd900000 {

Re: [PATCH v3 10/11] ARM: dts: qcom: msm8974: add clocks and clock-names to gcc device

[Konrad Dybcio]

On 30.10.2022 16:55, Dmitry Baryshkov wrote:
> Add clocks and clock-names nodes to the gcc device to bind clocks using
> the DT links.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  arch/arm/boot/dts/qcom-msm8974.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
> index 7f8b4356ccdb..4e70f51c8750 100644
> --- a/arch/arm/boot/dts/qcom-msm8974.dtsi
> +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
> @@ -1054,6 +1054,10 @@ gcc: clock-controller@fc400000 {
>  			#reset-cells = <1>;
>  			#power-domain-cells = <1>;
>  			reg = <0xfc400000 0x4000>;
> +
> +			clock-names = "xo", "sleep_clk";
> +			clocks = <&xo_board>,
> +				 <&sleep_clk>;
I think it would make sense to either have both properties take up either
one or two lines.

Other than that though:

Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>

Konrad

>  		};
>  
>  		rpm_msg_ram: sram@fc428000 {

Re: [PATCH v3 08/11] clk: qcom: mmcc-msm8974: use parent_hws/_data instead of parent_names

[Konrad Dybcio]

On 30.10.2022 16:55, Dmitry Baryshkov wrote:
> Convert the clock driver to specify parent data rather than parent
> names, to actually bind using 'clock-names' specified in the DTS rather
> than global clock names. Use parent_hws where possible to refer parent
> clocks directly, skipping the lookup.
> 
> Note, the system names for xo clocks were changed from "xo" to
> "xo_board" to follow the example of other platforms.
I think it should be reverse - look for "xo" and pass "xo_board" through DT.

Konrad
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  drivers/clk/qcom/mmcc-msm8974.c | 516 ++++++++++++++++----------------
>  1 file changed, 264 insertions(+), 252 deletions(-)
> 
> diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
> index 57f1a351c8f6..4273fce9a4a4 100644
> --- a/drivers/clk/qcom/mmcc-msm8974.c
> +++ b/drivers/clk/qcom/mmcc-msm8974.c
> @@ -52,7 +52,9 @@ static struct clk_pll mmpll0 = {
>  	.status_bit = 17,
>          .clkr.hw.init = &(struct clk_init_data){
>                  .name = "mmpll0",
> -                .parent_names = (const char *[]){ "xo" },
> +                .parent_data = (const struct clk_parent_data[]){
> +			{ .fw_name = "xo", .name = "xo_board" },
> +		},
>                  .num_parents = 1,
>                  .ops = &clk_pll_ops,
>          },
> @@ -63,7 +65,9 @@ static struct clk_regmap mmpll0_vote = {
>  	.enable_mask = BIT(0),
>  	.hw.init = &(struct clk_init_data){
>  		.name = "mmpll0_vote",
> -		.parent_names = (const char *[]){ "mmpll0" },
> +		.parent_hws = (const struct clk_hw*[]){
> +			&mmpll0.clkr.hw
> +		},
>  		.num_parents = 1,
>  		.ops = &clk_pll_vote_ops,
>  	},
> @@ -79,7 +83,9 @@ static struct clk_pll mmpll1 = {
>  	.status_bit = 17,
>          .clkr.hw.init = &(struct clk_init_data){
>                  .name = "mmpll1",
> -                .parent_names = (const char *[]){ "xo" },
> +                .parent_data = (const struct clk_parent_data[]){
> +			{ .fw_name = "xo", .name = "xo_board" },
> +		},
>                  .num_parents = 1,
>                  .ops = &clk_pll_ops,
>          },
> @@ -90,7 +96,9 @@ static struct clk_regmap mmpll1_vote = {
>  	.enable_mask = BIT(1),
>  	.hw.init = &(struct clk_init_data){
>  		.name = "mmpll1_vote",
> -		.parent_names = (const char *[]){ "mmpll1" },
> +		.parent_hws = (const struct clk_hw*[]){
> +			&mmpll1.clkr.hw
> +		},
>  		.num_parents = 1,
>  		.ops = &clk_pll_vote_ops,
>  	},
> @@ -105,7 +113,9 @@ static struct clk_pll mmpll2 = {
>  	.status_reg = 0x411c,
>          .clkr.hw.init = &(struct clk_init_data){
>                  .name = "mmpll2",
> -                .parent_names = (const char *[]){ "xo" },
> +                .parent_data = (const struct clk_parent_data[]){
> +			{ .fw_name = "xo", .name = "xo_board" },
> +		},
>                  .num_parents = 1,
>                  .ops = &clk_pll_ops,
>          },
> @@ -121,7 +131,9 @@ static struct clk_pll mmpll3 = {
>  	.status_bit = 17,
>          .clkr.hw.init = &(struct clk_init_data){
>                  .name = "mmpll3",
> -                .parent_names = (const char *[]){ "xo" },
> +                .parent_data = (const struct clk_parent_data[]){
> +			{ .fw_name = "xo", .name = "xo_board" },
> +		},
>                  .num_parents = 1,
>                  .ops = &clk_pll_ops,
>          },
> @@ -134,11 +146,11 @@ static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
>  	{ P_GPLL0, 5 }
>  };
>  
> -static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
> -	"xo",
> -	"mmpll0_vote",
> -	"mmpll1_vote",
> -	"mmss_gpll0_vote",
> +static const struct clk_parent_data mmcc_xo_mmpll0_mmpll1_gpll0[] = {
> +	{ .fw_name = "xo", .name = "xo_board" },
> +	{ .hw = &mmpll0_vote.hw },
> +	{ .hw = &mmpll1_vote.hw },
> +	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
>  };
>  
>  static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
> @@ -150,13 +162,13 @@ static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
>  	{ P_DSI1PLL, 3 }
>  };
>  
> -static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
> -	"xo",
> -	"mmpll0_vote",
> -	"hdmipll",
> -	"mmss_gpll0_vote",
> -	"dsi0pll",
> -	"dsi1pll",
> +static const struct clk_parent_data mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
> +	{ .fw_name = "xo", .name = "xo_board" },
> +	{ .hw = &mmpll0_vote.hw },
> +	{ .fw_name = "hdmipll", .name = "hdmipll" },
> +	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
> +	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
> +	{ .fw_name = "dsi1pll", .name = "dsi1pll" },
>  };
>  
>  static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
> @@ -167,12 +179,12 @@ static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
>  	{ P_MMPLL3, 3 }
>  };
>  
> -static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
> -	"xo",
> -	"mmpll0_vote",
> -	"mmpll1_vote",
> -	"mmss_gpll0_vote",
> -	"mmpll3",
> +static const struct clk_parent_data mmcc_xo_mmpll0_1_3_gpll0[] = {
> +	{ .fw_name = "xo", .name = "xo_board" },
> +	{ .hw = &mmpll0_vote.hw },
> +	{ .hw = &mmpll1_vote.hw },
> +	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
> +	{ .hw = &mmpll3.clkr.hw },
>  };
>  
>  static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
> @@ -183,12 +195,12 @@ static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
>  	{ P_GPLL1, 4 }
>  };
>  
> -static const char * const mmcc_xo_mmpll0_1_gpll1_0[] = {
> -	"xo",
> -	"mmpll0_vote",
> -	"mmpll1_vote",
> -	"mmss_gpll0_vote",
> -	"gpll1_vote",
> +static const struct clk_parent_data mmcc_xo_mmpll0_1_gpll1_0[] = {
> +	{ .fw_name = "xo", .name = "xo_board" },
> +	{ .hw = &mmpll0_vote.hw },
> +	{ .hw = &mmpll1_vote.hw },
> +	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
> +	{ .fw_name = "gpll1_vote", .name = "gpll1_vote" },
>  };
>  
>  static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
> @@ -200,13 +212,13 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
>  	{ P_DSI1PLL, 2 }
>  };
>  
> -static const char * const mmcc_xo_dsi_hdmi_edp[] = {
> -	"xo",
> -	"edp_link_clk",
> -	"hdmipll",
> -	"edp_vco_div",
> -	"dsi0pll",
> -	"dsi1pll",
> +static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp[] = {
> +	{ .fw_name = "xo", .name = "xo_board" },
> +	{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
> +	{ .fw_name = "hdmipll", .name = "hdmipll" },
> +	{ .fw_name = "edp_vco_div", .name = "edp_vco_div" },
> +	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
> +	{ .fw_name = "dsi1pll", .name = "dsi1pll" },
>  };
>  
>  static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
> @@ -218,13 +230,13 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
>  	{ P_DSI1PLL, 2 }
>  };
>  
> -static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
> -	"xo",
> -	"edp_link_clk",
> -	"hdmipll",
> -	"gpll0_vote",
> -	"dsi0pll",
> -	"dsi1pll",
> +static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp_gpll0[] = {
> +	{ .fw_name = "xo", .name = "xo_board" },
> +	{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
> +	{ .fw_name = "hdmipll", .name = "hdmipll" },
> +	{ .fw_name = "gpll0_vote", .name = "gpll0_vote" },
> +	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
> +	{ .fw_name = "dsi1pll", .name = "dsi1pll" },
>  };
>  
>  static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
> @@ -236,13 +248,13 @@ static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
>  	{ P_DSI1PLL_BYTE, 2 }
>  };
>  
> -static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
> -	"xo",
> -	"edp_link_clk",
> -	"hdmipll",
> -	"gpll0_vote",
> -	"dsi0pllbyte",
> -	"dsi1pllbyte",
> +static const struct clk_parent_data mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
> +	{ .fw_name = "xo", .name = "xo_board" },
> +	{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
> +	{ .fw_name = "hdmipll", .name = "hdmipll" },
> +	{ .fw_name = "gpll0_vote", .name = "gpll0_vote" },
> +	{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
> +	{ .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" },
>  };
>  
>  static struct clk_rcg2 mmss_ahb_clk_src = {
> @@ -251,7 +263,7 @@ static struct clk_rcg2 mmss_ahb_clk_src = {
>  	.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "mmss_ahb_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -288,7 +300,7 @@ static struct clk_rcg2 mmss_axi_clk_src = {
>  	.freq_tbl = ftbl_mmss_axi_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "mmss_axi_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -312,7 +324,7 @@ static struct clk_rcg2 ocmemnoc_clk_src = {
>  	.freq_tbl = ftbl_ocmemnoc_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "ocmemnoc_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -331,7 +343,7 @@ static struct clk_rcg2 csi0_clk_src = {
>  	.freq_tbl = ftbl_camss_csi0_3_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "csi0_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -344,7 +356,7 @@ static struct clk_rcg2 csi1_clk_src = {
>  	.freq_tbl = ftbl_camss_csi0_3_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "csi1_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -357,7 +369,7 @@ static struct clk_rcg2 csi2_clk_src = {
>  	.freq_tbl = ftbl_camss_csi0_3_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "csi2_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -370,7 +382,7 @@ static struct clk_rcg2 csi3_clk_src = {
>  	.freq_tbl = ftbl_camss_csi0_3_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "csi3_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -417,7 +429,7 @@ static struct clk_rcg2 vfe0_clk_src = {
>  	.freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "vfe0_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -430,7 +442,7 @@ static struct clk_rcg2 vfe1_clk_src = {
>  	.freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "vfe1_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -471,7 +483,7 @@ static struct clk_rcg2 mdp_clk_src = {
>  	.freq_tbl = ftbl_mdss_mdp_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "mdp_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -494,7 +506,7 @@ static struct clk_rcg2 jpeg0_clk_src = {
>  	.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "jpeg0_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -507,7 +519,7 @@ static struct clk_rcg2 jpeg1_clk_src = {
>  	.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "jpeg1_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -520,7 +532,7 @@ static struct clk_rcg2 jpeg2_clk_src = {
>  	.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "jpeg2_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -533,7 +545,7 @@ static struct clk_rcg2 pclk0_clk_src = {
>  	.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "pclk0_clk_src",
> -		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> +		.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
>  		.ops = &clk_pixel_ops,
>  		.flags = CLK_SET_RATE_PARENT,
> @@ -547,7 +559,7 @@ static struct clk_rcg2 pclk1_clk_src = {
>  	.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "pclk1_clk_src",
> -		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> +		.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
>  		.ops = &clk_pixel_ops,
>  		.flags = CLK_SET_RATE_PARENT,
> @@ -580,7 +592,7 @@ static struct clk_rcg2 vcodec0_clk_src = {
>  	.freq_tbl = ftbl_venus0_vcodec0_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "vcodec0_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_1_3_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_1_3_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -598,7 +610,7 @@ static struct clk_rcg2 cci_clk_src = {
>  	.freq_tbl = ftbl_camss_cci_cci_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cci_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -622,7 +634,7 @@ static struct clk_rcg2 camss_gp0_clk_src = {
>  	.freq_tbl = ftbl_camss_gp0_1_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "camss_gp0_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_1_gpll1_0,
> +		.parent_data = mmcc_xo_mmpll0_1_gpll1_0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -636,7 +648,7 @@ static struct clk_rcg2 camss_gp1_clk_src = {
>  	.freq_tbl = ftbl_camss_gp0_1_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "camss_gp1_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_1_gpll1_0,
> +		.parent_data = mmcc_xo_mmpll0_1_gpll1_0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -671,7 +683,7 @@ static struct clk_rcg2 mclk0_clk_src = {
>  	.freq_tbl = ftbl_camss_mclk0_3_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "mclk0_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -684,7 +696,7 @@ static struct clk_rcg2 mclk1_clk_src = {
>  	.freq_tbl = ftbl_camss_mclk0_3_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "mclk1_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -697,7 +709,7 @@ static struct clk_rcg2 mclk2_clk_src = {
>  	.freq_tbl = ftbl_camss_mclk0_3_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "mclk2_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -710,7 +722,7 @@ static struct clk_rcg2 mclk3_clk_src = {
>  	.freq_tbl = ftbl_camss_mclk0_3_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "mclk3_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -729,7 +741,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = {
>  	.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "csi0phytimer_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -742,7 +754,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = {
>  	.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "csi1phytimer_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -755,7 +767,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = {
>  	.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "csi2phytimer_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -786,7 +798,7 @@ static struct clk_rcg2 cpp_clk_src = {
>  	.freq_tbl = ftbl_camss_vfe_cpp_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cpp_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -804,7 +816,7 @@ static struct clk_rcg2 byte0_clk_src = {
>  	.freq_tbl = byte_freq_tbl,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "byte0_clk_src",
> -		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> +		.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
>  		.ops = &clk_byte2_ops,
>  		.flags = CLK_SET_RATE_PARENT,
> @@ -818,7 +830,7 @@ static struct clk_rcg2 byte1_clk_src = {
>  	.freq_tbl = byte_freq_tbl,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "byte1_clk_src",
> -		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> +		.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
>  		.ops = &clk_byte2_ops,
>  		.flags = CLK_SET_RATE_PARENT,
> @@ -837,7 +849,7 @@ static struct clk_rcg2 edpaux_clk_src = {
>  	.freq_tbl = ftbl_mdss_edpaux_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "edpaux_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -856,7 +868,7 @@ static struct clk_rcg2 edplink_clk_src = {
>  	.freq_tbl = ftbl_mdss_edplink_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "edplink_clk_src",
> -		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> +		.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
>  		.ops = &clk_rcg2_ops,
>  		.flags = CLK_SET_RATE_PARENT,
> @@ -876,7 +888,7 @@ static struct clk_rcg2 edppixel_clk_src = {
>  	.freq_tbl = edp_pixel_freq_tbl,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "edppixel_clk_src",
> -		.parent_names = mmcc_xo_dsi_hdmi_edp,
> +		.parent_data = mmcc_xo_dsi_hdmi_edp,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp),
>  		.ops = &clk_edp_pixel_ops,
>  	},
> @@ -894,7 +906,7 @@ static struct clk_rcg2 esc0_clk_src = {
>  	.freq_tbl = ftbl_mdss_esc0_1_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "esc0_clk_src",
> -		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> +		.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -907,7 +919,7 @@ static struct clk_rcg2 esc1_clk_src = {
>  	.freq_tbl = ftbl_mdss_esc0_1_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "esc1_clk_src",
> -		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> +		.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -925,7 +937,7 @@ static struct clk_rcg2 extpclk_clk_src = {
>  	.freq_tbl = extpclk_freq_tbl,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "extpclk_clk_src",
> -		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> +		.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
>  		.ops = &clk_byte_ops,
>  		.flags = CLK_SET_RATE_PARENT,
> @@ -944,7 +956,7 @@ static struct clk_rcg2 hdmi_clk_src = {
>  	.freq_tbl = ftbl_mdss_hdmi_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "hdmi_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -962,7 +974,7 @@ static struct clk_rcg2 vsync_clk_src = {
>  	.freq_tbl = ftbl_mdss_vsync_clk,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "vsync_clk_src",
> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -975,8 +987,8 @@ static struct clk_branch camss_cci_cci_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_cci_cci_ahb_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_ahb_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -991,8 +1003,8 @@ static struct clk_branch camss_cci_cci_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_cci_cci_clk",
> -			.parent_names = (const char *[]){
> -				"cci_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cci_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1008,8 +1020,8 @@ static struct clk_branch camss_csi0_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_csi0_ahb_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_ahb_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -1024,8 +1036,8 @@ static struct clk_branch camss_csi0_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_csi0_clk",
> -			.parent_names = (const char *[]){
> -				"csi0_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&csi0_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1041,8 +1053,8 @@ static struct clk_branch camss_csi0phy_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_csi0phy_clk",
> -			.parent_names = (const char *[]){
> -				"csi0_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&csi0_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1058,8 +1070,8 @@ static struct clk_branch camss_csi0pix_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_csi0pix_clk",
> -			.parent_names = (const char *[]){
> -				"csi0_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&csi0_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1075,8 +1087,8 @@ static struct clk_branch camss_csi0rdi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_csi0rdi_clk",
> -			.parent_names = (const char *[]){
> -				"csi0_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&csi0_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1092,8 +1104,8 @@ static struct clk_branch camss_csi1_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_csi1_ahb_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_ahb_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -1108,8 +1120,8 @@ static struct clk_branch camss_csi1_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_csi1_clk",
> -			.parent_names = (const char *[]){
> -				"csi1_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&csi1_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1125,8 +1137,8 @@ static struct clk_branch camss_csi1phy_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_csi1phy_clk",
> -			.parent_names = (const char *[]){
> -				"csi1_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&csi1_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1142,8 +1154,8 @@ static struct clk_branch camss_csi1pix_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_csi1pix_clk",
> -			.parent_names = (const char *[]){
> -				"csi1_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&csi1_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1159,8 +1171,8 @@ static struct clk_branch camss_csi1rdi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_csi1rdi_clk",
> -			.parent_names = (const char *[]){
> -				"csi1_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&csi1_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1176,8 +1188,8 @@ static struct clk_branch camss_csi2_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_csi2_ahb_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_ahb_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -1192,8 +1204,8 @@ static struct clk_branch camss_csi2_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_csi2_clk",
> -			.parent_names = (const char *[]){
> -				"csi2_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&csi2_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1209,8 +1221,8 @@ static struct clk_branch camss_csi2phy_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_csi2phy_clk",
> -			.parent_names = (const char *[]){
> -				"csi2_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&csi2_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1226,8 +1238,8 @@ static struct clk_branch camss_csi2pix_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_csi2pix_clk",
> -			.parent_names = (const char *[]){
> -				"csi2_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&csi2_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1243,8 +1255,8 @@ static struct clk_branch camss_csi2rdi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_csi2rdi_clk",
> -			.parent_names = (const char *[]){
> -				"csi2_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&csi2_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1260,8 +1272,8 @@ static struct clk_branch camss_csi3_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_csi3_ahb_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_ahb_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -1276,8 +1288,8 @@ static struct clk_branch camss_csi3_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_csi3_clk",
> -			.parent_names = (const char *[]){
> -				"csi3_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&csi3_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1293,8 +1305,8 @@ static struct clk_branch camss_csi3phy_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_csi3phy_clk",
> -			.parent_names = (const char *[]){
> -				"csi3_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&csi3_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1310,8 +1322,8 @@ static struct clk_branch camss_csi3pix_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_csi3pix_clk",
> -			.parent_names = (const char *[]){
> -				"csi3_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&csi3_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1327,8 +1339,8 @@ static struct clk_branch camss_csi3rdi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_csi3rdi_clk",
> -			.parent_names = (const char *[]){
> -				"csi3_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&csi3_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1344,8 +1356,8 @@ static struct clk_branch camss_csi_vfe0_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_csi_vfe0_clk",
> -			.parent_names = (const char *[]){
> -				"vfe0_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&vfe0_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1361,8 +1373,8 @@ static struct clk_branch camss_csi_vfe1_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_csi_vfe1_clk",
> -			.parent_names = (const char *[]){
> -				"vfe1_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&vfe1_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1378,8 +1390,8 @@ static struct clk_branch camss_gp0_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_gp0_clk",
> -			.parent_names = (const char *[]){
> -				"camss_gp0_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&camss_gp0_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1395,8 +1407,8 @@ static struct clk_branch camss_gp1_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_gp1_clk",
> -			.parent_names = (const char *[]){
> -				"camss_gp1_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&camss_gp1_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1412,8 +1424,8 @@ static struct clk_branch camss_ispif_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_ispif_ahb_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_ahb_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -1428,8 +1440,8 @@ static struct clk_branch camss_jpeg_jpeg0_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_jpeg_jpeg0_clk",
> -			.parent_names = (const char *[]){
> -				"jpeg0_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&jpeg0_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1445,8 +1457,8 @@ static struct clk_branch camss_jpeg_jpeg1_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_jpeg_jpeg1_clk",
> -			.parent_names = (const char *[]){
> -				"jpeg1_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&jpeg1_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1462,8 +1474,8 @@ static struct clk_branch camss_jpeg_jpeg2_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_jpeg_jpeg2_clk",
> -			.parent_names = (const char *[]){
> -				"jpeg2_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&jpeg2_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1479,8 +1491,8 @@ static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_jpeg_jpeg_ahb_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_ahb_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -1495,8 +1507,8 @@ static struct clk_branch camss_jpeg_jpeg_axi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_jpeg_jpeg_axi_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_axi_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_axi_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -1511,8 +1523,8 @@ static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_jpeg_jpeg_ocmemnoc_clk",
> -			.parent_names = (const char *[]){
> -				"ocmemnoc_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&ocmemnoc_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1528,8 +1540,8 @@ static struct clk_branch camss_mclk0_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_mclk0_clk",
> -			.parent_names = (const char *[]){
> -				"mclk0_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mclk0_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1545,8 +1557,8 @@ static struct clk_branch camss_mclk1_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_mclk1_clk",
> -			.parent_names = (const char *[]){
> -				"mclk1_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mclk1_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1562,8 +1574,8 @@ static struct clk_branch camss_mclk2_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_mclk2_clk",
> -			.parent_names = (const char *[]){
> -				"mclk2_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mclk2_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1579,8 +1591,8 @@ static struct clk_branch camss_mclk3_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_mclk3_clk",
> -			.parent_names = (const char *[]){
> -				"mclk3_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mclk3_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1596,8 +1608,8 @@ static struct clk_branch camss_micro_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_micro_ahb_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_ahb_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -1612,8 +1624,8 @@ static struct clk_branch camss_phy0_csi0phytimer_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_phy0_csi0phytimer_clk",
> -			.parent_names = (const char *[]){
> -				"csi0phytimer_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&csi0phytimer_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1629,8 +1641,8 @@ static struct clk_branch camss_phy1_csi1phytimer_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_phy1_csi1phytimer_clk",
> -			.parent_names = (const char *[]){
> -				"csi1phytimer_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&csi1phytimer_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1646,8 +1658,8 @@ static struct clk_branch camss_phy2_csi2phytimer_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_phy2_csi2phytimer_clk",
> -			.parent_names = (const char *[]){
> -				"csi2phytimer_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&csi2phytimer_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1663,8 +1675,8 @@ static struct clk_branch camss_top_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_top_ahb_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_ahb_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -1679,8 +1691,8 @@ static struct clk_branch camss_vfe_cpp_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_vfe_cpp_ahb_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_ahb_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -1695,8 +1707,8 @@ static struct clk_branch camss_vfe_cpp_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_vfe_cpp_clk",
> -			.parent_names = (const char *[]){
> -				"cpp_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cpp_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1712,8 +1724,8 @@ static struct clk_branch camss_vfe_vfe0_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_vfe_vfe0_clk",
> -			.parent_names = (const char *[]){
> -				"vfe0_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&vfe0_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1729,8 +1741,8 @@ static struct clk_branch camss_vfe_vfe1_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_vfe_vfe1_clk",
> -			.parent_names = (const char *[]){
> -				"vfe1_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&vfe1_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1746,8 +1758,8 @@ static struct clk_branch camss_vfe_vfe_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_vfe_vfe_ahb_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_ahb_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -1762,8 +1774,8 @@ static struct clk_branch camss_vfe_vfe_axi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_vfe_vfe_axi_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_axi_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_axi_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -1778,8 +1790,8 @@ static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "camss_vfe_vfe_ocmemnoc_clk",
> -			.parent_names = (const char *[]){
> -				"ocmemnoc_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&ocmemnoc_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1795,8 +1807,8 @@ static struct clk_branch mdss_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "mdss_ahb_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_ahb_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -1811,8 +1823,8 @@ static struct clk_branch mdss_axi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "mdss_axi_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_axi_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_axi_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1828,8 +1840,8 @@ static struct clk_branch mdss_byte0_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "mdss_byte0_clk",
> -			.parent_names = (const char *[]){
> -				"byte0_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&byte0_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1845,8 +1857,8 @@ static struct clk_branch mdss_byte1_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "mdss_byte1_clk",
> -			.parent_names = (const char *[]){
> -				"byte1_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&byte1_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1862,8 +1874,8 @@ static struct clk_branch mdss_edpaux_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "mdss_edpaux_clk",
> -			.parent_names = (const char *[]){
> -				"edpaux_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&edpaux_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1879,8 +1891,8 @@ static struct clk_branch mdss_edplink_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "mdss_edplink_clk",
> -			.parent_names = (const char *[]){
> -				"edplink_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&edplink_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1896,8 +1908,8 @@ static struct clk_branch mdss_edppixel_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "mdss_edppixel_clk",
> -			.parent_names = (const char *[]){
> -				"edppixel_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&edppixel_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1913,8 +1925,8 @@ static struct clk_branch mdss_esc0_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "mdss_esc0_clk",
> -			.parent_names = (const char *[]){
> -				"esc0_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&esc0_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1930,8 +1942,8 @@ static struct clk_branch mdss_esc1_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "mdss_esc1_clk",
> -			.parent_names = (const char *[]){
> -				"esc1_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&esc1_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1947,8 +1959,8 @@ static struct clk_branch mdss_extpclk_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "mdss_extpclk_clk",
> -			.parent_names = (const char *[]){
> -				"extpclk_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&extpclk_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1964,8 +1976,8 @@ static struct clk_branch mdss_hdmi_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "mdss_hdmi_ahb_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_ahb_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -1980,8 +1992,8 @@ static struct clk_branch mdss_hdmi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "mdss_hdmi_clk",
> -			.parent_names = (const char *[]){
> -				"hdmi_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&hdmi_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1997,8 +2009,8 @@ static struct clk_branch mdss_mdp_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "mdss_mdp_clk",
> -			.parent_names = (const char *[]){
> -				"mdp_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mdp_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -2014,8 +2026,8 @@ static struct clk_branch mdss_mdp_lut_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "mdss_mdp_lut_clk",
> -			.parent_names = (const char *[]){
> -				"mdp_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mdp_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -2031,8 +2043,8 @@ static struct clk_branch mdss_pclk0_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "mdss_pclk0_clk",
> -			.parent_names = (const char *[]){
> -				"pclk0_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&pclk0_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -2048,8 +2060,8 @@ static struct clk_branch mdss_pclk1_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "mdss_pclk1_clk",
> -			.parent_names = (const char *[]){
> -				"pclk1_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&pclk1_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -2065,8 +2077,8 @@ static struct clk_branch mdss_vsync_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "mdss_vsync_clk",
> -			.parent_names = (const char *[]){
> -				"vsync_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&vsync_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -2082,8 +2094,8 @@ static struct clk_branch mmss_misc_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "mmss_misc_ahb_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_ahb_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -2098,8 +2110,8 @@ static struct clk_branch mmss_mmssnoc_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "mmss_mmssnoc_ahb_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_ahb_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -2115,8 +2127,8 @@ static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "mmss_mmssnoc_bto_ahb_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_ahb_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -2132,8 +2144,8 @@ static struct clk_branch mmss_mmssnoc_axi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "mmss_mmssnoc_axi_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_axi_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_axi_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> @@ -2149,8 +2161,8 @@ static struct clk_branch mmss_s0_axi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "mmss_s0_axi_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_axi_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_axi_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -2166,8 +2178,8 @@ static struct clk_branch ocmemcx_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "ocmemcx_ahb_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_ahb_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -2182,8 +2194,8 @@ static struct clk_branch ocmemcx_ocmemnoc_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "ocmemcx_ocmemnoc_clk",
> -			.parent_names = (const char *[]){
> -				"ocmemnoc_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&ocmemnoc_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -2199,8 +2211,8 @@ static struct clk_branch oxili_ocmemgx_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "oxili_ocmemgx_clk",
> -			.parent_names = (const char *[]){
> -				"gfx3d_clk_src",
> +			.parent_data = (const struct clk_parent_data[]){
> +				{ .fw_name = "gfx3d_clk_src", .name = "gfx3d_clk_src" },
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -2216,8 +2228,8 @@ static struct clk_branch ocmemnoc_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "ocmemnoc_clk",
> -			.parent_names = (const char *[]){
> -				"ocmemnoc_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&ocmemnoc_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -2233,8 +2245,8 @@ static struct clk_branch oxili_gfx3d_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "oxili_gfx3d_clk",
> -			.parent_names = (const char *[]){
> -				"gfx3d_clk_src",
> +			.parent_data = (const struct clk_parent_data[]){
> +				{ .fw_name = "gfx3d_clk_src", .name = "gfx3d_clk_src" },
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -2250,8 +2262,8 @@ static struct clk_branch oxilicx_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "oxilicx_ahb_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_ahb_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -2266,8 +2278,8 @@ static struct clk_branch oxilicx_axi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "oxilicx_axi_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_axi_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_axi_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -2282,8 +2294,8 @@ static struct clk_branch venus0_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "venus0_ahb_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_ahb_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -2298,8 +2310,8 @@ static struct clk_branch venus0_axi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "venus0_axi_clk",
> -			.parent_names = (const char *[]){
> -				"mmss_axi_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&mmss_axi_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -2314,8 +2326,8 @@ static struct clk_branch venus0_ocmemnoc_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "venus0_ocmemnoc_clk",
> -			.parent_names = (const char *[]){
> -				"ocmemnoc_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&ocmemnoc_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -2331,8 +2343,8 @@ static struct clk_branch venus0_vcodec0_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "venus0_vcodec0_clk",
> -			.parent_names = (const char *[]){
> -				"vcodec0_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&vcodec0_clk_src.clkr.hw
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,

Re: [PATCH v3 03/11] clk: qcom: gcc-msm8974: use ARRAY_SIZE instead of specifying num_parents

[Konrad Dybcio]

On 30.10.2022 16:55, Dmitry Baryshkov wrote:
> Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
> adding/removing entries to/from parent_data easy and errorproof.
> 
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  drivers/clk/qcom/gcc-msm8974.c | 110 ++++++++++++++++-----------------
>  1 file changed, 55 insertions(+), 55 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
> index bf305fa9e522..b847ce852ef8 100644
> --- a/drivers/clk/qcom/gcc-msm8974.c
> +++ b/drivers/clk/qcom/gcc-msm8974.c
> @@ -88,7 +88,7 @@ static struct clk_rcg2 config_noc_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "config_noc_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -100,7 +100,7 @@ static struct clk_rcg2 periph_noc_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "periph_noc_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -112,7 +112,7 @@ static struct clk_rcg2 system_noc_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "system_noc_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -185,7 +185,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "usb30_master_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -205,7 +205,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup1_i2c_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -230,7 +230,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup1_spi_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -243,7 +243,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup2_i2c_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -257,7 +257,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup2_spi_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -270,7 +270,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup3_i2c_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -284,7 +284,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup3_spi_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -297,7 +297,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup4_i2c_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -311,7 +311,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup4_spi_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -324,7 +324,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup5_i2c_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -338,7 +338,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup5_spi_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -351,7 +351,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup6_i2c_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -365,7 +365,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup6_spi_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -398,7 +398,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_uart1_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -412,7 +412,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_uart2_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -426,7 +426,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_uart3_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -440,7 +440,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_uart4_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -454,7 +454,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_uart5_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -468,7 +468,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_uart6_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -481,7 +481,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup1_i2c_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -495,7 +495,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup1_spi_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -508,7 +508,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup2_i2c_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -522,7 +522,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup2_spi_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -535,7 +535,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup3_i2c_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -549,7 +549,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup3_spi_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -562,7 +562,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup4_i2c_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -576,7 +576,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup4_spi_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -589,7 +589,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup5_i2c_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -603,7 +603,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup5_spi_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -616,7 +616,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup6_i2c_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -630,7 +630,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup6_spi_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -644,7 +644,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_uart1_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -658,7 +658,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_uart2_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -672,7 +672,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_uart3_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -686,7 +686,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_uart4_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -700,7 +700,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_uart5_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -714,7 +714,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_uart6_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -741,7 +741,7 @@ static struct clk_rcg2 ce1_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "ce1_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -762,7 +762,7 @@ static struct clk_rcg2 ce2_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "ce2_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -794,7 +794,7 @@ static struct clk_rcg2 gp1_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "gp1_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -808,7 +808,7 @@ static struct clk_rcg2 gp2_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "gp2_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -822,7 +822,7 @@ static struct clk_rcg2 gp3_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "gp3_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -840,7 +840,7 @@ static struct clk_rcg2 pdm2_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "pdm2_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -872,7 +872,7 @@ static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_pro[] = {
>  static struct clk_init_data sdcc1_apps_clk_src_init = {
>  	.name = "sdcc1_apps_clk_src",
>  	.parent_names = gcc_xo_gpll0,
> -	.num_parents = 2,
> +	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  	.ops = &clk_rcg2_floor_ops,
>  };
>  
> @@ -894,7 +894,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "sdcc2_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_floor_ops,
>  	},
>  };
> @@ -908,7 +908,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "sdcc3_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_floor_ops,
>  	},
>  };
> @@ -922,7 +922,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "sdcc4_apps_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_floor_ops,
>  	},
>  };
> @@ -941,7 +941,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "tsif_ref_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -959,7 +959,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "usb30_mock_utmi_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -978,7 +978,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "usb_hs_system_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -1022,7 +1022,7 @@ static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "usb_hsic_io_cal_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 1,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
It differs! I wonder if that's gonna fix anything :D

Anyway,

Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>

Konrad
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -1041,7 +1041,7 @@ static struct clk_rcg2 usb_hsic_system_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "usb_hsic_system_clk_src",
>  		.parent_names = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };

Re: [PATCH v3 04/11] clk: qcom: gcc-msm8974: move clock parent tables down

[Konrad Dybcio]

On 30.10.2022 16:55, Dmitry Baryshkov wrote:
> Rearrage clock parent tables and PLL declarations (pull parents down
> and gpll4 up), so that we can use pll hw clock fields in the next
> commit.
> 
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>

Konrad
>  drivers/clk/qcom/gcc-msm8974.c | 98 +++++++++++++++++-----------------
>  1 file changed, 49 insertions(+), 49 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
> index b847ce852ef8..77f3497265a0 100644
> --- a/drivers/clk/qcom/gcc-msm8974.c
> +++ b/drivers/clk/qcom/gcc-msm8974.c
> @@ -32,28 +32,6 @@ enum {
>  	P_GPLL4,
>  };
>  
> -static const struct parent_map gcc_xo_gpll0_map[] = {
> -	{ P_XO, 0 },
> -	{ P_GPLL0, 1 }
> -};
> -
> -static const char * const gcc_xo_gpll0[] = {
> -	"xo",
> -	"gpll0_vote",
> -};
> -
> -static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
> -	{ P_XO, 0 },
> -	{ P_GPLL0, 1 },
> -	{ P_GPLL4, 5 }
> -};
> -
> -static const char * const gcc_xo_gpll0_gpll4[] = {
> -	"xo",
> -	"gpll0_vote",
> -	"gpll4_vote",
> -};
> -
>  static struct clk_pll gpll0 = {
>  	.l_reg = 0x0004,
>  	.m_reg = 0x0008,
> @@ -81,6 +59,55 @@ static struct clk_regmap gpll0_vote = {
>  	},
>  };
>  
> +static struct clk_pll gpll4 = {
> +	.l_reg = 0x1dc4,
> +	.m_reg = 0x1dc8,
> +	.n_reg = 0x1dcc,
> +	.config_reg = 0x1dd4,
> +	.mode_reg = 0x1dc0,
> +	.status_reg = 0x1ddc,
> +	.status_bit = 17,
> +	.clkr.hw.init = &(struct clk_init_data){
> +		.name = "gpll4",
> +		.parent_names = (const char *[]){ "xo" },
> +		.num_parents = 1,
> +		.ops = &clk_pll_ops,
> +	},
> +};
> +
> +static struct clk_regmap gpll4_vote = {
> +	.enable_reg = 0x1480,
> +	.enable_mask = BIT(4),
> +	.hw.init = &(struct clk_init_data){
> +		.name = "gpll4_vote",
> +		.parent_names = (const char *[]){ "gpll4" },
> +		.num_parents = 1,
> +		.ops = &clk_pll_vote_ops,
> +	},
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_map[] = {
> +	{ P_XO, 0 },
> +	{ P_GPLL0, 1 }
> +};
> +
> +static const char * const gcc_xo_gpll0[] = {
> +	"xo",
> +	"gpll0_vote",
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
> +	{ P_XO, 0 },
> +	{ P_GPLL0, 1 },
> +	{ P_GPLL4, 5 }
> +};
> +
> +static const char * const gcc_xo_gpll0_gpll4[] = {
> +	"xo",
> +	"gpll0_vote",
> +	"gpll4_vote",
> +};
> +
>  static struct clk_rcg2 config_noc_clk_src = {
>  	.cmd_rcgr = 0x0150,
>  	.hid_width = 5,
> @@ -144,33 +171,6 @@ static struct clk_regmap gpll1_vote = {
>  	},
>  };
>  
> -static struct clk_pll gpll4 = {
> -	.l_reg = 0x1dc4,
> -	.m_reg = 0x1dc8,
> -	.n_reg = 0x1dcc,
> -	.config_reg = 0x1dd4,
> -	.mode_reg = 0x1dc0,
> -	.status_reg = 0x1ddc,
> -	.status_bit = 17,
> -	.clkr.hw.init = &(struct clk_init_data){
> -		.name = "gpll4",
> -		.parent_names = (const char *[]){ "xo" },
> -		.num_parents = 1,
> -		.ops = &clk_pll_ops,
> -	},
> -};
> -
> -static struct clk_regmap gpll4_vote = {
> -	.enable_reg = 0x1480,
> -	.enable_mask = BIT(4),
> -	.hw.init = &(struct clk_init_data){
> -		.name = "gpll4_vote",
> -		.parent_names = (const char *[]){ "gpll4" },
> -		.num_parents = 1,
> -		.ops = &clk_pll_vote_ops,
> -	},
> -};
> -
>  static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = {
>  	F(125000000, P_GPLL0, 1, 5, 24),
>  	{ }

Re: [PATCH v3 06/11] clk: qcom: mmcc-msm8974: use ARRAY_SIZE instead of specifying num_parents

[Konrad Dybcio]

On 30.10.2022 16:55, Dmitry Baryshkov wrote:
> Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
> adding/removing entries to/from parent_data easy and errorproof.
> 
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>

Konrad
>  drivers/clk/qcom/mmcc-msm8974.c | 74 ++++++++++++++++-----------------
>  1 file changed, 37 insertions(+), 37 deletions(-)
> 
> diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
> index f74662925a58..9008df2305df 100644
> --- a/drivers/clk/qcom/mmcc-msm8974.c
> +++ b/drivers/clk/qcom/mmcc-msm8974.c
> @@ -252,7 +252,7 @@ static struct clk_rcg2 mmss_ahb_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "mmss_ahb_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -289,7 +289,7 @@ static struct clk_rcg2 mmss_axi_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "mmss_axi_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -313,7 +313,7 @@ static struct clk_rcg2 ocmemnoc_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "ocmemnoc_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -332,7 +332,7 @@ static struct clk_rcg2 csi0_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "csi0_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -345,7 +345,7 @@ static struct clk_rcg2 csi1_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "csi1_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -358,7 +358,7 @@ static struct clk_rcg2 csi2_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "csi2_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -371,7 +371,7 @@ static struct clk_rcg2 csi3_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "csi3_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -418,7 +418,7 @@ static struct clk_rcg2 vfe0_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "vfe0_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -431,7 +431,7 @@ static struct clk_rcg2 vfe1_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "vfe1_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -472,7 +472,7 @@ static struct clk_rcg2 mdp_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "mdp_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
> -		.num_parents = 6,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -495,7 +495,7 @@ static struct clk_rcg2 jpeg0_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "jpeg0_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -508,7 +508,7 @@ static struct clk_rcg2 jpeg1_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "jpeg1_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -521,7 +521,7 @@ static struct clk_rcg2 jpeg2_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "jpeg2_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -534,7 +534,7 @@ static struct clk_rcg2 pclk0_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "pclk0_clk_src",
>  		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> -		.num_parents = 6,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
>  		.ops = &clk_pixel_ops,
>  		.flags = CLK_SET_RATE_PARENT,
>  	},
> @@ -548,7 +548,7 @@ static struct clk_rcg2 pclk1_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "pclk1_clk_src",
>  		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> -		.num_parents = 6,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
>  		.ops = &clk_pixel_ops,
>  		.flags = CLK_SET_RATE_PARENT,
>  	},
> @@ -581,7 +581,7 @@ static struct clk_rcg2 vcodec0_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "vcodec0_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_1_3_gpll0,
> -		.num_parents = 5,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -599,7 +599,7 @@ static struct clk_rcg2 cci_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cci_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -623,7 +623,7 @@ static struct clk_rcg2 camss_gp0_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "camss_gp0_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_1_gpll1_0,
> -		.num_parents = 5,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -637,7 +637,7 @@ static struct clk_rcg2 camss_gp1_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "camss_gp1_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_1_gpll1_0,
> -		.num_parents = 5,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -672,7 +672,7 @@ static struct clk_rcg2 mclk0_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "mclk0_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -685,7 +685,7 @@ static struct clk_rcg2 mclk1_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "mclk1_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -698,7 +698,7 @@ static struct clk_rcg2 mclk2_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "mclk2_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -711,7 +711,7 @@ static struct clk_rcg2 mclk3_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "mclk3_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -730,7 +730,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "csi0phytimer_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -743,7 +743,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "csi1phytimer_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -756,7 +756,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "csi2phytimer_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -787,7 +787,7 @@ static struct clk_rcg2 cpp_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cpp_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -805,7 +805,7 @@ static struct clk_rcg2 byte0_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "byte0_clk_src",
>  		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> -		.num_parents = 6,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
>  		.ops = &clk_byte2_ops,
>  		.flags = CLK_SET_RATE_PARENT,
>  	},
> @@ -819,7 +819,7 @@ static struct clk_rcg2 byte1_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "byte1_clk_src",
>  		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> -		.num_parents = 6,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
>  		.ops = &clk_byte2_ops,
>  		.flags = CLK_SET_RATE_PARENT,
>  	},
> @@ -838,7 +838,7 @@ static struct clk_rcg2 edpaux_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "edpaux_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -857,7 +857,7 @@ static struct clk_rcg2 edplink_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "edplink_clk_src",
>  		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> -		.num_parents = 6,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
>  		.ops = &clk_rcg2_ops,
>  		.flags = CLK_SET_RATE_PARENT,
>  	},
> @@ -877,7 +877,7 @@ static struct clk_rcg2 edppixel_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "edppixel_clk_src",
>  		.parent_names = mmcc_xo_dsi_hdmi_edp,
> -		.num_parents = 6,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp),
>  		.ops = &clk_edp_pixel_ops,
>  	},
>  };
> @@ -895,7 +895,7 @@ static struct clk_rcg2 esc0_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "esc0_clk_src",
>  		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> -		.num_parents = 6,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -908,7 +908,7 @@ static struct clk_rcg2 esc1_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "esc1_clk_src",
>  		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> -		.num_parents = 6,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -926,7 +926,7 @@ static struct clk_rcg2 extpclk_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "extpclk_clk_src",
>  		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> -		.num_parents = 6,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
>  		.ops = &clk_byte_ops,
>  		.flags = CLK_SET_RATE_PARENT,
>  	},
> @@ -945,7 +945,7 @@ static struct clk_rcg2 hdmi_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "hdmi_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -963,7 +963,7 @@ static struct clk_rcg2 vsync_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "vsync_clk_src",
>  		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };

Re: [PATCH v3 07/11] clk: qcom: mmcc-msm8974: move clock parent tables down

[Konrad Dybcio]

On 30.10.2022 16:55, Dmitry Baryshkov wrote:
> Move clock parent tables down, after the PLL declarataions, so that we
> can use pll hw clock fields in the next commit.
> 
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>

Konrad
>  drivers/clk/qcom/mmcc-msm8974.c | 170 ++++++++++++++++----------------
>  1 file changed, 85 insertions(+), 85 deletions(-)
> 
> diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
> index 9008df2305df..57f1a351c8f6 100644
> --- a/drivers/clk/qcom/mmcc-msm8974.c
> +++ b/drivers/clk/qcom/mmcc-msm8974.c
> @@ -42,6 +42,91 @@ enum {
>  	P_DSI1PLL_BYTE,
>  };
>  
> +static struct clk_pll mmpll0 = {
> +	.l_reg = 0x0004,
> +	.m_reg = 0x0008,
> +	.n_reg = 0x000c,
> +	.config_reg = 0x0014,
> +	.mode_reg = 0x0000,
> +	.status_reg = 0x001c,
> +	.status_bit = 17,
> +        .clkr.hw.init = &(struct clk_init_data){
> +                .name = "mmpll0",
> +                .parent_names = (const char *[]){ "xo" },
> +                .num_parents = 1,
> +                .ops = &clk_pll_ops,
> +        },
> +};
> +
> +static struct clk_regmap mmpll0_vote = {
> +	.enable_reg = 0x0100,
> +	.enable_mask = BIT(0),
> +	.hw.init = &(struct clk_init_data){
> +		.name = "mmpll0_vote",
> +		.parent_names = (const char *[]){ "mmpll0" },
> +		.num_parents = 1,
> +		.ops = &clk_pll_vote_ops,
> +	},
> +};
> +
> +static struct clk_pll mmpll1 = {
> +	.l_reg = 0x0044,
> +	.m_reg = 0x0048,
> +	.n_reg = 0x004c,
> +	.config_reg = 0x0050,
> +	.mode_reg = 0x0040,
> +	.status_reg = 0x005c,
> +	.status_bit = 17,
> +        .clkr.hw.init = &(struct clk_init_data){
> +                .name = "mmpll1",
> +                .parent_names = (const char *[]){ "xo" },
> +                .num_parents = 1,
> +                .ops = &clk_pll_ops,
> +        },
> +};
> +
> +static struct clk_regmap mmpll1_vote = {
> +	.enable_reg = 0x0100,
> +	.enable_mask = BIT(1),
> +	.hw.init = &(struct clk_init_data){
> +		.name = "mmpll1_vote",
> +		.parent_names = (const char *[]){ "mmpll1" },
> +		.num_parents = 1,
> +		.ops = &clk_pll_vote_ops,
> +	},
> +};
> +
> +static struct clk_pll mmpll2 = {
> +	.l_reg = 0x4104,
> +	.m_reg = 0x4108,
> +	.n_reg = 0x410c,
> +	.config_reg = 0x4110,
> +	.mode_reg = 0x4100,
> +	.status_reg = 0x411c,
> +        .clkr.hw.init = &(struct clk_init_data){
> +                .name = "mmpll2",
> +                .parent_names = (const char *[]){ "xo" },
> +                .num_parents = 1,
> +                .ops = &clk_pll_ops,
> +        },
> +};
> +
> +static struct clk_pll mmpll3 = {
> +	.l_reg = 0x0084,
> +	.m_reg = 0x0088,
> +	.n_reg = 0x008c,
> +	.config_reg = 0x0090,
> +	.mode_reg = 0x0080,
> +	.status_reg = 0x009c,
> +	.status_bit = 17,
> +        .clkr.hw.init = &(struct clk_init_data){
> +                .name = "mmpll3",
> +                .parent_names = (const char *[]){ "xo" },
> +                .num_parents = 1,
> +                .ops = &clk_pll_ops,
> +        },
> +};
> +
>  static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
>  	{ P_XO, 0 },
>  	{ P_MMPLL0, 1 },
> @@ -160,91 +245,6 @@ static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
>  	"dsi1pllbyte",
>  };
>  
> -static struct clk_pll mmpll0 = {
> -	.l_reg = 0x0004,
> -	.m_reg = 0x0008,
> -	.n_reg = 0x000c,
> -	.config_reg = 0x0014,
> -	.mode_reg = 0x0000,
> -	.status_reg = 0x001c,
> -	.status_bit = 17,
> -        .clkr.hw.init = &(struct clk_init_data){
> -                .name = "mmpll0",
> -                .parent_names = (const char *[]){ "xo" },
> -                .num_parents = 1,
> -                .ops = &clk_pll_ops,
> -        },
> -};
> -
> -static struct clk_regmap mmpll0_vote = {
> -	.enable_reg = 0x0100,
> -	.enable_mask = BIT(0),
> -	.hw.init = &(struct clk_init_data){
> -		.name = "mmpll0_vote",
> -		.parent_names = (const char *[]){ "mmpll0" },
> -		.num_parents = 1,
> -		.ops = &clk_pll_vote_ops,
> -	},
> -};
> -
> -static struct clk_pll mmpll1 = {
> -	.l_reg = 0x0044,
> -	.m_reg = 0x0048,
> -	.n_reg = 0x004c,
> -	.config_reg = 0x0050,
> -	.mode_reg = 0x0040,
> -	.status_reg = 0x005c,
> -	.status_bit = 17,
> -        .clkr.hw.init = &(struct clk_init_data){
> -                .name = "mmpll1",
> -                .parent_names = (const char *[]){ "xo" },
> -                .num_parents = 1,
> -                .ops = &clk_pll_ops,
> -        },
> -};
> -
> -static struct clk_regmap mmpll1_vote = {
> -	.enable_reg = 0x0100,
> -	.enable_mask = BIT(1),
> -	.hw.init = &(struct clk_init_data){
> -		.name = "mmpll1_vote",
> -		.parent_names = (const char *[]){ "mmpll1" },
> -		.num_parents = 1,
> -		.ops = &clk_pll_vote_ops,
> -	},
> -};
> -
> -static struct clk_pll mmpll2 = {
> -	.l_reg = 0x4104,
> -	.m_reg = 0x4108,
> -	.n_reg = 0x410c,
> -	.config_reg = 0x4110,
> -	.mode_reg = 0x4100,
> -	.status_reg = 0x411c,
> -        .clkr.hw.init = &(struct clk_init_data){
> -                .name = "mmpll2",
> -                .parent_names = (const char *[]){ "xo" },
> -                .num_parents = 1,
> -                .ops = &clk_pll_ops,
> -        },
> -};
> -
> -static struct clk_pll mmpll3 = {
> -	.l_reg = 0x0084,
> -	.m_reg = 0x0088,
> -	.n_reg = 0x008c,
> -	.config_reg = 0x0090,
> -	.mode_reg = 0x0080,
> -	.status_reg = 0x009c,
> -	.status_bit = 17,
> -        .clkr.hw.init = &(struct clk_init_data){
> -                .name = "mmpll3",
> -                .parent_names = (const char *[]){ "xo" },
> -                .num_parents = 1,
> -                .ops = &clk_pll_ops,
> -        },
> -};
> -
>  static struct clk_rcg2 mmss_ahb_clk_src = {
>  	.cmd_rcgr = 0x5000,
>  	.hid_width = 5,

Re: [PATCH v3 01/11] dt-bindings: clock: split qcom,gcc-msm8974,-msm8226 to the separate file

[Rob Herring]

On Sun, 30 Oct 2022 18:55:10 +0300, Dmitry Baryshkov wrote:
> Move schema for the GCC on MSM8974 and MSM8226 platforms to a separate
> file to be able to define device-specific clock properties.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  .../bindings/clock/qcom,gcc-msm8974.yaml      | 64 +++++++++++++++++++
>  .../bindings/clock/qcom,gcc-other.yaml        |  9 +--
>  2 files changed, 65 insertions(+), 8 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH v3 01/11] dt-bindings: clock: split qcom,gcc-msm8974,-msm8226 to the separate file

[Krzysztof Kozlowski]

On 30/10/2022 11:55, Dmitry Baryshkov wrote:
> Move schema for the GCC on MSM8974 and MSM8226 platforms to a separate
> file to be able to define device-specific clock properties.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  .../bindings/clock/qcom,gcc-msm8974.yaml      | 64 +++++++++++++++++++
>  .../bindings/clock/qcom,gcc-other.yaml        |  9 +--
>  2 files changed, 65 insertions(+), 8 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml
> new file mode 100644
> index 000000000000..a92a60f8c1af
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml
> @@ -0,0 +1,64 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8974.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm MSM8974 (including Pro) and MSM8226 Global Clock & Reset
> +  Controller
> +
> +maintainers:
> +  - Stephen Boyd <sboyd@kernel.org>
> +  - Taniya Das <quic_tdas@quicinc.com>
> +
> +description: |
> +  Qualcomm global clock control module which supports the clocks, resets and
> +  power domains on MSM8974 (all variants) and MSM8226.

Please incorporate the same changes I did here:

https://lore.kernel.org/linux-devicetree/20221102163153.55460-2-krzysztof.kozlowski@linaro.org/

> +

Rest looks good.

Best regards,
Krzysztof

Re: [PATCH v3 08/11] clk: qcom: mmcc-msm8974: use parent_hws/_data instead of parent_names

[Bjorn Andersson]

On Mon, Oct 31, 2022 at 10:09:23PM +0100, Konrad Dybcio wrote:
> 
> 
> On 30.10.2022 16:55, Dmitry Baryshkov wrote:
> > Convert the clock driver to specify parent data rather than parent
> > names, to actually bind using 'clock-names' specified in the DTS rather
> > than global clock names. Use parent_hws where possible to refer parent
> > clocks directly, skipping the lookup.
> > 
> > Note, the system names for xo clocks were changed from "xo" to
> > "xo_board" to follow the example of other platforms.
> I think it should be reverse - look for "xo" and pass "xo_board" through DT.
> 

We have a clock with the global name "xo_board", so .name = "xo_board"
should work just fine. Relying on the .name = "xo" would make us use the
board-clock registered in gcc_msm8974_probe(), but with this we should
be able to drop that.

We also don't have any clocks in the DT node, so picking "xo" for that
would work fine as well.


Please let me know if I'm missing something here.

Regards,
Bjorn

> Konrad
> > 
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> >  drivers/clk/qcom/mmcc-msm8974.c | 516 ++++++++++++++++----------------
> >  1 file changed, 264 insertions(+), 252 deletions(-)
> > 
> > diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
> > index 57f1a351c8f6..4273fce9a4a4 100644
> > --- a/drivers/clk/qcom/mmcc-msm8974.c
> > +++ b/drivers/clk/qcom/mmcc-msm8974.c
> > @@ -52,7 +52,9 @@ static struct clk_pll mmpll0 = {
> >  	.status_bit = 17,
> >          .clkr.hw.init = &(struct clk_init_data){
> >                  .name = "mmpll0",
> > -                .parent_names = (const char *[]){ "xo" },
> > +                .parent_data = (const struct clk_parent_data[]){
> > +			{ .fw_name = "xo", .name = "xo_board" },
> > +		},
> >                  .num_parents = 1,
> >                  .ops = &clk_pll_ops,
> >          },
> > @@ -63,7 +65,9 @@ static struct clk_regmap mmpll0_vote = {
> >  	.enable_mask = BIT(0),
> >  	.hw.init = &(struct clk_init_data){
> >  		.name = "mmpll0_vote",
> > -		.parent_names = (const char *[]){ "mmpll0" },
> > +		.parent_hws = (const struct clk_hw*[]){
> > +			&mmpll0.clkr.hw
> > +		},
> >  		.num_parents = 1,
> >  		.ops = &clk_pll_vote_ops,
> >  	},
> > @@ -79,7 +83,9 @@ static struct clk_pll mmpll1 = {
> >  	.status_bit = 17,
> >          .clkr.hw.init = &(struct clk_init_data){
> >                  .name = "mmpll1",
> > -                .parent_names = (const char *[]){ "xo" },
> > +                .parent_data = (const struct clk_parent_data[]){
> > +			{ .fw_name = "xo", .name = "xo_board" },
> > +		},
> >                  .num_parents = 1,
> >                  .ops = &clk_pll_ops,
> >          },
> > @@ -90,7 +96,9 @@ static struct clk_regmap mmpll1_vote = {
> >  	.enable_mask = BIT(1),
> >  	.hw.init = &(struct clk_init_data){
> >  		.name = "mmpll1_vote",
> > -		.parent_names = (const char *[]){ "mmpll1" },
> > +		.parent_hws = (const struct clk_hw*[]){
> > +			&mmpll1.clkr.hw
> > +		},
> >  		.num_parents = 1,
> >  		.ops = &clk_pll_vote_ops,
> >  	},
> > @@ -105,7 +113,9 @@ static struct clk_pll mmpll2 = {
> >  	.status_reg = 0x411c,
> >          .clkr.hw.init = &(struct clk_init_data){
> >                  .name = "mmpll2",
> > -                .parent_names = (const char *[]){ "xo" },
> > +                .parent_data = (const struct clk_parent_data[]){
> > +			{ .fw_name = "xo", .name = "xo_board" },
> > +		},
> >                  .num_parents = 1,
> >                  .ops = &clk_pll_ops,
> >          },
> > @@ -121,7 +131,9 @@ static struct clk_pll mmpll3 = {
> >  	.status_bit = 17,
> >          .clkr.hw.init = &(struct clk_init_data){
> >                  .name = "mmpll3",
> > -                .parent_names = (const char *[]){ "xo" },
> > +                .parent_data = (const struct clk_parent_data[]){
> > +			{ .fw_name = "xo", .name = "xo_board" },
> > +		},
> >                  .num_parents = 1,
> >                  .ops = &clk_pll_ops,
> >          },
> > @@ -134,11 +146,11 @@ static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
> >  	{ P_GPLL0, 5 }
> >  };
> >  
> > -static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
> > -	"xo",
> > -	"mmpll0_vote",
> > -	"mmpll1_vote",
> > -	"mmss_gpll0_vote",
> > +static const struct clk_parent_data mmcc_xo_mmpll0_mmpll1_gpll0[] = {
> > +	{ .fw_name = "xo", .name = "xo_board" },
> > +	{ .hw = &mmpll0_vote.hw },
> > +	{ .hw = &mmpll1_vote.hw },
> > +	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
> >  };
> >  
> >  static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
> > @@ -150,13 +162,13 @@ static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
> >  	{ P_DSI1PLL, 3 }
> >  };
> >  
> > -static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
> > -	"xo",
> > -	"mmpll0_vote",
> > -	"hdmipll",
> > -	"mmss_gpll0_vote",
> > -	"dsi0pll",
> > -	"dsi1pll",
> > +static const struct clk_parent_data mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
> > +	{ .fw_name = "xo", .name = "xo_board" },
> > +	{ .hw = &mmpll0_vote.hw },
> > +	{ .fw_name = "hdmipll", .name = "hdmipll" },
> > +	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
> > +	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
> > +	{ .fw_name = "dsi1pll", .name = "dsi1pll" },
> >  };
> >  
> >  static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
> > @@ -167,12 +179,12 @@ static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
> >  	{ P_MMPLL3, 3 }
> >  };
> >  
> > -static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
> > -	"xo",
> > -	"mmpll0_vote",
> > -	"mmpll1_vote",
> > -	"mmss_gpll0_vote",
> > -	"mmpll3",
> > +static const struct clk_parent_data mmcc_xo_mmpll0_1_3_gpll0[] = {
> > +	{ .fw_name = "xo", .name = "xo_board" },
> > +	{ .hw = &mmpll0_vote.hw },
> > +	{ .hw = &mmpll1_vote.hw },
> > +	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
> > +	{ .hw = &mmpll3.clkr.hw },
> >  };
> >  
> >  static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
> > @@ -183,12 +195,12 @@ static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
> >  	{ P_GPLL1, 4 }
> >  };
> >  
> > -static const char * const mmcc_xo_mmpll0_1_gpll1_0[] = {
> > -	"xo",
> > -	"mmpll0_vote",
> > -	"mmpll1_vote",
> > -	"mmss_gpll0_vote",
> > -	"gpll1_vote",
> > +static const struct clk_parent_data mmcc_xo_mmpll0_1_gpll1_0[] = {
> > +	{ .fw_name = "xo", .name = "xo_board" },
> > +	{ .hw = &mmpll0_vote.hw },
> > +	{ .hw = &mmpll1_vote.hw },
> > +	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
> > +	{ .fw_name = "gpll1_vote", .name = "gpll1_vote" },
> >  };
> >  
> >  static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
> > @@ -200,13 +212,13 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
> >  	{ P_DSI1PLL, 2 }
> >  };
> >  
> > -static const char * const mmcc_xo_dsi_hdmi_edp[] = {
> > -	"xo",
> > -	"edp_link_clk",
> > -	"hdmipll",
> > -	"edp_vco_div",
> > -	"dsi0pll",
> > -	"dsi1pll",
> > +static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp[] = {
> > +	{ .fw_name = "xo", .name = "xo_board" },
> > +	{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
> > +	{ .fw_name = "hdmipll", .name = "hdmipll" },
> > +	{ .fw_name = "edp_vco_div", .name = "edp_vco_div" },
> > +	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
> > +	{ .fw_name = "dsi1pll", .name = "dsi1pll" },
> >  };
> >  
> >  static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
> > @@ -218,13 +230,13 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
> >  	{ P_DSI1PLL, 2 }
> >  };
> >  
> > -static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
> > -	"xo",
> > -	"edp_link_clk",
> > -	"hdmipll",
> > -	"gpll0_vote",
> > -	"dsi0pll",
> > -	"dsi1pll",
> > +static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp_gpll0[] = {
> > +	{ .fw_name = "xo", .name = "xo_board" },
> > +	{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
> > +	{ .fw_name = "hdmipll", .name = "hdmipll" },
> > +	{ .fw_name = "gpll0_vote", .name = "gpll0_vote" },
> > +	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
> > +	{ .fw_name = "dsi1pll", .name = "dsi1pll" },
> >  };
> >  
> >  static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
> > @@ -236,13 +248,13 @@ static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
> >  	{ P_DSI1PLL_BYTE, 2 }
> >  };
> >  
> > -static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
> > -	"xo",
> > -	"edp_link_clk",
> > -	"hdmipll",
> > -	"gpll0_vote",
> > -	"dsi0pllbyte",
> > -	"dsi1pllbyte",
> > +static const struct clk_parent_data mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
> > +	{ .fw_name = "xo", .name = "xo_board" },
> > +	{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
> > +	{ .fw_name = "hdmipll", .name = "hdmipll" },
> > +	{ .fw_name = "gpll0_vote", .name = "gpll0_vote" },
> > +	{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
> > +	{ .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" },
> >  };
> >  
> >  static struct clk_rcg2 mmss_ahb_clk_src = {
> > @@ -251,7 +263,7 @@ static struct clk_rcg2 mmss_ahb_clk_src = {
> >  	.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "mmss_ahb_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -288,7 +300,7 @@ static struct clk_rcg2 mmss_axi_clk_src = {
> >  	.freq_tbl = ftbl_mmss_axi_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "mmss_axi_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -312,7 +324,7 @@ static struct clk_rcg2 ocmemnoc_clk_src = {
> >  	.freq_tbl = ftbl_ocmemnoc_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "ocmemnoc_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -331,7 +343,7 @@ static struct clk_rcg2 csi0_clk_src = {
> >  	.freq_tbl = ftbl_camss_csi0_3_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "csi0_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -344,7 +356,7 @@ static struct clk_rcg2 csi1_clk_src = {
> >  	.freq_tbl = ftbl_camss_csi0_3_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "csi1_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -357,7 +369,7 @@ static struct clk_rcg2 csi2_clk_src = {
> >  	.freq_tbl = ftbl_camss_csi0_3_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "csi2_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -370,7 +382,7 @@ static struct clk_rcg2 csi3_clk_src = {
> >  	.freq_tbl = ftbl_camss_csi0_3_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "csi3_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -417,7 +429,7 @@ static struct clk_rcg2 vfe0_clk_src = {
> >  	.freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "vfe0_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -430,7 +442,7 @@ static struct clk_rcg2 vfe1_clk_src = {
> >  	.freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "vfe1_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -471,7 +483,7 @@ static struct clk_rcg2 mdp_clk_src = {
> >  	.freq_tbl = ftbl_mdss_mdp_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "mdp_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -494,7 +506,7 @@ static struct clk_rcg2 jpeg0_clk_src = {
> >  	.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "jpeg0_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -507,7 +519,7 @@ static struct clk_rcg2 jpeg1_clk_src = {
> >  	.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "jpeg1_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -520,7 +532,7 @@ static struct clk_rcg2 jpeg2_clk_src = {
> >  	.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "jpeg2_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -533,7 +545,7 @@ static struct clk_rcg2 pclk0_clk_src = {
> >  	.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "pclk0_clk_src",
> > -		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> > +		.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
> >  		.ops = &clk_pixel_ops,
> >  		.flags = CLK_SET_RATE_PARENT,
> > @@ -547,7 +559,7 @@ static struct clk_rcg2 pclk1_clk_src = {
> >  	.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "pclk1_clk_src",
> > -		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> > +		.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
> >  		.ops = &clk_pixel_ops,
> >  		.flags = CLK_SET_RATE_PARENT,
> > @@ -580,7 +592,7 @@ static struct clk_rcg2 vcodec0_clk_src = {
> >  	.freq_tbl = ftbl_venus0_vcodec0_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "vcodec0_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_1_3_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_1_3_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -598,7 +610,7 @@ static struct clk_rcg2 cci_clk_src = {
> >  	.freq_tbl = ftbl_camss_cci_cci_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "cci_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -622,7 +634,7 @@ static struct clk_rcg2 camss_gp0_clk_src = {
> >  	.freq_tbl = ftbl_camss_gp0_1_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "camss_gp0_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_1_gpll1_0,
> > +		.parent_data = mmcc_xo_mmpll0_1_gpll1_0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -636,7 +648,7 @@ static struct clk_rcg2 camss_gp1_clk_src = {
> >  	.freq_tbl = ftbl_camss_gp0_1_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "camss_gp1_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_1_gpll1_0,
> > +		.parent_data = mmcc_xo_mmpll0_1_gpll1_0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -671,7 +683,7 @@ static struct clk_rcg2 mclk0_clk_src = {
> >  	.freq_tbl = ftbl_camss_mclk0_3_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "mclk0_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -684,7 +696,7 @@ static struct clk_rcg2 mclk1_clk_src = {
> >  	.freq_tbl = ftbl_camss_mclk0_3_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "mclk1_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -697,7 +709,7 @@ static struct clk_rcg2 mclk2_clk_src = {
> >  	.freq_tbl = ftbl_camss_mclk0_3_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "mclk2_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -710,7 +722,7 @@ static struct clk_rcg2 mclk3_clk_src = {
> >  	.freq_tbl = ftbl_camss_mclk0_3_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "mclk3_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -729,7 +741,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = {
> >  	.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "csi0phytimer_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -742,7 +754,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = {
> >  	.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "csi1phytimer_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -755,7 +767,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = {
> >  	.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "csi2phytimer_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -786,7 +798,7 @@ static struct clk_rcg2 cpp_clk_src = {
> >  	.freq_tbl = ftbl_camss_vfe_cpp_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "cpp_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -804,7 +816,7 @@ static struct clk_rcg2 byte0_clk_src = {
> >  	.freq_tbl = byte_freq_tbl,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "byte0_clk_src",
> > -		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> > +		.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
> >  		.ops = &clk_byte2_ops,
> >  		.flags = CLK_SET_RATE_PARENT,
> > @@ -818,7 +830,7 @@ static struct clk_rcg2 byte1_clk_src = {
> >  	.freq_tbl = byte_freq_tbl,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "byte1_clk_src",
> > -		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> > +		.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
> >  		.ops = &clk_byte2_ops,
> >  		.flags = CLK_SET_RATE_PARENT,
> > @@ -837,7 +849,7 @@ static struct clk_rcg2 edpaux_clk_src = {
> >  	.freq_tbl = ftbl_mdss_edpaux_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "edpaux_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -856,7 +868,7 @@ static struct clk_rcg2 edplink_clk_src = {
> >  	.freq_tbl = ftbl_mdss_edplink_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "edplink_clk_src",
> > -		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> > +		.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  		.flags = CLK_SET_RATE_PARENT,
> > @@ -876,7 +888,7 @@ static struct clk_rcg2 edppixel_clk_src = {
> >  	.freq_tbl = edp_pixel_freq_tbl,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "edppixel_clk_src",
> > -		.parent_names = mmcc_xo_dsi_hdmi_edp,
> > +		.parent_data = mmcc_xo_dsi_hdmi_edp,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp),
> >  		.ops = &clk_edp_pixel_ops,
> >  	},
> > @@ -894,7 +906,7 @@ static struct clk_rcg2 esc0_clk_src = {
> >  	.freq_tbl = ftbl_mdss_esc0_1_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "esc0_clk_src",
> > -		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> > +		.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -907,7 +919,7 @@ static struct clk_rcg2 esc1_clk_src = {
> >  	.freq_tbl = ftbl_mdss_esc0_1_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "esc1_clk_src",
> > -		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> > +		.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -925,7 +937,7 @@ static struct clk_rcg2 extpclk_clk_src = {
> >  	.freq_tbl = extpclk_freq_tbl,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "extpclk_clk_src",
> > -		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> > +		.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
> >  		.ops = &clk_byte_ops,
> >  		.flags = CLK_SET_RATE_PARENT,
> > @@ -944,7 +956,7 @@ static struct clk_rcg2 hdmi_clk_src = {
> >  	.freq_tbl = ftbl_mdss_hdmi_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "hdmi_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -962,7 +974,7 @@ static struct clk_rcg2 vsync_clk_src = {
> >  	.freq_tbl = ftbl_mdss_vsync_clk,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "vsync_clk_src",
> > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -975,8 +987,8 @@ static struct clk_branch camss_cci_cci_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_cci_cci_ahb_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_ahb_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_ahb_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -991,8 +1003,8 @@ static struct clk_branch camss_cci_cci_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_cci_cci_clk",
> > -			.parent_names = (const char *[]){
> > -				"cci_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&cci_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1008,8 +1020,8 @@ static struct clk_branch camss_csi0_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_csi0_ahb_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_ahb_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_ahb_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -1024,8 +1036,8 @@ static struct clk_branch camss_csi0_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_csi0_clk",
> > -			.parent_names = (const char *[]){
> > -				"csi0_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&csi0_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1041,8 +1053,8 @@ static struct clk_branch camss_csi0phy_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_csi0phy_clk",
> > -			.parent_names = (const char *[]){
> > -				"csi0_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&csi0_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1058,8 +1070,8 @@ static struct clk_branch camss_csi0pix_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_csi0pix_clk",
> > -			.parent_names = (const char *[]){
> > -				"csi0_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&csi0_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1075,8 +1087,8 @@ static struct clk_branch camss_csi0rdi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_csi0rdi_clk",
> > -			.parent_names = (const char *[]){
> > -				"csi0_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&csi0_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1092,8 +1104,8 @@ static struct clk_branch camss_csi1_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_csi1_ahb_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_ahb_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_ahb_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -1108,8 +1120,8 @@ static struct clk_branch camss_csi1_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_csi1_clk",
> > -			.parent_names = (const char *[]){
> > -				"csi1_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&csi1_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1125,8 +1137,8 @@ static struct clk_branch camss_csi1phy_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_csi1phy_clk",
> > -			.parent_names = (const char *[]){
> > -				"csi1_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&csi1_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1142,8 +1154,8 @@ static struct clk_branch camss_csi1pix_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_csi1pix_clk",
> > -			.parent_names = (const char *[]){
> > -				"csi1_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&csi1_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1159,8 +1171,8 @@ static struct clk_branch camss_csi1rdi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_csi1rdi_clk",
> > -			.parent_names = (const char *[]){
> > -				"csi1_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&csi1_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1176,8 +1188,8 @@ static struct clk_branch camss_csi2_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_csi2_ahb_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_ahb_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_ahb_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -1192,8 +1204,8 @@ static struct clk_branch camss_csi2_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_csi2_clk",
> > -			.parent_names = (const char *[]){
> > -				"csi2_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&csi2_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1209,8 +1221,8 @@ static struct clk_branch camss_csi2phy_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_csi2phy_clk",
> > -			.parent_names = (const char *[]){
> > -				"csi2_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&csi2_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1226,8 +1238,8 @@ static struct clk_branch camss_csi2pix_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_csi2pix_clk",
> > -			.parent_names = (const char *[]){
> > -				"csi2_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&csi2_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1243,8 +1255,8 @@ static struct clk_branch camss_csi2rdi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_csi2rdi_clk",
> > -			.parent_names = (const char *[]){
> > -				"csi2_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&csi2_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1260,8 +1272,8 @@ static struct clk_branch camss_csi3_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_csi3_ahb_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_ahb_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_ahb_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -1276,8 +1288,8 @@ static struct clk_branch camss_csi3_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_csi3_clk",
> > -			.parent_names = (const char *[]){
> > -				"csi3_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&csi3_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1293,8 +1305,8 @@ static struct clk_branch camss_csi3phy_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_csi3phy_clk",
> > -			.parent_names = (const char *[]){
> > -				"csi3_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&csi3_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1310,8 +1322,8 @@ static struct clk_branch camss_csi3pix_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_csi3pix_clk",
> > -			.parent_names = (const char *[]){
> > -				"csi3_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&csi3_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1327,8 +1339,8 @@ static struct clk_branch camss_csi3rdi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_csi3rdi_clk",
> > -			.parent_names = (const char *[]){
> > -				"csi3_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&csi3_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1344,8 +1356,8 @@ static struct clk_branch camss_csi_vfe0_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_csi_vfe0_clk",
> > -			.parent_names = (const char *[]){
> > -				"vfe0_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&vfe0_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1361,8 +1373,8 @@ static struct clk_branch camss_csi_vfe1_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_csi_vfe1_clk",
> > -			.parent_names = (const char *[]){
> > -				"vfe1_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&vfe1_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1378,8 +1390,8 @@ static struct clk_branch camss_gp0_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_gp0_clk",
> > -			.parent_names = (const char *[]){
> > -				"camss_gp0_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&camss_gp0_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1395,8 +1407,8 @@ static struct clk_branch camss_gp1_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_gp1_clk",
> > -			.parent_names = (const char *[]){
> > -				"camss_gp1_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&camss_gp1_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1412,8 +1424,8 @@ static struct clk_branch camss_ispif_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_ispif_ahb_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_ahb_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_ahb_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -1428,8 +1440,8 @@ static struct clk_branch camss_jpeg_jpeg0_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_jpeg_jpeg0_clk",
> > -			.parent_names = (const char *[]){
> > -				"jpeg0_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&jpeg0_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1445,8 +1457,8 @@ static struct clk_branch camss_jpeg_jpeg1_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_jpeg_jpeg1_clk",
> > -			.parent_names = (const char *[]){
> > -				"jpeg1_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&jpeg1_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1462,8 +1474,8 @@ static struct clk_branch camss_jpeg_jpeg2_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_jpeg_jpeg2_clk",
> > -			.parent_names = (const char *[]){
> > -				"jpeg2_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&jpeg2_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1479,8 +1491,8 @@ static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_jpeg_jpeg_ahb_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_ahb_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_ahb_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -1495,8 +1507,8 @@ static struct clk_branch camss_jpeg_jpeg_axi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_jpeg_jpeg_axi_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_axi_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_axi_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -1511,8 +1523,8 @@ static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_jpeg_jpeg_ocmemnoc_clk",
> > -			.parent_names = (const char *[]){
> > -				"ocmemnoc_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&ocmemnoc_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1528,8 +1540,8 @@ static struct clk_branch camss_mclk0_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_mclk0_clk",
> > -			.parent_names = (const char *[]){
> > -				"mclk0_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mclk0_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1545,8 +1557,8 @@ static struct clk_branch camss_mclk1_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_mclk1_clk",
> > -			.parent_names = (const char *[]){
> > -				"mclk1_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mclk1_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1562,8 +1574,8 @@ static struct clk_branch camss_mclk2_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_mclk2_clk",
> > -			.parent_names = (const char *[]){
> > -				"mclk2_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mclk2_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1579,8 +1591,8 @@ static struct clk_branch camss_mclk3_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_mclk3_clk",
> > -			.parent_names = (const char *[]){
> > -				"mclk3_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mclk3_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1596,8 +1608,8 @@ static struct clk_branch camss_micro_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_micro_ahb_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_ahb_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_ahb_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -1612,8 +1624,8 @@ static struct clk_branch camss_phy0_csi0phytimer_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_phy0_csi0phytimer_clk",
> > -			.parent_names = (const char *[]){
> > -				"csi0phytimer_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&csi0phytimer_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1629,8 +1641,8 @@ static struct clk_branch camss_phy1_csi1phytimer_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_phy1_csi1phytimer_clk",
> > -			.parent_names = (const char *[]){
> > -				"csi1phytimer_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&csi1phytimer_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1646,8 +1658,8 @@ static struct clk_branch camss_phy2_csi2phytimer_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_phy2_csi2phytimer_clk",
> > -			.parent_names = (const char *[]){
> > -				"csi2phytimer_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&csi2phytimer_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1663,8 +1675,8 @@ static struct clk_branch camss_top_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_top_ahb_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_ahb_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_ahb_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -1679,8 +1691,8 @@ static struct clk_branch camss_vfe_cpp_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_vfe_cpp_ahb_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_ahb_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_ahb_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -1695,8 +1707,8 @@ static struct clk_branch camss_vfe_cpp_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_vfe_cpp_clk",
> > -			.parent_names = (const char *[]){
> > -				"cpp_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&cpp_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1712,8 +1724,8 @@ static struct clk_branch camss_vfe_vfe0_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_vfe_vfe0_clk",
> > -			.parent_names = (const char *[]){
> > -				"vfe0_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&vfe0_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1729,8 +1741,8 @@ static struct clk_branch camss_vfe_vfe1_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_vfe_vfe1_clk",
> > -			.parent_names = (const char *[]){
> > -				"vfe1_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&vfe1_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1746,8 +1758,8 @@ static struct clk_branch camss_vfe_vfe_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_vfe_vfe_ahb_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_ahb_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_ahb_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -1762,8 +1774,8 @@ static struct clk_branch camss_vfe_vfe_axi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_vfe_vfe_axi_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_axi_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_axi_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -1778,8 +1790,8 @@ static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "camss_vfe_vfe_ocmemnoc_clk",
> > -			.parent_names = (const char *[]){
> > -				"ocmemnoc_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&ocmemnoc_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1795,8 +1807,8 @@ static struct clk_branch mdss_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "mdss_ahb_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_ahb_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_ahb_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -1811,8 +1823,8 @@ static struct clk_branch mdss_axi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "mdss_axi_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_axi_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_axi_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1828,8 +1840,8 @@ static struct clk_branch mdss_byte0_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "mdss_byte0_clk",
> > -			.parent_names = (const char *[]){
> > -				"byte0_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&byte0_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1845,8 +1857,8 @@ static struct clk_branch mdss_byte1_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "mdss_byte1_clk",
> > -			.parent_names = (const char *[]){
> > -				"byte1_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&byte1_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1862,8 +1874,8 @@ static struct clk_branch mdss_edpaux_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "mdss_edpaux_clk",
> > -			.parent_names = (const char *[]){
> > -				"edpaux_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&edpaux_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1879,8 +1891,8 @@ static struct clk_branch mdss_edplink_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "mdss_edplink_clk",
> > -			.parent_names = (const char *[]){
> > -				"edplink_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&edplink_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1896,8 +1908,8 @@ static struct clk_branch mdss_edppixel_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "mdss_edppixel_clk",
> > -			.parent_names = (const char *[]){
> > -				"edppixel_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&edppixel_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1913,8 +1925,8 @@ static struct clk_branch mdss_esc0_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "mdss_esc0_clk",
> > -			.parent_names = (const char *[]){
> > -				"esc0_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&esc0_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1930,8 +1942,8 @@ static struct clk_branch mdss_esc1_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "mdss_esc1_clk",
> > -			.parent_names = (const char *[]){
> > -				"esc1_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&esc1_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1947,8 +1959,8 @@ static struct clk_branch mdss_extpclk_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "mdss_extpclk_clk",
> > -			.parent_names = (const char *[]){
> > -				"extpclk_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&extpclk_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1964,8 +1976,8 @@ static struct clk_branch mdss_hdmi_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "mdss_hdmi_ahb_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_ahb_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_ahb_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -1980,8 +1992,8 @@ static struct clk_branch mdss_hdmi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "mdss_hdmi_clk",
> > -			.parent_names = (const char *[]){
> > -				"hdmi_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&hdmi_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1997,8 +2009,8 @@ static struct clk_branch mdss_mdp_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "mdss_mdp_clk",
> > -			.parent_names = (const char *[]){
> > -				"mdp_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mdp_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -2014,8 +2026,8 @@ static struct clk_branch mdss_mdp_lut_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "mdss_mdp_lut_clk",
> > -			.parent_names = (const char *[]){
> > -				"mdp_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mdp_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -2031,8 +2043,8 @@ static struct clk_branch mdss_pclk0_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "mdss_pclk0_clk",
> > -			.parent_names = (const char *[]){
> > -				"pclk0_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&pclk0_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -2048,8 +2060,8 @@ static struct clk_branch mdss_pclk1_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "mdss_pclk1_clk",
> > -			.parent_names = (const char *[]){
> > -				"pclk1_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&pclk1_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -2065,8 +2077,8 @@ static struct clk_branch mdss_vsync_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "mdss_vsync_clk",
> > -			.parent_names = (const char *[]){
> > -				"vsync_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&vsync_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -2082,8 +2094,8 @@ static struct clk_branch mmss_misc_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "mmss_misc_ahb_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_ahb_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_ahb_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -2098,8 +2110,8 @@ static struct clk_branch mmss_mmssnoc_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "mmss_mmssnoc_ahb_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_ahb_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_ahb_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -2115,8 +2127,8 @@ static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "mmss_mmssnoc_bto_ahb_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_ahb_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_ahb_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -2132,8 +2144,8 @@ static struct clk_branch mmss_mmssnoc_axi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "mmss_mmssnoc_axi_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_axi_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_axi_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > @@ -2149,8 +2161,8 @@ static struct clk_branch mmss_s0_axi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "mmss_s0_axi_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_axi_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_axi_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -2166,8 +2178,8 @@ static struct clk_branch ocmemcx_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "ocmemcx_ahb_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_ahb_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_ahb_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -2182,8 +2194,8 @@ static struct clk_branch ocmemcx_ocmemnoc_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "ocmemcx_ocmemnoc_clk",
> > -			.parent_names = (const char *[]){
> > -				"ocmemnoc_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&ocmemnoc_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -2199,8 +2211,8 @@ static struct clk_branch oxili_ocmemgx_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "oxili_ocmemgx_clk",
> > -			.parent_names = (const char *[]){
> > -				"gfx3d_clk_src",
> > +			.parent_data = (const struct clk_parent_data[]){
> > +				{ .fw_name = "gfx3d_clk_src", .name = "gfx3d_clk_src" },
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -2216,8 +2228,8 @@ static struct clk_branch ocmemnoc_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "ocmemnoc_clk",
> > -			.parent_names = (const char *[]){
> > -				"ocmemnoc_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&ocmemnoc_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -2233,8 +2245,8 @@ static struct clk_branch oxili_gfx3d_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "oxili_gfx3d_clk",
> > -			.parent_names = (const char *[]){
> > -				"gfx3d_clk_src",
> > +			.parent_data = (const struct clk_parent_data[]){
> > +				{ .fw_name = "gfx3d_clk_src", .name = "gfx3d_clk_src" },
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -2250,8 +2262,8 @@ static struct clk_branch oxilicx_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "oxilicx_ahb_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_ahb_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_ahb_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -2266,8 +2278,8 @@ static struct clk_branch oxilicx_axi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "oxilicx_axi_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_axi_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_axi_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -2282,8 +2294,8 @@ static struct clk_branch venus0_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "venus0_ahb_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_ahb_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_ahb_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -2298,8 +2310,8 @@ static struct clk_branch venus0_axi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "venus0_axi_clk",
> > -			.parent_names = (const char *[]){
> > -				"mmss_axi_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&mmss_axi_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> > @@ -2314,8 +2326,8 @@ static struct clk_branch venus0_ocmemnoc_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "venus0_ocmemnoc_clk",
> > -			.parent_names = (const char *[]){
> > -				"ocmemnoc_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&ocmemnoc_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -2331,8 +2343,8 @@ static struct clk_branch venus0_vcodec0_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "venus0_vcodec0_clk",
> > -			.parent_names = (const char *[]){
> > -				"vcodec0_clk_src",
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&vcodec0_clk_src.clkr.hw
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,

Re: [PATCH v3 08/11] clk: qcom: mmcc-msm8974: use parent_hws/_data instead of parent_names

[Konrad Dybcio]

On 7.11.2022 22:55, Bjorn Andersson wrote:
> On Mon, Oct 31, 2022 at 10:09:23PM +0100, Konrad Dybcio wrote:
>>
>>
>> On 30.10.2022 16:55, Dmitry Baryshkov wrote:
>>> Convert the clock driver to specify parent data rather than parent
>>> names, to actually bind using 'clock-names' specified in the DTS rather
>>> than global clock names. Use parent_hws where possible to refer parent
>>> clocks directly, skipping the lookup.
>>>
>>> Note, the system names for xo clocks were changed from "xo" to
>>> "xo_board" to follow the example of other platforms.
>> I think it should be reverse - look for "xo" and pass "xo_board" through DT.
>>
> 
> We have a clock with the global name "xo_board", so .name = "xo_board"
> should work just fine. Relying on the .name = "xo" would make us use the
> board-clock registered in gcc_msm8974_probe(), but with this we should
> be able to drop that.
> 
> We also don't have any clocks in the DT node, so picking "xo" for that
> would work fine as well.
> 
> 
> Please let me know if I'm missing something here.
I kinda forgot there was this ancient registered-in-gcc-probe() "xo" clock
and I just based this on the fact that it was previously parented to "xo".

Your approach does make sense. AFAICS "xo_board" was only introduced in 30fc4212d5417
as part of v4.6-rc1, but I doubt anyone would care about their 8974 not booting
with a >6-year-old DTB.. not to mention there were probably more compat breakages
throughout the years that went unnoticed, as 8974 was the first ever SMD/RPM
qcom SoC (or at least one that's supported upstream). So I think this can go through.

Konrad
> 
> Regards,
> Bjorn
> 
>> Konrad
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>>>  drivers/clk/qcom/mmcc-msm8974.c | 516 ++++++++++++++++----------------
>>>  1 file changed, 264 insertions(+), 252 deletions(-)
>>>
>>> diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
>>> index 57f1a351c8f6..4273fce9a4a4 100644
>>> --- a/drivers/clk/qcom/mmcc-msm8974.c
>>> +++ b/drivers/clk/qcom/mmcc-msm8974.c
>>> @@ -52,7 +52,9 @@ static struct clk_pll mmpll0 = {
>>>  	.status_bit = 17,
>>>          .clkr.hw.init = &(struct clk_init_data){
>>>                  .name = "mmpll0",
>>> -                .parent_names = (const char *[]){ "xo" },
>>> +                .parent_data = (const struct clk_parent_data[]){
>>> +			{ .fw_name = "xo", .name = "xo_board" },
>>> +		},
>>>                  .num_parents = 1,
>>>                  .ops = &clk_pll_ops,
>>>          },
>>> @@ -63,7 +65,9 @@ static struct clk_regmap mmpll0_vote = {
>>>  	.enable_mask = BIT(0),
>>>  	.hw.init = &(struct clk_init_data){
>>>  		.name = "mmpll0_vote",
>>> -		.parent_names = (const char *[]){ "mmpll0" },
>>> +		.parent_hws = (const struct clk_hw*[]){
>>> +			&mmpll0.clkr.hw
>>> +		},
>>>  		.num_parents = 1,
>>>  		.ops = &clk_pll_vote_ops,
>>>  	},
>>> @@ -79,7 +83,9 @@ static struct clk_pll mmpll1 = {
>>>  	.status_bit = 17,
>>>          .clkr.hw.init = &(struct clk_init_data){
>>>                  .name = "mmpll1",
>>> -                .parent_names = (const char *[]){ "xo" },
>>> +                .parent_data = (const struct clk_parent_data[]){
>>> +			{ .fw_name = "xo", .name = "xo_board" },
>>> +		},
>>>                  .num_parents = 1,
>>>                  .ops = &clk_pll_ops,
>>>          },
>>> @@ -90,7 +96,9 @@ static struct clk_regmap mmpll1_vote = {
>>>  	.enable_mask = BIT(1),
>>>  	.hw.init = &(struct clk_init_data){
>>>  		.name = "mmpll1_vote",
>>> -		.parent_names = (const char *[]){ "mmpll1" },
>>> +		.parent_hws = (const struct clk_hw*[]){
>>> +			&mmpll1.clkr.hw
>>> +		},
>>>  		.num_parents = 1,
>>>  		.ops = &clk_pll_vote_ops,
>>>  	},
>>> @@ -105,7 +113,9 @@ static struct clk_pll mmpll2 = {
>>>  	.status_reg = 0x411c,
>>>          .clkr.hw.init = &(struct clk_init_data){
>>>                  .name = "mmpll2",
>>> -                .parent_names = (const char *[]){ "xo" },
>>> +                .parent_data = (const struct clk_parent_data[]){
>>> +			{ .fw_name = "xo", .name = "xo_board" },
>>> +		},
>>>                  .num_parents = 1,
>>>                  .ops = &clk_pll_ops,
>>>          },
>>> @@ -121,7 +131,9 @@ static struct clk_pll mmpll3 = {
>>>  	.status_bit = 17,
>>>          .clkr.hw.init = &(struct clk_init_data){
>>>                  .name = "mmpll3",
>>> -                .parent_names = (const char *[]){ "xo" },
>>> +                .parent_data = (const struct clk_parent_data[]){
>>> +			{ .fw_name = "xo", .name = "xo_board" },
>>> +		},
>>>                  .num_parents = 1,
>>>                  .ops = &clk_pll_ops,
>>>          },
>>> @@ -134,11 +146,11 @@ static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
>>>  	{ P_GPLL0, 5 }
>>>  };
>>>  
>>> -static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
>>> -	"xo",
>>> -	"mmpll0_vote",
>>> -	"mmpll1_vote",
>>> -	"mmss_gpll0_vote",
>>> +static const struct clk_parent_data mmcc_xo_mmpll0_mmpll1_gpll0[] = {
>>> +	{ .fw_name = "xo", .name = "xo_board" },
>>> +	{ .hw = &mmpll0_vote.hw },
>>> +	{ .hw = &mmpll1_vote.hw },
>>> +	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
>>>  };
>>>  
>>>  static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
>>> @@ -150,13 +162,13 @@ static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
>>>  	{ P_DSI1PLL, 3 }
>>>  };
>>>  
>>> -static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
>>> -	"xo",
>>> -	"mmpll0_vote",
>>> -	"hdmipll",
>>> -	"mmss_gpll0_vote",
>>> -	"dsi0pll",
>>> -	"dsi1pll",
>>> +static const struct clk_parent_data mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
>>> +	{ .fw_name = "xo", .name = "xo_board" },
>>> +	{ .hw = &mmpll0_vote.hw },
>>> +	{ .fw_name = "hdmipll", .name = "hdmipll" },
>>> +	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
>>> +	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
>>> +	{ .fw_name = "dsi1pll", .name = "dsi1pll" },
>>>  };
>>>  
>>>  static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
>>> @@ -167,12 +179,12 @@ static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
>>>  	{ P_MMPLL3, 3 }
>>>  };
>>>  
>>> -static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
>>> -	"xo",
>>> -	"mmpll0_vote",
>>> -	"mmpll1_vote",
>>> -	"mmss_gpll0_vote",
>>> -	"mmpll3",
>>> +static const struct clk_parent_data mmcc_xo_mmpll0_1_3_gpll0[] = {
>>> +	{ .fw_name = "xo", .name = "xo_board" },
>>> +	{ .hw = &mmpll0_vote.hw },
>>> +	{ .hw = &mmpll1_vote.hw },
>>> +	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
>>> +	{ .hw = &mmpll3.clkr.hw },
>>>  };
>>>  
>>>  static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
>>> @@ -183,12 +195,12 @@ static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
>>>  	{ P_GPLL1, 4 }
>>>  };
>>>  
>>> -static const char * const mmcc_xo_mmpll0_1_gpll1_0[] = {
>>> -	"xo",
>>> -	"mmpll0_vote",
>>> -	"mmpll1_vote",
>>> -	"mmss_gpll0_vote",
>>> -	"gpll1_vote",
>>> +static const struct clk_parent_data mmcc_xo_mmpll0_1_gpll1_0[] = {
>>> +	{ .fw_name = "xo", .name = "xo_board" },
>>> +	{ .hw = &mmpll0_vote.hw },
>>> +	{ .hw = &mmpll1_vote.hw },
>>> +	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
>>> +	{ .fw_name = "gpll1_vote", .name = "gpll1_vote" },
>>>  };
>>>  
>>>  static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
>>> @@ -200,13 +212,13 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
>>>  	{ P_DSI1PLL, 2 }
>>>  };
>>>  
>>> -static const char * const mmcc_xo_dsi_hdmi_edp[] = {
>>> -	"xo",
>>> -	"edp_link_clk",
>>> -	"hdmipll",
>>> -	"edp_vco_div",
>>> -	"dsi0pll",
>>> -	"dsi1pll",
>>> +static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp[] = {
>>> +	{ .fw_name = "xo", .name = "xo_board" },
>>> +	{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
>>> +	{ .fw_name = "hdmipll", .name = "hdmipll" },
>>> +	{ .fw_name = "edp_vco_div", .name = "edp_vco_div" },
>>> +	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
>>> +	{ .fw_name = "dsi1pll", .name = "dsi1pll" },
>>>  };
>>>  
>>>  static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
>>> @@ -218,13 +230,13 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
>>>  	{ P_DSI1PLL, 2 }
>>>  };
>>>  
>>> -static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
>>> -	"xo",
>>> -	"edp_link_clk",
>>> -	"hdmipll",
>>> -	"gpll0_vote",
>>> -	"dsi0pll",
>>> -	"dsi1pll",
>>> +static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp_gpll0[] = {
>>> +	{ .fw_name = "xo", .name = "xo_board" },
>>> +	{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
>>> +	{ .fw_name = "hdmipll", .name = "hdmipll" },
>>> +	{ .fw_name = "gpll0_vote", .name = "gpll0_vote" },
>>> +	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
>>> +	{ .fw_name = "dsi1pll", .name = "dsi1pll" },
>>>  };
>>>  
>>>  static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
>>> @@ -236,13 +248,13 @@ static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
>>>  	{ P_DSI1PLL_BYTE, 2 }
>>>  };
>>>  
>>> -static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
>>> -	"xo",
>>> -	"edp_link_clk",
>>> -	"hdmipll",
>>> -	"gpll0_vote",
>>> -	"dsi0pllbyte",
>>> -	"dsi1pllbyte",
>>> +static const struct clk_parent_data mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
>>> +	{ .fw_name = "xo", .name = "xo_board" },
>>> +	{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
>>> +	{ .fw_name = "hdmipll", .name = "hdmipll" },
>>> +	{ .fw_name = "gpll0_vote", .name = "gpll0_vote" },
>>> +	{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
>>> +	{ .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" },
>>>  };
>>>  
>>>  static struct clk_rcg2 mmss_ahb_clk_src = {
>>> @@ -251,7 +263,7 @@ static struct clk_rcg2 mmss_ahb_clk_src = {
>>>  	.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "mmss_ahb_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -288,7 +300,7 @@ static struct clk_rcg2 mmss_axi_clk_src = {
>>>  	.freq_tbl = ftbl_mmss_axi_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "mmss_axi_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -312,7 +324,7 @@ static struct clk_rcg2 ocmemnoc_clk_src = {
>>>  	.freq_tbl = ftbl_ocmemnoc_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "ocmemnoc_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -331,7 +343,7 @@ static struct clk_rcg2 csi0_clk_src = {
>>>  	.freq_tbl = ftbl_camss_csi0_3_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "csi0_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -344,7 +356,7 @@ static struct clk_rcg2 csi1_clk_src = {
>>>  	.freq_tbl = ftbl_camss_csi0_3_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "csi1_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -357,7 +369,7 @@ static struct clk_rcg2 csi2_clk_src = {
>>>  	.freq_tbl = ftbl_camss_csi0_3_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "csi2_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -370,7 +382,7 @@ static struct clk_rcg2 csi3_clk_src = {
>>>  	.freq_tbl = ftbl_camss_csi0_3_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "csi3_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -417,7 +429,7 @@ static struct clk_rcg2 vfe0_clk_src = {
>>>  	.freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "vfe0_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -430,7 +442,7 @@ static struct clk_rcg2 vfe1_clk_src = {
>>>  	.freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "vfe1_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -471,7 +483,7 @@ static struct clk_rcg2 mdp_clk_src = {
>>>  	.freq_tbl = ftbl_mdss_mdp_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "mdp_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -494,7 +506,7 @@ static struct clk_rcg2 jpeg0_clk_src = {
>>>  	.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "jpeg0_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -507,7 +519,7 @@ static struct clk_rcg2 jpeg1_clk_src = {
>>>  	.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "jpeg1_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -520,7 +532,7 @@ static struct clk_rcg2 jpeg2_clk_src = {
>>>  	.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "jpeg2_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -533,7 +545,7 @@ static struct clk_rcg2 pclk0_clk_src = {
>>>  	.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "pclk0_clk_src",
>>> -		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
>>> +		.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
>>>  		.ops = &clk_pixel_ops,
>>>  		.flags = CLK_SET_RATE_PARENT,
>>> @@ -547,7 +559,7 @@ static struct clk_rcg2 pclk1_clk_src = {
>>>  	.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "pclk1_clk_src",
>>> -		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
>>> +		.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
>>>  		.ops = &clk_pixel_ops,
>>>  		.flags = CLK_SET_RATE_PARENT,
>>> @@ -580,7 +592,7 @@ static struct clk_rcg2 vcodec0_clk_src = {
>>>  	.freq_tbl = ftbl_venus0_vcodec0_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "vcodec0_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_1_3_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_1_3_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -598,7 +610,7 @@ static struct clk_rcg2 cci_clk_src = {
>>>  	.freq_tbl = ftbl_camss_cci_cci_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "cci_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -622,7 +634,7 @@ static struct clk_rcg2 camss_gp0_clk_src = {
>>>  	.freq_tbl = ftbl_camss_gp0_1_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "camss_gp0_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_1_gpll1_0,
>>> +		.parent_data = mmcc_xo_mmpll0_1_gpll1_0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -636,7 +648,7 @@ static struct clk_rcg2 camss_gp1_clk_src = {
>>>  	.freq_tbl = ftbl_camss_gp0_1_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "camss_gp1_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_1_gpll1_0,
>>> +		.parent_data = mmcc_xo_mmpll0_1_gpll1_0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -671,7 +683,7 @@ static struct clk_rcg2 mclk0_clk_src = {
>>>  	.freq_tbl = ftbl_camss_mclk0_3_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "mclk0_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -684,7 +696,7 @@ static struct clk_rcg2 mclk1_clk_src = {
>>>  	.freq_tbl = ftbl_camss_mclk0_3_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "mclk1_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -697,7 +709,7 @@ static struct clk_rcg2 mclk2_clk_src = {
>>>  	.freq_tbl = ftbl_camss_mclk0_3_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "mclk2_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -710,7 +722,7 @@ static struct clk_rcg2 mclk3_clk_src = {
>>>  	.freq_tbl = ftbl_camss_mclk0_3_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "mclk3_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -729,7 +741,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = {
>>>  	.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "csi0phytimer_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -742,7 +754,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = {
>>>  	.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "csi1phytimer_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -755,7 +767,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = {
>>>  	.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "csi2phytimer_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -786,7 +798,7 @@ static struct clk_rcg2 cpp_clk_src = {
>>>  	.freq_tbl = ftbl_camss_vfe_cpp_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "cpp_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -804,7 +816,7 @@ static struct clk_rcg2 byte0_clk_src = {
>>>  	.freq_tbl = byte_freq_tbl,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "byte0_clk_src",
>>> -		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
>>> +		.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
>>>  		.ops = &clk_byte2_ops,
>>>  		.flags = CLK_SET_RATE_PARENT,
>>> @@ -818,7 +830,7 @@ static struct clk_rcg2 byte1_clk_src = {
>>>  	.freq_tbl = byte_freq_tbl,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "byte1_clk_src",
>>> -		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
>>> +		.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
>>>  		.ops = &clk_byte2_ops,
>>>  		.flags = CLK_SET_RATE_PARENT,
>>> @@ -837,7 +849,7 @@ static struct clk_rcg2 edpaux_clk_src = {
>>>  	.freq_tbl = ftbl_mdss_edpaux_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "edpaux_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -856,7 +868,7 @@ static struct clk_rcg2 edplink_clk_src = {
>>>  	.freq_tbl = ftbl_mdss_edplink_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "edplink_clk_src",
>>> -		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
>>> +		.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  		.flags = CLK_SET_RATE_PARENT,
>>> @@ -876,7 +888,7 @@ static struct clk_rcg2 edppixel_clk_src = {
>>>  	.freq_tbl = edp_pixel_freq_tbl,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "edppixel_clk_src",
>>> -		.parent_names = mmcc_xo_dsi_hdmi_edp,
>>> +		.parent_data = mmcc_xo_dsi_hdmi_edp,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp),
>>>  		.ops = &clk_edp_pixel_ops,
>>>  	},
>>> @@ -894,7 +906,7 @@ static struct clk_rcg2 esc0_clk_src = {
>>>  	.freq_tbl = ftbl_mdss_esc0_1_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "esc0_clk_src",
>>> -		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
>>> +		.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -907,7 +919,7 @@ static struct clk_rcg2 esc1_clk_src = {
>>>  	.freq_tbl = ftbl_mdss_esc0_1_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "esc1_clk_src",
>>> -		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
>>> +		.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -925,7 +937,7 @@ static struct clk_rcg2 extpclk_clk_src = {
>>>  	.freq_tbl = extpclk_freq_tbl,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "extpclk_clk_src",
>>> -		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
>>> +		.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
>>>  		.ops = &clk_byte_ops,
>>>  		.flags = CLK_SET_RATE_PARENT,
>>> @@ -944,7 +956,7 @@ static struct clk_rcg2 hdmi_clk_src = {
>>>  	.freq_tbl = ftbl_mdss_hdmi_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "hdmi_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -962,7 +974,7 @@ static struct clk_rcg2 vsync_clk_src = {
>>>  	.freq_tbl = ftbl_mdss_vsync_clk,
>>>  	.clkr.hw.init = &(struct clk_init_data){
>>>  		.name = "vsync_clk_src",
>>> -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
>>> +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
>>>  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
>>>  		.ops = &clk_rcg2_ops,
>>>  	},
>>> @@ -975,8 +987,8 @@ static struct clk_branch camss_cci_cci_ahb_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_cci_cci_ahb_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_ahb_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_ahb_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -991,8 +1003,8 @@ static struct clk_branch camss_cci_cci_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_cci_cci_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"cci_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&cci_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1008,8 +1020,8 @@ static struct clk_branch camss_csi0_ahb_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_csi0_ahb_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_ahb_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_ahb_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -1024,8 +1036,8 @@ static struct clk_branch camss_csi0_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_csi0_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"csi0_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&csi0_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1041,8 +1053,8 @@ static struct clk_branch camss_csi0phy_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_csi0phy_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"csi0_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&csi0_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1058,8 +1070,8 @@ static struct clk_branch camss_csi0pix_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_csi0pix_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"csi0_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&csi0_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1075,8 +1087,8 @@ static struct clk_branch camss_csi0rdi_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_csi0rdi_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"csi0_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&csi0_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1092,8 +1104,8 @@ static struct clk_branch camss_csi1_ahb_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_csi1_ahb_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_ahb_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_ahb_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -1108,8 +1120,8 @@ static struct clk_branch camss_csi1_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_csi1_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"csi1_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&csi1_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1125,8 +1137,8 @@ static struct clk_branch camss_csi1phy_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_csi1phy_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"csi1_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&csi1_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1142,8 +1154,8 @@ static struct clk_branch camss_csi1pix_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_csi1pix_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"csi1_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&csi1_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1159,8 +1171,8 @@ static struct clk_branch camss_csi1rdi_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_csi1rdi_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"csi1_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&csi1_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1176,8 +1188,8 @@ static struct clk_branch camss_csi2_ahb_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_csi2_ahb_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_ahb_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_ahb_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -1192,8 +1204,8 @@ static struct clk_branch camss_csi2_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_csi2_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"csi2_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&csi2_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1209,8 +1221,8 @@ static struct clk_branch camss_csi2phy_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_csi2phy_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"csi2_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&csi2_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1226,8 +1238,8 @@ static struct clk_branch camss_csi2pix_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_csi2pix_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"csi2_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&csi2_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1243,8 +1255,8 @@ static struct clk_branch camss_csi2rdi_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_csi2rdi_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"csi2_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&csi2_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1260,8 +1272,8 @@ static struct clk_branch camss_csi3_ahb_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_csi3_ahb_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_ahb_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_ahb_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -1276,8 +1288,8 @@ static struct clk_branch camss_csi3_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_csi3_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"csi3_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&csi3_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1293,8 +1305,8 @@ static struct clk_branch camss_csi3phy_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_csi3phy_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"csi3_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&csi3_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1310,8 +1322,8 @@ static struct clk_branch camss_csi3pix_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_csi3pix_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"csi3_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&csi3_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1327,8 +1339,8 @@ static struct clk_branch camss_csi3rdi_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_csi3rdi_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"csi3_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&csi3_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1344,8 +1356,8 @@ static struct clk_branch camss_csi_vfe0_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_csi_vfe0_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"vfe0_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&vfe0_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1361,8 +1373,8 @@ static struct clk_branch camss_csi_vfe1_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_csi_vfe1_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"vfe1_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&vfe1_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1378,8 +1390,8 @@ static struct clk_branch camss_gp0_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_gp0_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"camss_gp0_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&camss_gp0_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1395,8 +1407,8 @@ static struct clk_branch camss_gp1_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_gp1_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"camss_gp1_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&camss_gp1_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1412,8 +1424,8 @@ static struct clk_branch camss_ispif_ahb_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_ispif_ahb_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_ahb_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_ahb_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -1428,8 +1440,8 @@ static struct clk_branch camss_jpeg_jpeg0_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_jpeg_jpeg0_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"jpeg0_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&jpeg0_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1445,8 +1457,8 @@ static struct clk_branch camss_jpeg_jpeg1_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_jpeg_jpeg1_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"jpeg1_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&jpeg1_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1462,8 +1474,8 @@ static struct clk_branch camss_jpeg_jpeg2_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_jpeg_jpeg2_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"jpeg2_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&jpeg2_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1479,8 +1491,8 @@ static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_jpeg_jpeg_ahb_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_ahb_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_ahb_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -1495,8 +1507,8 @@ static struct clk_branch camss_jpeg_jpeg_axi_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_jpeg_jpeg_axi_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_axi_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_axi_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -1511,8 +1523,8 @@ static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_jpeg_jpeg_ocmemnoc_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"ocmemnoc_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&ocmemnoc_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1528,8 +1540,8 @@ static struct clk_branch camss_mclk0_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_mclk0_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mclk0_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mclk0_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1545,8 +1557,8 @@ static struct clk_branch camss_mclk1_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_mclk1_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mclk1_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mclk1_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1562,8 +1574,8 @@ static struct clk_branch camss_mclk2_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_mclk2_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mclk2_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mclk2_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1579,8 +1591,8 @@ static struct clk_branch camss_mclk3_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_mclk3_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mclk3_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mclk3_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1596,8 +1608,8 @@ static struct clk_branch camss_micro_ahb_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_micro_ahb_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_ahb_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_ahb_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -1612,8 +1624,8 @@ static struct clk_branch camss_phy0_csi0phytimer_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_phy0_csi0phytimer_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"csi0phytimer_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&csi0phytimer_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1629,8 +1641,8 @@ static struct clk_branch camss_phy1_csi1phytimer_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_phy1_csi1phytimer_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"csi1phytimer_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&csi1phytimer_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1646,8 +1658,8 @@ static struct clk_branch camss_phy2_csi2phytimer_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_phy2_csi2phytimer_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"csi2phytimer_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&csi2phytimer_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1663,8 +1675,8 @@ static struct clk_branch camss_top_ahb_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_top_ahb_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_ahb_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_ahb_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -1679,8 +1691,8 @@ static struct clk_branch camss_vfe_cpp_ahb_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_vfe_cpp_ahb_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_ahb_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_ahb_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -1695,8 +1707,8 @@ static struct clk_branch camss_vfe_cpp_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_vfe_cpp_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"cpp_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&cpp_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1712,8 +1724,8 @@ static struct clk_branch camss_vfe_vfe0_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_vfe_vfe0_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"vfe0_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&vfe0_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1729,8 +1741,8 @@ static struct clk_branch camss_vfe_vfe1_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_vfe_vfe1_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"vfe1_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&vfe1_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1746,8 +1758,8 @@ static struct clk_branch camss_vfe_vfe_ahb_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_vfe_vfe_ahb_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_ahb_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_ahb_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -1762,8 +1774,8 @@ static struct clk_branch camss_vfe_vfe_axi_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_vfe_vfe_axi_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_axi_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_axi_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -1778,8 +1790,8 @@ static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "camss_vfe_vfe_ocmemnoc_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"ocmemnoc_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&ocmemnoc_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1795,8 +1807,8 @@ static struct clk_branch mdss_ahb_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "mdss_ahb_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_ahb_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_ahb_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -1811,8 +1823,8 @@ static struct clk_branch mdss_axi_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "mdss_axi_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_axi_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_axi_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1828,8 +1840,8 @@ static struct clk_branch mdss_byte0_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "mdss_byte0_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"byte0_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&byte0_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1845,8 +1857,8 @@ static struct clk_branch mdss_byte1_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "mdss_byte1_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"byte1_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&byte1_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1862,8 +1874,8 @@ static struct clk_branch mdss_edpaux_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "mdss_edpaux_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"edpaux_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&edpaux_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1879,8 +1891,8 @@ static struct clk_branch mdss_edplink_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "mdss_edplink_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"edplink_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&edplink_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1896,8 +1908,8 @@ static struct clk_branch mdss_edppixel_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "mdss_edppixel_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"edppixel_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&edppixel_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1913,8 +1925,8 @@ static struct clk_branch mdss_esc0_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "mdss_esc0_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"esc0_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&esc0_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1930,8 +1942,8 @@ static struct clk_branch mdss_esc1_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "mdss_esc1_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"esc1_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&esc1_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1947,8 +1959,8 @@ static struct clk_branch mdss_extpclk_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "mdss_extpclk_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"extpclk_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&extpclk_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1964,8 +1976,8 @@ static struct clk_branch mdss_hdmi_ahb_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "mdss_hdmi_ahb_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_ahb_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_ahb_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -1980,8 +1992,8 @@ static struct clk_branch mdss_hdmi_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "mdss_hdmi_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"hdmi_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&hdmi_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -1997,8 +2009,8 @@ static struct clk_branch mdss_mdp_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "mdss_mdp_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mdp_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mdp_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -2014,8 +2026,8 @@ static struct clk_branch mdss_mdp_lut_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "mdss_mdp_lut_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mdp_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mdp_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -2031,8 +2043,8 @@ static struct clk_branch mdss_pclk0_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "mdss_pclk0_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"pclk0_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&pclk0_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -2048,8 +2060,8 @@ static struct clk_branch mdss_pclk1_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "mdss_pclk1_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"pclk1_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&pclk1_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -2065,8 +2077,8 @@ static struct clk_branch mdss_vsync_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "mdss_vsync_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"vsync_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&vsync_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -2082,8 +2094,8 @@ static struct clk_branch mmss_misc_ahb_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "mmss_misc_ahb_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_ahb_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_ahb_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -2098,8 +2110,8 @@ static struct clk_branch mmss_mmssnoc_ahb_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "mmss_mmssnoc_ahb_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_ahb_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_ahb_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -2115,8 +2127,8 @@ static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "mmss_mmssnoc_bto_ahb_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_ahb_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_ahb_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -2132,8 +2144,8 @@ static struct clk_branch mmss_mmssnoc_axi_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "mmss_mmssnoc_axi_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_axi_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_axi_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>>> @@ -2149,8 +2161,8 @@ static struct clk_branch mmss_s0_axi_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "mmss_s0_axi_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_axi_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_axi_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -2166,8 +2178,8 @@ static struct clk_branch ocmemcx_ahb_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "ocmemcx_ahb_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_ahb_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_ahb_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -2182,8 +2194,8 @@ static struct clk_branch ocmemcx_ocmemnoc_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "ocmemcx_ocmemnoc_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"ocmemnoc_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&ocmemnoc_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -2199,8 +2211,8 @@ static struct clk_branch oxili_ocmemgx_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "oxili_ocmemgx_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"gfx3d_clk_src",
>>> +			.parent_data = (const struct clk_parent_data[]){
>>> +				{ .fw_name = "gfx3d_clk_src", .name = "gfx3d_clk_src" },
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -2216,8 +2228,8 @@ static struct clk_branch ocmemnoc_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "ocmemnoc_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"ocmemnoc_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&ocmemnoc_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -2233,8 +2245,8 @@ static struct clk_branch oxili_gfx3d_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "oxili_gfx3d_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"gfx3d_clk_src",
>>> +			.parent_data = (const struct clk_parent_data[]){
>>> +				{ .fw_name = "gfx3d_clk_src", .name = "gfx3d_clk_src" },
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -2250,8 +2262,8 @@ static struct clk_branch oxilicx_ahb_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "oxilicx_ahb_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_ahb_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_ahb_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -2266,8 +2278,8 @@ static struct clk_branch oxilicx_axi_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "oxilicx_axi_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_axi_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_axi_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -2282,8 +2294,8 @@ static struct clk_branch venus0_ahb_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "venus0_ahb_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_ahb_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_ahb_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -2298,8 +2310,8 @@ static struct clk_branch venus0_axi_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "venus0_axi_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"mmss_axi_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&mmss_axi_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.ops = &clk_branch2_ops,
>>> @@ -2314,8 +2326,8 @@ static struct clk_branch venus0_ocmemnoc_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "venus0_ocmemnoc_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"ocmemnoc_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&ocmemnoc_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,
>>> @@ -2331,8 +2343,8 @@ static struct clk_branch venus0_vcodec0_clk = {
>>>  		.enable_mask = BIT(0),
>>>  		.hw.init = &(struct clk_init_data){
>>>  			.name = "venus0_vcodec0_clk",
>>> -			.parent_names = (const char *[]){
>>> -				"vcodec0_clk_src",
>>> +			.parent_hws = (const struct clk_hw*[]){
>>> +				&vcodec0_clk_src.clkr.hw
>>>  			},
>>>  			.num_parents = 1,
>>>  			.flags = CLK_SET_RATE_PARENT,

Re: [PATCH v3 08/11] clk: qcom: mmcc-msm8974: use parent_hws/_data instead of parent_names

[Marijn Suijten]

On 2022-11-07 15:55:30, Bjorn Andersson wrote:
> On Mon, Oct 31, 2022 at 10:09:23PM +0100, Konrad Dybcio wrote:
> > 
> > 
> > On 30.10.2022 16:55, Dmitry Baryshkov wrote:
> > > Convert the clock driver to specify parent data rather than parent
> > > names, to actually bind using 'clock-names' specified in the DTS rather
> > > than global clock names. Use parent_hws where possible to refer parent
> > > clocks directly, skipping the lookup.
> > > 
> > > Note, the system names for xo clocks were changed from "xo" to
> > > "xo_board" to follow the example of other platforms.
> > I think it should be reverse - look for "xo" and pass "xo_board" through DT.
> > 
> 
> We have a clock with the global name "xo_board", so .name = "xo_board"
> should work just fine. Relying on the .name = "xo" would make us use the
> board-clock registered in gcc_msm8974_probe(), but with this we should
> be able to drop that.

On that note I don't think [1] ever landed, which does the same for
sdm660 gcc now that all the global node name lookups have been squared
away.

[1]: https://lore.kernel.org/linux-arm-msm/20210830182445.167527-3-marijn.suijten@somainline.org/

Should it be resent?

- Marijn

> 
> We also don't have any clocks in the DT node, so picking "xo" for that
> would work fine as well.
> 
> 
> Please let me know if I'm missing something here.
> 
> Regards,
> Bjorn
> 
> > Konrad
> > > 
> > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > ---
> > >  drivers/clk/qcom/mmcc-msm8974.c | 516 ++++++++++++++++----------------
> > >  1 file changed, 264 insertions(+), 252 deletions(-)
> > > 
> > > diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
> > > index 57f1a351c8f6..4273fce9a4a4 100644
> > > --- a/drivers/clk/qcom/mmcc-msm8974.c
> > > +++ b/drivers/clk/qcom/mmcc-msm8974.c
> > > @@ -52,7 +52,9 @@ static struct clk_pll mmpll0 = {
> > >  	.status_bit = 17,
> > >          .clkr.hw.init = &(struct clk_init_data){
> > >                  .name = "mmpll0",
> > > -                .parent_names = (const char *[]){ "xo" },
> > > +                .parent_data = (const struct clk_parent_data[]){
> > > +			{ .fw_name = "xo", .name = "xo_board" },
> > > +		},
> > >                  .num_parents = 1,
> > >                  .ops = &clk_pll_ops,
> > >          },
> > > @@ -63,7 +65,9 @@ static struct clk_regmap mmpll0_vote = {
> > >  	.enable_mask = BIT(0),
> > >  	.hw.init = &(struct clk_init_data){
> > >  		.name = "mmpll0_vote",
> > > -		.parent_names = (const char *[]){ "mmpll0" },
> > > +		.parent_hws = (const struct clk_hw*[]){
> > > +			&mmpll0.clkr.hw
> > > +		},
> > >  		.num_parents = 1,
> > >  		.ops = &clk_pll_vote_ops,
> > >  	},
> > > @@ -79,7 +83,9 @@ static struct clk_pll mmpll1 = {
> > >  	.status_bit = 17,
> > >          .clkr.hw.init = &(struct clk_init_data){
> > >                  .name = "mmpll1",
> > > -                .parent_names = (const char *[]){ "xo" },
> > > +                .parent_data = (const struct clk_parent_data[]){
> > > +			{ .fw_name = "xo", .name = "xo_board" },
> > > +		},
> > >                  .num_parents = 1,
> > >                  .ops = &clk_pll_ops,
> > >          },
> > > @@ -90,7 +96,9 @@ static struct clk_regmap mmpll1_vote = {
> > >  	.enable_mask = BIT(1),
> > >  	.hw.init = &(struct clk_init_data){
> > >  		.name = "mmpll1_vote",
> > > -		.parent_names = (const char *[]){ "mmpll1" },
> > > +		.parent_hws = (const struct clk_hw*[]){
> > > +			&mmpll1.clkr.hw
> > > +		},
> > >  		.num_parents = 1,
> > >  		.ops = &clk_pll_vote_ops,
> > >  	},
> > > @@ -105,7 +113,9 @@ static struct clk_pll mmpll2 = {
> > >  	.status_reg = 0x411c,
> > >          .clkr.hw.init = &(struct clk_init_data){
> > >                  .name = "mmpll2",
> > > -                .parent_names = (const char *[]){ "xo" },
> > > +                .parent_data = (const struct clk_parent_data[]){
> > > +			{ .fw_name = "xo", .name = "xo_board" },
> > > +		},
> > >                  .num_parents = 1,
> > >                  .ops = &clk_pll_ops,
> > >          },
> > > @@ -121,7 +131,9 @@ static struct clk_pll mmpll3 = {
> > >  	.status_bit = 17,
> > >          .clkr.hw.init = &(struct clk_init_data){
> > >                  .name = "mmpll3",
> > > -                .parent_names = (const char *[]){ "xo" },
> > > +                .parent_data = (const struct clk_parent_data[]){
> > > +			{ .fw_name = "xo", .name = "xo_board" },
> > > +		},
> > >                  .num_parents = 1,
> > >                  .ops = &clk_pll_ops,
> > >          },
> > > @@ -134,11 +146,11 @@ static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
> > >  	{ P_GPLL0, 5 }
> > >  };
> > >  
> > > -static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
> > > -	"xo",
> > > -	"mmpll0_vote",
> > > -	"mmpll1_vote",
> > > -	"mmss_gpll0_vote",
> > > +static const struct clk_parent_data mmcc_xo_mmpll0_mmpll1_gpll0[] = {
> > > +	{ .fw_name = "xo", .name = "xo_board" },
> > > +	{ .hw = &mmpll0_vote.hw },
> > > +	{ .hw = &mmpll1_vote.hw },
> > > +	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
> > >  };
> > >  
> > >  static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
> > > @@ -150,13 +162,13 @@ static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
> > >  	{ P_DSI1PLL, 3 }
> > >  };
> > >  
> > > -static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
> > > -	"xo",
> > > -	"mmpll0_vote",
> > > -	"hdmipll",
> > > -	"mmss_gpll0_vote",
> > > -	"dsi0pll",
> > > -	"dsi1pll",
> > > +static const struct clk_parent_data mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
> > > +	{ .fw_name = "xo", .name = "xo_board" },
> > > +	{ .hw = &mmpll0_vote.hw },
> > > +	{ .fw_name = "hdmipll", .name = "hdmipll" },
> > > +	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
> > > +	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
> > > +	{ .fw_name = "dsi1pll", .name = "dsi1pll" },
> > >  };
> > >  
> > >  static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
> > > @@ -167,12 +179,12 @@ static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
> > >  	{ P_MMPLL3, 3 }
> > >  };
> > >  
> > > -static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
> > > -	"xo",
> > > -	"mmpll0_vote",
> > > -	"mmpll1_vote",
> > > -	"mmss_gpll0_vote",
> > > -	"mmpll3",
> > > +static const struct clk_parent_data mmcc_xo_mmpll0_1_3_gpll0[] = {
> > > +	{ .fw_name = "xo", .name = "xo_board" },
> > > +	{ .hw = &mmpll0_vote.hw },
> > > +	{ .hw = &mmpll1_vote.hw },
> > > +	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
> > > +	{ .hw = &mmpll3.clkr.hw },
> > >  };
> > >  
> > >  static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
> > > @@ -183,12 +195,12 @@ static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
> > >  	{ P_GPLL1, 4 }
> > >  };
> > >  
> > > -static const char * const mmcc_xo_mmpll0_1_gpll1_0[] = {
> > > -	"xo",
> > > -	"mmpll0_vote",
> > > -	"mmpll1_vote",
> > > -	"mmss_gpll0_vote",
> > > -	"gpll1_vote",
> > > +static const struct clk_parent_data mmcc_xo_mmpll0_1_gpll1_0[] = {
> > > +	{ .fw_name = "xo", .name = "xo_board" },
> > > +	{ .hw = &mmpll0_vote.hw },
> > > +	{ .hw = &mmpll1_vote.hw },
> > > +	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
> > > +	{ .fw_name = "gpll1_vote", .name = "gpll1_vote" },
> > >  };
> > >  
> > >  static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
> > > @@ -200,13 +212,13 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
> > >  	{ P_DSI1PLL, 2 }
> > >  };
> > >  
> > > -static const char * const mmcc_xo_dsi_hdmi_edp[] = {
> > > -	"xo",
> > > -	"edp_link_clk",
> > > -	"hdmipll",
> > > -	"edp_vco_div",
> > > -	"dsi0pll",
> > > -	"dsi1pll",
> > > +static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp[] = {
> > > +	{ .fw_name = "xo", .name = "xo_board" },
> > > +	{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
> > > +	{ .fw_name = "hdmipll", .name = "hdmipll" },
> > > +	{ .fw_name = "edp_vco_div", .name = "edp_vco_div" },
> > > +	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
> > > +	{ .fw_name = "dsi1pll", .name = "dsi1pll" },
> > >  };
> > >  
> > >  static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
> > > @@ -218,13 +230,13 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
> > >  	{ P_DSI1PLL, 2 }
> > >  };
> > >  
> > > -static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
> > > -	"xo",
> > > -	"edp_link_clk",
> > > -	"hdmipll",
> > > -	"gpll0_vote",
> > > -	"dsi0pll",
> > > -	"dsi1pll",
> > > +static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp_gpll0[] = {
> > > +	{ .fw_name = "xo", .name = "xo_board" },
> > > +	{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
> > > +	{ .fw_name = "hdmipll", .name = "hdmipll" },
> > > +	{ .fw_name = "gpll0_vote", .name = "gpll0_vote" },
> > > +	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
> > > +	{ .fw_name = "dsi1pll", .name = "dsi1pll" },
> > >  };
> > >  
> > >  static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
> > > @@ -236,13 +248,13 @@ static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
> > >  	{ P_DSI1PLL_BYTE, 2 }
> > >  };
> > >  
> > > -static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
> > > -	"xo",
> > > -	"edp_link_clk",
> > > -	"hdmipll",
> > > -	"gpll0_vote",
> > > -	"dsi0pllbyte",
> > > -	"dsi1pllbyte",
> > > +static const struct clk_parent_data mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
> > > +	{ .fw_name = "xo", .name = "xo_board" },
> > > +	{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
> > > +	{ .fw_name = "hdmipll", .name = "hdmipll" },
> > > +	{ .fw_name = "gpll0_vote", .name = "gpll0_vote" },
> > > +	{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
> > > +	{ .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" },
> > >  };
> > >  
> > >  static struct clk_rcg2 mmss_ahb_clk_src = {
> > > @@ -251,7 +263,7 @@ static struct clk_rcg2 mmss_ahb_clk_src = {
> > >  	.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "mmss_ahb_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -288,7 +300,7 @@ static struct clk_rcg2 mmss_axi_clk_src = {
> > >  	.freq_tbl = ftbl_mmss_axi_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "mmss_axi_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -312,7 +324,7 @@ static struct clk_rcg2 ocmemnoc_clk_src = {
> > >  	.freq_tbl = ftbl_ocmemnoc_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "ocmemnoc_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -331,7 +343,7 @@ static struct clk_rcg2 csi0_clk_src = {
> > >  	.freq_tbl = ftbl_camss_csi0_3_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "csi0_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -344,7 +356,7 @@ static struct clk_rcg2 csi1_clk_src = {
> > >  	.freq_tbl = ftbl_camss_csi0_3_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "csi1_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -357,7 +369,7 @@ static struct clk_rcg2 csi2_clk_src = {
> > >  	.freq_tbl = ftbl_camss_csi0_3_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "csi2_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -370,7 +382,7 @@ static struct clk_rcg2 csi3_clk_src = {
> > >  	.freq_tbl = ftbl_camss_csi0_3_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "csi3_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -417,7 +429,7 @@ static struct clk_rcg2 vfe0_clk_src = {
> > >  	.freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "vfe0_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -430,7 +442,7 @@ static struct clk_rcg2 vfe1_clk_src = {
> > >  	.freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "vfe1_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -471,7 +483,7 @@ static struct clk_rcg2 mdp_clk_src = {
> > >  	.freq_tbl = ftbl_mdss_mdp_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "mdp_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -494,7 +506,7 @@ static struct clk_rcg2 jpeg0_clk_src = {
> > >  	.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "jpeg0_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -507,7 +519,7 @@ static struct clk_rcg2 jpeg1_clk_src = {
> > >  	.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "jpeg1_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -520,7 +532,7 @@ static struct clk_rcg2 jpeg2_clk_src = {
> > >  	.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "jpeg2_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -533,7 +545,7 @@ static struct clk_rcg2 pclk0_clk_src = {
> > >  	.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "pclk0_clk_src",
> > > -		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> > > +		.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
> > >  		.ops = &clk_pixel_ops,
> > >  		.flags = CLK_SET_RATE_PARENT,
> > > @@ -547,7 +559,7 @@ static struct clk_rcg2 pclk1_clk_src = {
> > >  	.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "pclk1_clk_src",
> > > -		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> > > +		.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
> > >  		.ops = &clk_pixel_ops,
> > >  		.flags = CLK_SET_RATE_PARENT,
> > > @@ -580,7 +592,7 @@ static struct clk_rcg2 vcodec0_clk_src = {
> > >  	.freq_tbl = ftbl_venus0_vcodec0_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "vcodec0_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_1_3_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_1_3_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -598,7 +610,7 @@ static struct clk_rcg2 cci_clk_src = {
> > >  	.freq_tbl = ftbl_camss_cci_cci_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "cci_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -622,7 +634,7 @@ static struct clk_rcg2 camss_gp0_clk_src = {
> > >  	.freq_tbl = ftbl_camss_gp0_1_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "camss_gp0_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_1_gpll1_0,
> > > +		.parent_data = mmcc_xo_mmpll0_1_gpll1_0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -636,7 +648,7 @@ static struct clk_rcg2 camss_gp1_clk_src = {
> > >  	.freq_tbl = ftbl_camss_gp0_1_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "camss_gp1_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_1_gpll1_0,
> > > +		.parent_data = mmcc_xo_mmpll0_1_gpll1_0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -671,7 +683,7 @@ static struct clk_rcg2 mclk0_clk_src = {
> > >  	.freq_tbl = ftbl_camss_mclk0_3_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "mclk0_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -684,7 +696,7 @@ static struct clk_rcg2 mclk1_clk_src = {
> > >  	.freq_tbl = ftbl_camss_mclk0_3_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "mclk1_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -697,7 +709,7 @@ static struct clk_rcg2 mclk2_clk_src = {
> > >  	.freq_tbl = ftbl_camss_mclk0_3_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "mclk2_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -710,7 +722,7 @@ static struct clk_rcg2 mclk3_clk_src = {
> > >  	.freq_tbl = ftbl_camss_mclk0_3_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "mclk3_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -729,7 +741,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = {
> > >  	.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "csi0phytimer_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -742,7 +754,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = {
> > >  	.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "csi1phytimer_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -755,7 +767,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = {
> > >  	.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "csi2phytimer_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -786,7 +798,7 @@ static struct clk_rcg2 cpp_clk_src = {
> > >  	.freq_tbl = ftbl_camss_vfe_cpp_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "cpp_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -804,7 +816,7 @@ static struct clk_rcg2 byte0_clk_src = {
> > >  	.freq_tbl = byte_freq_tbl,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "byte0_clk_src",
> > > -		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> > > +		.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
> > >  		.ops = &clk_byte2_ops,
> > >  		.flags = CLK_SET_RATE_PARENT,
> > > @@ -818,7 +830,7 @@ static struct clk_rcg2 byte1_clk_src = {
> > >  	.freq_tbl = byte_freq_tbl,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "byte1_clk_src",
> > > -		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> > > +		.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
> > >  		.ops = &clk_byte2_ops,
> > >  		.flags = CLK_SET_RATE_PARENT,
> > > @@ -837,7 +849,7 @@ static struct clk_rcg2 edpaux_clk_src = {
> > >  	.freq_tbl = ftbl_mdss_edpaux_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "edpaux_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -856,7 +868,7 @@ static struct clk_rcg2 edplink_clk_src = {
> > >  	.freq_tbl = ftbl_mdss_edplink_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "edplink_clk_src",
> > > -		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> > > +		.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  		.flags = CLK_SET_RATE_PARENT,
> > > @@ -876,7 +888,7 @@ static struct clk_rcg2 edppixel_clk_src = {
> > >  	.freq_tbl = edp_pixel_freq_tbl,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "edppixel_clk_src",
> > > -		.parent_names = mmcc_xo_dsi_hdmi_edp,
> > > +		.parent_data = mmcc_xo_dsi_hdmi_edp,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp),
> > >  		.ops = &clk_edp_pixel_ops,
> > >  	},
> > > @@ -894,7 +906,7 @@ static struct clk_rcg2 esc0_clk_src = {
> > >  	.freq_tbl = ftbl_mdss_esc0_1_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "esc0_clk_src",
> > > -		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> > > +		.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -907,7 +919,7 @@ static struct clk_rcg2 esc1_clk_src = {
> > >  	.freq_tbl = ftbl_mdss_esc0_1_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "esc1_clk_src",
> > > -		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> > > +		.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -925,7 +937,7 @@ static struct clk_rcg2 extpclk_clk_src = {
> > >  	.freq_tbl = extpclk_freq_tbl,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "extpclk_clk_src",
> > > -		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> > > +		.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
> > >  		.ops = &clk_byte_ops,
> > >  		.flags = CLK_SET_RATE_PARENT,
> > > @@ -944,7 +956,7 @@ static struct clk_rcg2 hdmi_clk_src = {
> > >  	.freq_tbl = ftbl_mdss_hdmi_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "hdmi_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -962,7 +974,7 @@ static struct clk_rcg2 vsync_clk_src = {
> > >  	.freq_tbl = ftbl_mdss_vsync_clk,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "vsync_clk_src",
> > > -		.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> > > +		.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> > >  		.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -975,8 +987,8 @@ static struct clk_branch camss_cci_cci_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_cci_cci_ahb_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_ahb_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_ahb_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -991,8 +1003,8 @@ static struct clk_branch camss_cci_cci_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_cci_cci_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"cci_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&cci_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1008,8 +1020,8 @@ static struct clk_branch camss_csi0_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_csi0_ahb_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_ahb_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_ahb_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1024,8 +1036,8 @@ static struct clk_branch camss_csi0_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_csi0_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"csi0_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&csi0_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1041,8 +1053,8 @@ static struct clk_branch camss_csi0phy_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_csi0phy_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"csi0_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&csi0_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1058,8 +1070,8 @@ static struct clk_branch camss_csi0pix_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_csi0pix_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"csi0_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&csi0_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1075,8 +1087,8 @@ static struct clk_branch camss_csi0rdi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_csi0rdi_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"csi0_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&csi0_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1092,8 +1104,8 @@ static struct clk_branch camss_csi1_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_csi1_ahb_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_ahb_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_ahb_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1108,8 +1120,8 @@ static struct clk_branch camss_csi1_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_csi1_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"csi1_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&csi1_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1125,8 +1137,8 @@ static struct clk_branch camss_csi1phy_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_csi1phy_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"csi1_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&csi1_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1142,8 +1154,8 @@ static struct clk_branch camss_csi1pix_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_csi1pix_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"csi1_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&csi1_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1159,8 +1171,8 @@ static struct clk_branch camss_csi1rdi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_csi1rdi_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"csi1_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&csi1_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1176,8 +1188,8 @@ static struct clk_branch camss_csi2_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_csi2_ahb_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_ahb_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_ahb_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1192,8 +1204,8 @@ static struct clk_branch camss_csi2_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_csi2_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"csi2_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&csi2_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1209,8 +1221,8 @@ static struct clk_branch camss_csi2phy_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_csi2phy_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"csi2_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&csi2_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1226,8 +1238,8 @@ static struct clk_branch camss_csi2pix_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_csi2pix_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"csi2_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&csi2_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1243,8 +1255,8 @@ static struct clk_branch camss_csi2rdi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_csi2rdi_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"csi2_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&csi2_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1260,8 +1272,8 @@ static struct clk_branch camss_csi3_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_csi3_ahb_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_ahb_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_ahb_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1276,8 +1288,8 @@ static struct clk_branch camss_csi3_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_csi3_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"csi3_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&csi3_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1293,8 +1305,8 @@ static struct clk_branch camss_csi3phy_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_csi3phy_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"csi3_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&csi3_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1310,8 +1322,8 @@ static struct clk_branch camss_csi3pix_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_csi3pix_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"csi3_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&csi3_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1327,8 +1339,8 @@ static struct clk_branch camss_csi3rdi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_csi3rdi_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"csi3_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&csi3_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1344,8 +1356,8 @@ static struct clk_branch camss_csi_vfe0_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_csi_vfe0_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"vfe0_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&vfe0_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1361,8 +1373,8 @@ static struct clk_branch camss_csi_vfe1_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_csi_vfe1_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"vfe1_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&vfe1_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1378,8 +1390,8 @@ static struct clk_branch camss_gp0_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_gp0_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"camss_gp0_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&camss_gp0_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1395,8 +1407,8 @@ static struct clk_branch camss_gp1_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_gp1_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"camss_gp1_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&camss_gp1_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1412,8 +1424,8 @@ static struct clk_branch camss_ispif_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_ispif_ahb_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_ahb_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_ahb_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1428,8 +1440,8 @@ static struct clk_branch camss_jpeg_jpeg0_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_jpeg_jpeg0_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"jpeg0_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&jpeg0_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1445,8 +1457,8 @@ static struct clk_branch camss_jpeg_jpeg1_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_jpeg_jpeg1_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"jpeg1_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&jpeg1_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1462,8 +1474,8 @@ static struct clk_branch camss_jpeg_jpeg2_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_jpeg_jpeg2_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"jpeg2_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&jpeg2_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1479,8 +1491,8 @@ static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_jpeg_jpeg_ahb_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_ahb_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_ahb_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1495,8 +1507,8 @@ static struct clk_branch camss_jpeg_jpeg_axi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_jpeg_jpeg_axi_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_axi_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_axi_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1511,8 +1523,8 @@ static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_jpeg_jpeg_ocmemnoc_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"ocmemnoc_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&ocmemnoc_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1528,8 +1540,8 @@ static struct clk_branch camss_mclk0_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_mclk0_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mclk0_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mclk0_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1545,8 +1557,8 @@ static struct clk_branch camss_mclk1_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_mclk1_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mclk1_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mclk1_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1562,8 +1574,8 @@ static struct clk_branch camss_mclk2_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_mclk2_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mclk2_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mclk2_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1579,8 +1591,8 @@ static struct clk_branch camss_mclk3_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_mclk3_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mclk3_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mclk3_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1596,8 +1608,8 @@ static struct clk_branch camss_micro_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_micro_ahb_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_ahb_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_ahb_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1612,8 +1624,8 @@ static struct clk_branch camss_phy0_csi0phytimer_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_phy0_csi0phytimer_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"csi0phytimer_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&csi0phytimer_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1629,8 +1641,8 @@ static struct clk_branch camss_phy1_csi1phytimer_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_phy1_csi1phytimer_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"csi1phytimer_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&csi1phytimer_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1646,8 +1658,8 @@ static struct clk_branch camss_phy2_csi2phytimer_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_phy2_csi2phytimer_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"csi2phytimer_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&csi2phytimer_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1663,8 +1675,8 @@ static struct clk_branch camss_top_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_top_ahb_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_ahb_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_ahb_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1679,8 +1691,8 @@ static struct clk_branch camss_vfe_cpp_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_vfe_cpp_ahb_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_ahb_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_ahb_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1695,8 +1707,8 @@ static struct clk_branch camss_vfe_cpp_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_vfe_cpp_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"cpp_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&cpp_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1712,8 +1724,8 @@ static struct clk_branch camss_vfe_vfe0_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_vfe_vfe0_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"vfe0_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&vfe0_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1729,8 +1741,8 @@ static struct clk_branch camss_vfe_vfe1_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_vfe_vfe1_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"vfe1_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&vfe1_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1746,8 +1758,8 @@ static struct clk_branch camss_vfe_vfe_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_vfe_vfe_ahb_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_ahb_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_ahb_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1762,8 +1774,8 @@ static struct clk_branch camss_vfe_vfe_axi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_vfe_vfe_axi_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_axi_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_axi_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1778,8 +1790,8 @@ static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "camss_vfe_vfe_ocmemnoc_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"ocmemnoc_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&ocmemnoc_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1795,8 +1807,8 @@ static struct clk_branch mdss_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "mdss_ahb_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_ahb_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_ahb_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1811,8 +1823,8 @@ static struct clk_branch mdss_axi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "mdss_axi_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_axi_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_axi_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1828,8 +1840,8 @@ static struct clk_branch mdss_byte0_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "mdss_byte0_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"byte0_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&byte0_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1845,8 +1857,8 @@ static struct clk_branch mdss_byte1_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "mdss_byte1_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"byte1_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&byte1_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1862,8 +1874,8 @@ static struct clk_branch mdss_edpaux_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "mdss_edpaux_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"edpaux_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&edpaux_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1879,8 +1891,8 @@ static struct clk_branch mdss_edplink_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "mdss_edplink_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"edplink_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&edplink_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1896,8 +1908,8 @@ static struct clk_branch mdss_edppixel_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "mdss_edppixel_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"edppixel_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&edppixel_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1913,8 +1925,8 @@ static struct clk_branch mdss_esc0_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "mdss_esc0_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"esc0_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&esc0_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1930,8 +1942,8 @@ static struct clk_branch mdss_esc1_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "mdss_esc1_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"esc1_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&esc1_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1947,8 +1959,8 @@ static struct clk_branch mdss_extpclk_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "mdss_extpclk_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"extpclk_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&extpclk_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1964,8 +1976,8 @@ static struct clk_branch mdss_hdmi_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "mdss_hdmi_ahb_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_ahb_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_ahb_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1980,8 +1992,8 @@ static struct clk_branch mdss_hdmi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "mdss_hdmi_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"hdmi_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&hdmi_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -1997,8 +2009,8 @@ static struct clk_branch mdss_mdp_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "mdss_mdp_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mdp_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mdp_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -2014,8 +2026,8 @@ static struct clk_branch mdss_mdp_lut_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "mdss_mdp_lut_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mdp_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mdp_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -2031,8 +2043,8 @@ static struct clk_branch mdss_pclk0_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "mdss_pclk0_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"pclk0_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&pclk0_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -2048,8 +2060,8 @@ static struct clk_branch mdss_pclk1_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "mdss_pclk1_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"pclk1_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&pclk1_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -2065,8 +2077,8 @@ static struct clk_branch mdss_vsync_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "mdss_vsync_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"vsync_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&vsync_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -2082,8 +2094,8 @@ static struct clk_branch mmss_misc_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "mmss_misc_ahb_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_ahb_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_ahb_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2098,8 +2110,8 @@ static struct clk_branch mmss_mmssnoc_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "mmss_mmssnoc_ahb_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_ahb_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_ahb_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2115,8 +2127,8 @@ static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "mmss_mmssnoc_bto_ahb_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_ahb_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_ahb_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2132,8 +2144,8 @@ static struct clk_branch mmss_mmssnoc_axi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "mmss_mmssnoc_axi_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_axi_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_axi_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > > @@ -2149,8 +2161,8 @@ static struct clk_branch mmss_s0_axi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "mmss_s0_axi_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_axi_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_axi_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2166,8 +2178,8 @@ static struct clk_branch ocmemcx_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "ocmemcx_ahb_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_ahb_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_ahb_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2182,8 +2194,8 @@ static struct clk_branch ocmemcx_ocmemnoc_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "ocmemcx_ocmemnoc_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"ocmemnoc_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&ocmemnoc_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -2199,8 +2211,8 @@ static struct clk_branch oxili_ocmemgx_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "oxili_ocmemgx_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"gfx3d_clk_src",
> > > +			.parent_data = (const struct clk_parent_data[]){
> > > +				{ .fw_name = "gfx3d_clk_src", .name = "gfx3d_clk_src" },
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -2216,8 +2228,8 @@ static struct clk_branch ocmemnoc_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "ocmemnoc_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"ocmemnoc_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&ocmemnoc_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -2233,8 +2245,8 @@ static struct clk_branch oxili_gfx3d_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "oxili_gfx3d_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"gfx3d_clk_src",
> > > +			.parent_data = (const struct clk_parent_data[]){
> > > +				{ .fw_name = "gfx3d_clk_src", .name = "gfx3d_clk_src" },
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -2250,8 +2262,8 @@ static struct clk_branch oxilicx_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "oxilicx_ahb_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_ahb_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_ahb_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2266,8 +2278,8 @@ static struct clk_branch oxilicx_axi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "oxilicx_axi_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_axi_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_axi_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2282,8 +2294,8 @@ static struct clk_branch venus0_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "venus0_ahb_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_ahb_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_ahb_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2298,8 +2310,8 @@ static struct clk_branch venus0_axi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "venus0_axi_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"mmss_axi_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&mmss_axi_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2314,8 +2326,8 @@ static struct clk_branch venus0_ocmemnoc_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "venus0_ocmemnoc_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"ocmemnoc_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&ocmemnoc_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > > @@ -2331,8 +2343,8 @@ static struct clk_branch venus0_vcodec0_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "venus0_vcodec0_clk",
> > > -			.parent_names = (const char *[]){
> > > -				"vcodec0_clk_src",
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&vcodec0_clk_src.clkr.hw
> > >  			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,