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* [PATCH v5 0/7] STM32 DSI HOST
@ 2017-07-03  8:41 ` Philippe CORNU
  0 siblings, 0 replies; 24+ messages in thread
From: Philippe CORNU @ 2017-07-03  8:41 UTC (permalink / raw)
  To: Alexandre Torgue, Thierry Reding, David Airlie, Maxime Coquelin,
	Russell King, Mark Rutland, Rob Herring, Arnd Bergmann,
	Benjamin Gaignard, Yannick Fertre, Neil Armstrong, Archit Taneja,
	Eric Anholt, Chris Zhong, Andrzej Hajda, Xinliang Liu,
	zourongrong, Xinwei Kong, Chen Feng, Mark Yao
  Cc: linux-arm-kernel, devicetree, Philippe Cornu, Fabien Dessenne,
	dri-devel, Mickael Reulier, Vincent Abriou, Gabriel Fernandez,
	Ludovic Barre

Version 5:
- bridge/synopsis/dw-mipi-dsi.c: Improve the direct call to panel
  bridge post_disable() & related comments (Archit Taneja)
- stm/ltdc.c: fix leak of pixel clock enable in some error
  paths (Eric Anholt)
- bindings/display/bridge/dw_mipi_dsi.txt: add pixel clock & remove
  "driver" (Rob Herring, Archit Taneja)
- bindings/display/st,stm32-ltdc.txt: remove "driver" (Rob Herring,
  Archit Taneja)

Version 4:
- bridge/synopsis/dw-mipi-dsi.c: Add panel-bridge support (-45 lines,
  but no so easy to do) and is_panel_bridge for a better clean up, add
  stm copyright/remove dpms_mode/remove drm_of.h/improve clk
  management/add mode_valid (thanks to comments of Archit Taneja), use
  "DesignWare" instead of "Designware (thanks to comments of Neil
  Armstrong)
- bridge/synopsis/Kconfig: Remove help section to hide it in menuconfig
  (thanks to comments of Archit Taneja)
- include/drm/bridge/dw_mipi_dsi.h: Remove drmP.h (thanks to comments
  of Archit Taneja)
- bindings/display/bridge/dw_mipi_dsi.txt: Improve optional property
  explanations (thanks to comments of Neil Armstrong)
- stm/ltdc.c: Add is_panel_bridge for a better clean up/remove
  drm_encoder_helper_add() (thanks to comments of Eric Anholt)
- stm/dw_mipi_dsi-stm.c: remove math64.h/use DRM_WARN/remove warnings
  (thanks to comments of Archit Taneja), minor alignment fix (thanks to
  comments of Neil Armstrong)
- bindings/display/st,stm32-ltdc.txt: use graph binding in the 
  example/improve ports usage doc (thanks to comments of Rob Herring),
  use "DSI" instead of "dsi" where relevant (thanks to comments of Neil
  Armstrong)

Version 3:
- stm/ltdc: Use panel-bridge (-170 lines), thanks to comments of Eric Anholt,
  Boris Brezillon, Archit Taneja & Andrzej Hajda.
- Synopsys dsi: Add dw_mipi_dsi.h (forgotten in v2), thanks to comments of
  Neil Armstrong.
- Synopsys dsi/dw-mipi-dsi.c: add dw_mipi_dsi_dphy_init() &
  dw_mipi_dsi_dphy_enable() to better manage DW phy-dedicated regs, remove
  dw_mipi_dsi_mode enum, remove stm32 patch for lpm, remove pllref (manage in
  the vendor phy) thanks to comments of Archit Taneja. Add mode_flags to phy
  parameters to better adjust lane mbps according to dsi burst and non burst
  modes todos in caps.
- stm/dw_mipi_dsi-stm.c: Add pllref management.
- dt-bindings/display/stm: Split dt-bindings patch in two (parent node
  removal/ dsi), add required nodes (port & panel/bridge), updates thanks to
  comments of Rob Herring.
- dt-bindings/display/Synopsys dsi: remove port as part of the vendor
  documentation, add panel/bridge node, update dt-bindings thanks to comments
  of Rob Herring.
- Add more people from Hisilicon & Rockchip.

Version 2:
- Add a generic Synopsys DesignWare MIPI DSI bridge driver following
  comments from Neil Armstrong & Archit Taneja.
- Use drm_of_find_panel_or_bridge() thanks to Eric Anholt comments
- Update dt-bindings thanks to Rob Herring comments

Version 1:
- Initial commit

The purpose of this set of patches is to add the mipi dsi host driver
to the stm32 family.

This mipi dsi host driver is based on the Rockchip version of the
Synopsys Designware mipi dsi driver (rockchip/dw-mipi-dsi.c)
modified for the stm32 family:
    - replace Rockchip digital & phy specific extensions with stm32's ones.
    - add a bridge

Philippe CORNU (7):
  drm/stm: ltdc: Fix leak of px clk enable in some error paths
  drm/stm: ltdc: Add panel-bridge support
  dt-bindings: display: Add Synopsys DW MIPI DSI host controller
  drm/bridge/synopsys: Add MIPI DSI host controller bridge
  dt-bindings: display: stm32: remove st-display-subsystem parent node
    requirement
  dt-bindings: display: stm32: Add DSI controller
  drm/stm: Add STM32 DSI controller driver

 .../bindings/display/bridge/dw_mipi_dsi.txt        |  32 +
 .../devicetree/bindings/display/st,stm32-ltdc.txt  | 105 ++-
 drivers/gpu/drm/bridge/synopsys/Kconfig            |   6 +
 drivers/gpu/drm/bridge/synopsys/Makefile           |   2 +
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c      | 979 +++++++++++++++++++++
 drivers/gpu/drm/stm/Kconfig                        |   9 +-
 drivers/gpu/drm/stm/Makefile                       |   2 +
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c              | 352 ++++++++
 drivers/gpu/drm/stm/ltdc.c                         | 220 +----
 drivers/gpu/drm/stm/ltdc.h                         |   3 +-
 include/drm/bridge/dw_mipi_dsi.h                   |  39 +
 11 files changed, 1566 insertions(+), 183 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
 create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
 create mode 100644 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
 create mode 100644 include/drm/bridge/dw_mipi_dsi.h

-- 
1.9.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 24+ messages in thread
* [PATCH v5 0/7] STM32 DSI HOST
@ 2017-07-03  8:41 ` Philippe CORNU
  0 siblings, 0 replies; 24+ messages in thread
From: Philippe CORNU @ 2017-07-03  8:41 UTC (permalink / raw)
  To: linux-arm-kernel

Version 5:
- bridge/synopsis/dw-mipi-dsi.c: Improve the direct call to panel
  bridge post_disable() & related comments (Archit Taneja)
- stm/ltdc.c: fix leak of pixel clock enable in some error
  paths (Eric Anholt)
- bindings/display/bridge/dw_mipi_dsi.txt: add pixel clock & remove
  "driver" (Rob Herring, Archit Taneja)
- bindings/display/st,stm32-ltdc.txt: remove "driver" (Rob Herring,
  Archit Taneja)

Version 4:
- bridge/synopsis/dw-mipi-dsi.c: Add panel-bridge support (-45 lines,
  but no so easy to do) and is_panel_bridge for a better clean up, add
  stm copyright/remove dpms_mode/remove drm_of.h/improve clk
  management/add mode_valid (thanks to comments of Archit Taneja), use
  "DesignWare" instead of "Designware (thanks to comments of Neil
  Armstrong)
- bridge/synopsis/Kconfig: Remove help section to hide it in menuconfig
  (thanks to comments of Archit Taneja)
- include/drm/bridge/dw_mipi_dsi.h: Remove drmP.h (thanks to comments
  of Archit Taneja)
- bindings/display/bridge/dw_mipi_dsi.txt: Improve optional property
  explanations (thanks to comments of Neil Armstrong)
- stm/ltdc.c: Add is_panel_bridge for a better clean up/remove
  drm_encoder_helper_add() (thanks to comments of Eric Anholt)
- stm/dw_mipi_dsi-stm.c: remove math64.h/use DRM_WARN/remove warnings
  (thanks to comments of Archit Taneja), minor alignment fix (thanks to
  comments of Neil Armstrong)
- bindings/display/st,stm32-ltdc.txt: use graph binding in the 
  example/improve ports usage doc (thanks to comments of Rob Herring),
  use "DSI" instead of "dsi" where relevant (thanks to comments of Neil
  Armstrong)

Version 3:
- stm/ltdc: Use panel-bridge (-170 lines), thanks to comments of Eric Anholt,
  Boris Brezillon, Archit Taneja & Andrzej Hajda.
- Synopsys dsi: Add dw_mipi_dsi.h (forgotten in v2), thanks to comments of
  Neil Armstrong.
- Synopsys dsi/dw-mipi-dsi.c: add dw_mipi_dsi_dphy_init() &
  dw_mipi_dsi_dphy_enable() to better manage DW phy-dedicated regs, remove
  dw_mipi_dsi_mode enum, remove stm32 patch for lpm, remove pllref (manage in
  the vendor phy) thanks to comments of Archit Taneja. Add mode_flags to phy
  parameters to better adjust lane mbps according to dsi burst and non burst
  modes todos in caps.
- stm/dw_mipi_dsi-stm.c: Add pllref management.
- dt-bindings/display/stm: Split dt-bindings patch in two (parent node
  removal/ dsi), add required nodes (port & panel/bridge), updates thanks to
  comments of Rob Herring.
- dt-bindings/display/Synopsys dsi: remove port as part of the vendor
  documentation, add panel/bridge node, update dt-bindings thanks to comments
  of Rob Herring.
- Add more people from Hisilicon & Rockchip.

Version 2:
- Add a generic Synopsys DesignWare MIPI DSI bridge driver following
  comments from Neil Armstrong & Archit Taneja.
- Use drm_of_find_panel_or_bridge() thanks to Eric Anholt comments
- Update dt-bindings thanks to Rob Herring comments

Version 1:
- Initial commit

The purpose of this set of patches is to add the mipi dsi host driver
to the stm32 family.

This mipi dsi host driver is based on the Rockchip version of the
Synopsys Designware mipi dsi driver (rockchip/dw-mipi-dsi.c)
modified for the stm32 family:
    - replace Rockchip digital & phy specific extensions with stm32's ones.
    - add a bridge

Philippe CORNU (7):
  drm/stm: ltdc: Fix leak of px clk enable in some error paths
  drm/stm: ltdc: Add panel-bridge support
  dt-bindings: display: Add Synopsys DW MIPI DSI host controller
  drm/bridge/synopsys: Add MIPI DSI host controller bridge
  dt-bindings: display: stm32: remove st-display-subsystem parent node
    requirement
  dt-bindings: display: stm32: Add DSI controller
  drm/stm: Add STM32 DSI controller driver

 .../bindings/display/bridge/dw_mipi_dsi.txt        |  32 +
 .../devicetree/bindings/display/st,stm32-ltdc.txt  | 105 ++-
 drivers/gpu/drm/bridge/synopsys/Kconfig            |   6 +
 drivers/gpu/drm/bridge/synopsys/Makefile           |   2 +
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c      | 979 +++++++++++++++++++++
 drivers/gpu/drm/stm/Kconfig                        |   9 +-
 drivers/gpu/drm/stm/Makefile                       |   2 +
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c              | 352 ++++++++
 drivers/gpu/drm/stm/ltdc.c                         | 220 +----
 drivers/gpu/drm/stm/ltdc.h                         |   3 +-
 include/drm/bridge/dw_mipi_dsi.h                   |  39 +
 11 files changed, 1566 insertions(+), 183 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
 create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
 create mode 100644 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
 create mode 100644 include/drm/bridge/dw_mipi_dsi.h

-- 
1.9.1

^ permalink raw reply	[flat|nested] 24+ messages in thread
* [PATCH v5 1/7] drm/stm: ltdc: Fix leak of px clk enable in some error paths
  2017-07-03  8:41 ` Philippe CORNU
@ 2017-07-03  8:41   ` Philippe CORNU
  -1 siblings, 0 replies; 24+ messages in thread
From: Philippe CORNU @ 2017-07-03  8:41 UTC (permalink / raw)
  To: Alexandre Torgue, Thierry Reding, David Airlie, Maxime Coquelin,
	Russell King, Mark Rutland, Rob Herring, Arnd Bergmann,
	Benjamin Gaignard, Yannick Fertre, Neil Armstrong, Archit Taneja,
	Eric Anholt, Chris Zhong, Andrzej Hajda, Xinliang Liu,
	zourongrong, Xinwei Kong, Chen Feng, Mark Yao
  Cc: linux-arm-kernel, devicetree, Philippe Cornu, Fabien Dessenne,
	dri-devel, Mickael Reulier, Vincent Abriou, Gabriel Fernandez,
	Ludovic Barre

The pixel clock gets enabled early during init, since it's required
in order to read registers. This pixel clock must be disabled if
errors during this init phase.

Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Philippe Cornu <philippe.cornu@st.com>
---
 drivers/gpu/drm/stm/ltdc.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 5331760..7f64d5a 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -1045,13 +1045,15 @@ int ltdc_load(struct drm_device *ddev)
 
 	if (of_address_to_resource(np, 0, &res)) {
 		DRM_ERROR("Unable to get resource\n");
-		return -ENODEV;
+		ret = -ENODEV;
+		goto err;
 	}
 
 	ldev->regs = devm_ioremap_resource(dev, &res);
 	if (IS_ERR(ldev->regs)) {
 		DRM_ERROR("Unable to get ltdc registers\n");
-		return PTR_ERR(ldev->regs);
+		ret = PTR_ERR(ldev->regs);
+		goto err;
 	}
 
 	for (i = 0; i < MAX_IRQ; i++) {
@@ -1064,7 +1066,7 @@ int ltdc_load(struct drm_device *ddev)
 						dev_name(dev), ddev);
 		if (ret) {
 			DRM_ERROR("Failed to register LTDC interrupt\n");
-			return ret;
+			goto err;
 		}
 	}
 
@@ -1079,7 +1081,7 @@ int ltdc_load(struct drm_device *ddev)
 	if (ret) {
 		DRM_ERROR("hardware identifier (0x%08x) not supported!\n",
 			  ldev->caps.hw_version);
-		return ret;
+		goto err;
 	}
 
 	DRM_INFO("ltdc hw version 0x%08x - ready\n", ldev->caps.hw_version);
-- 
1.9.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v5 1/7] drm/stm: ltdc: Fix leak of px clk enable in some error paths
@ 2017-07-03  8:41   ` Philippe CORNU
  0 siblings, 0 replies; 24+ messages in thread
From: Philippe CORNU @ 2017-07-03  8:41 UTC (permalink / raw)
  To: linux-arm-kernel

The pixel clock gets enabled early during init, since it's required
in order to read registers. This pixel clock must be disabled if
errors during this init phase.

Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Philippe Cornu <philippe.cornu@st.com>
---
 drivers/gpu/drm/stm/ltdc.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 5331760..7f64d5a 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -1045,13 +1045,15 @@ int ltdc_load(struct drm_device *ddev)
 
 	if (of_address_to_resource(np, 0, &res)) {
 		DRM_ERROR("Unable to get resource\n");
-		return -ENODEV;
+		ret = -ENODEV;
+		goto err;
 	}
 
 	ldev->regs = devm_ioremap_resource(dev, &res);
 	if (IS_ERR(ldev->regs)) {
 		DRM_ERROR("Unable to get ltdc registers\n");
-		return PTR_ERR(ldev->regs);
+		ret = PTR_ERR(ldev->regs);
+		goto err;
 	}
 
 	for (i = 0; i < MAX_IRQ; i++) {
@@ -1064,7 +1066,7 @@ int ltdc_load(struct drm_device *ddev)
 						dev_name(dev), ddev);
 		if (ret) {
 			DRM_ERROR("Failed to register LTDC interrupt\n");
-			return ret;
+			goto err;
 		}
 	}
 
@@ -1079,7 +1081,7 @@ int ltdc_load(struct drm_device *ddev)
 	if (ret) {
 		DRM_ERROR("hardware identifier (0x%08x) not supported!\n",
 			  ldev->caps.hw_version);
-		return ret;
+		goto err;
 	}
 
 	DRM_INFO("ltdc hw version 0x%08x - ready\n", ldev->caps.hw_version);
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v5 2/7] drm/stm: ltdc: Add panel-bridge support
  2017-07-03  8:41 ` Philippe CORNU
@ 2017-07-03  8:41   ` Philippe CORNU
  -1 siblings, 0 replies; 24+ messages in thread
From: Philippe CORNU @ 2017-07-03  8:41 UTC (permalink / raw)
  To: Alexandre Torgue, Thierry Reding, David Airlie, Maxime Coquelin,
	Russell King, Mark Rutland, Rob Herring, Arnd Bergmann,
	Benjamin Gaignard, Yannick Fertre, Neil Armstrong, Archit Taneja,
	Eric Anholt, Chris Zhong, Andrzej Hajda, Xinliang Liu,
	zourongrong, Xinwei Kong, Chen Feng, Mark Yao
  Cc: linux-arm-kernel, devicetree, Philippe Cornu, Fabien Dessenne,
	dri-devel, Mickael Reulier, Vincent Abriou, Gabriel Fernandez,
	Ludovic Barre

Add the panel-bridge support for both panels & bridges (used by DSI host &
HDMI/LVDS bridges).

Signed-off-by: Philippe CORNU <philippe.cornu@st.com>
Reviewed-by: Archit Taneja <architt@codeaurora.org>
---
 drivers/gpu/drm/stm/Kconfig |   2 +-
 drivers/gpu/drm/stm/ltdc.c  | 210 ++++++++------------------------------------
 drivers/gpu/drm/stm/ltdc.h  |   3 +-
 3 files changed, 38 insertions(+), 177 deletions(-)

diff --git a/drivers/gpu/drm/stm/Kconfig b/drivers/gpu/drm/stm/Kconfig
index 2c4817f..4b88223 100644
--- a/drivers/gpu/drm/stm/Kconfig
+++ b/drivers/gpu/drm/stm/Kconfig
@@ -4,7 +4,7 @@ config DRM_STM
 	select DRM_KMS_HELPER
 	select DRM_GEM_CMA_HELPER
 	select DRM_KMS_CMA_HELPER
-	select DRM_PANEL
+	select DRM_PANEL_BRIDGE
 	select VIDEOMODE_HELPERS
 	select FB_PROVIDE_GET_FB_UNMAPPED_AREA
 	default y
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 7f64d5a..e46b427 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -21,7 +21,7 @@
 #include <drm/drm_fb_cma_helper.h>
 #include <drm/drm_gem_cma_helper.h>
 #include <drm/drm_of.h>
-#include <drm/drm_panel.h>
+#include <drm/drm_bridge.h>
 #include <drm/drm_plane_helper.h>
 
 #include <video/videomode.h>
@@ -269,11 +269,6 @@ static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc)
 	return (struct ltdc_device *)enc->dev->dev_private;
 }
 
-static inline struct ltdc_device *connector_to_ltdc(struct drm_connector *con)
-{
-	return (struct ltdc_device *)con->dev->dev_private;
-}
-
 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt)
 {
 	enum ltdc_pix_fmt pf;
@@ -815,130 +810,35 @@ static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
  * DRM_ENCODER
  */
 
-static void ltdc_rgb_encoder_enable(struct drm_encoder *encoder)
-{
-	struct ltdc_device *ldev = encoder_to_ltdc(encoder);
-
-	DRM_DEBUG_DRIVER("\n");
-
-	drm_panel_prepare(ldev->panel);
-	drm_panel_enable(ldev->panel);
-}
-
-static void ltdc_rgb_encoder_disable(struct drm_encoder *encoder)
-{
-	struct ltdc_device *ldev = encoder_to_ltdc(encoder);
-
-	DRM_DEBUG_DRIVER("\n");
-
-	drm_panel_disable(ldev->panel);
-	drm_panel_unprepare(ldev->panel);
-}
-
-static const struct drm_encoder_helper_funcs ltdc_rgb_encoder_helper_funcs = {
-	.enable = ltdc_rgb_encoder_enable,
-	.disable = ltdc_rgb_encoder_disable,
-};
-
-static const struct drm_encoder_funcs ltdc_rgb_encoder_funcs = {
+static const struct drm_encoder_funcs ltdc_encoder_funcs = {
 	.destroy = drm_encoder_cleanup,
 };
 
-static struct drm_encoder *ltdc_rgb_encoder_create(struct drm_device *ddev)
+static int ltdc_encoder_init(struct drm_device *ddev)
 {
+	struct ltdc_device *ldev = ddev->dev_private;
 	struct drm_encoder *encoder;
+	int ret;
 
 	encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL);
 	if (!encoder)
-		return NULL;
+		return -ENOMEM;
 
 	encoder->possible_crtcs = CRTC_MASK;
 	encoder->possible_clones = 0; /* No cloning support */
 
-	drm_encoder_init(ddev, encoder, &ltdc_rgb_encoder_funcs,
+	drm_encoder_init(ddev, encoder, &ltdc_encoder_funcs,
 			 DRM_MODE_ENCODER_DPI, NULL);
 
-	drm_encoder_helper_add(encoder, &ltdc_rgb_encoder_helper_funcs);
-
-	DRM_DEBUG_DRIVER("RGB encoder:%d created\n", encoder->base.id);
-
-	return encoder;
-}
-
-/*
- * DRM_CONNECTOR
- */
-
-static int ltdc_rgb_connector_get_modes(struct drm_connector *connector)
-{
-	struct drm_device *ddev = connector->dev;
-	struct ltdc_device *ldev = ddev->dev_private;
-	int ret = 0;
-
-	DRM_DEBUG_DRIVER("\n");
-
-	if (ldev->panel)
-		ret = drm_panel_get_modes(ldev->panel);
-
-	return ret < 0 ? 0 : ret;
-}
-
-static struct drm_connector_helper_funcs ltdc_rgb_connector_helper_funcs = {
-	.get_modes = ltdc_rgb_connector_get_modes,
-};
-
-static enum drm_connector_status
-ltdc_rgb_connector_detect(struct drm_connector *connector, bool force)
-{
-	struct ltdc_device *ldev = connector_to_ltdc(connector);
-
-	return ldev->panel ? connector_status_connected :
-	       connector_status_disconnected;
-}
-
-static void ltdc_rgb_connector_destroy(struct drm_connector *connector)
-{
-	DRM_DEBUG_DRIVER("\n");
-
-	drm_connector_unregister(connector);
-	drm_connector_cleanup(connector);
-}
-
-static const struct drm_connector_funcs ltdc_rgb_connector_funcs = {
-	.dpms = drm_atomic_helper_connector_dpms,
-	.fill_modes = drm_helper_probe_single_connector_modes,
-	.detect = ltdc_rgb_connector_detect,
-	.destroy = ltdc_rgb_connector_destroy,
-	.reset = drm_atomic_helper_connector_reset,
-	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
-	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-};
-
-struct drm_connector *ltdc_rgb_connector_create(struct drm_device *ddev)
-{
-	struct drm_connector *connector;
-	int err;
-
-	connector = devm_kzalloc(ddev->dev, sizeof(*connector), GFP_KERNEL);
-	if (!connector) {
-		DRM_ERROR("Failed to allocate connector\n");
-		return NULL;
-	}
-
-	connector->polled = DRM_CONNECTOR_POLL_HPD;
-
-	err = drm_connector_init(ddev, connector, &ltdc_rgb_connector_funcs,
-				 DRM_MODE_CONNECTOR_DPI);
-	if (err) {
-		DRM_ERROR("Failed to initialize connector\n");
-		return NULL;
+	ret = drm_bridge_attach(encoder, ldev->bridge, NULL);
+	if (ret) {
+		drm_encoder_cleanup(encoder);
+		return -EINVAL;
 	}
 
-	drm_connector_helper_add(connector, &ltdc_rgb_connector_helper_funcs);
-
-	DRM_DEBUG_DRIVER("RGB connector:%d created\n", connector->base.id);
+	DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id);
 
-	return connector;
+	return 0;
 }
 
 static int ltdc_get_caps(struct drm_device *ddev)
@@ -974,49 +874,14 @@ static int ltdc_get_caps(struct drm_device *ddev)
 	return 0;
 }
 
-static struct drm_panel *ltdc_get_panel(struct drm_device *ddev)
-{
-	struct device *dev = ddev->dev;
-	struct device_node *np = dev->of_node;
-	struct device_node *entity, *port = NULL;
-	struct drm_panel *panel = NULL;
-
-	DRM_DEBUG_DRIVER("\n");
-
-	/*
-	 * Parse ltdc node to get remote port and find RGB panel / HDMI slave
-	 * If a dsi or a bridge (hdmi, lvds...) is connected to ltdc,
-	 * a remote port & RGB panel will not be found.
-	 */
-	for_each_endpoint_of_node(np, entity) {
-		if (!of_device_is_available(entity))
-			continue;
-
-		port = of_graph_get_remote_port_parent(entity);
-		if (port) {
-			panel = of_drm_find_panel(port);
-			of_node_put(port);
-			if (panel) {
-				DRM_DEBUG_DRIVER("remote panel %s\n",
-						 port->full_name);
-			} else {
-				DRM_DEBUG_DRIVER("panel missing\n");
-				of_node_put(entity);
-			}
-		}
-	}
-
-	return panel;
-}
-
 int ltdc_load(struct drm_device *ddev)
 {
 	struct platform_device *pdev = to_platform_device(ddev->dev);
 	struct ltdc_device *ldev = ddev->dev_private;
 	struct device *dev = ddev->dev;
 	struct device_node *np = dev->of_node;
-	struct drm_encoder *encoder;
-	struct drm_connector *connector = NULL;
+	struct drm_bridge *bridge;
+	struct drm_panel *panel;
 	struct drm_crtc *crtc;
 	struct reset_control *rstc;
 	struct resource res;
@@ -1024,9 +889,9 @@ int ltdc_load(struct drm_device *ddev)
 
 	DRM_DEBUG_DRIVER("\n");
 
-	ldev->panel = ltdc_get_panel(ddev);
-	if (!ldev->panel)
-		return -EPROBE_DEFER;
+	ret = drm_of_find_panel_or_bridge(np, 0, 0, &panel, &bridge);
+	if (ret)
+		return ret;
 
 	rstc = of_reset_control_get(np, NULL);
 
@@ -1086,28 +951,22 @@ int ltdc_load(struct drm_device *ddev)
 
 	DRM_INFO("ltdc hw version 0x%08x - ready\n", ldev->caps.hw_version);
 
-	if (ldev->panel) {
-		encoder = ltdc_rgb_encoder_create(ddev);
-		if (!encoder) {
-			DRM_ERROR("Failed to create RGB encoder\n");
-			ret = -EINVAL;
-			goto err;
-		}
-
-		connector = ltdc_rgb_connector_create(ddev);
-		if (!connector) {
-			DRM_ERROR("Failed to create RGB connector\n");
-			ret = -EINVAL;
+	if (panel) {
+		bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DPI);
+		if (IS_ERR(bridge)) {
+			DRM_ERROR("Failed to create panel-bridge\n");
+			ret = PTR_ERR(bridge);
 			goto err;
 		}
+		ldev->is_panel_bridge = true;
+	}
 
-		ret = drm_mode_connector_attach_encoder(connector, encoder);
-		if (ret) {
-			DRM_ERROR("Failed to attach connector to encoder\n");
-			goto err;
-		}
+	ldev->bridge = bridge;
 
-		drm_panel_attach(ldev->panel, connector);
+	ret = ltdc_encoder_init(ddev);
+	if (ret) {
+		DRM_ERROR("Failed to init encoder\n");
+		goto err;
 	}
 
 	crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL);
@@ -1133,9 +992,10 @@ int ltdc_load(struct drm_device *ddev)
 	ddev->irq_enabled = 1;
 
 	return 0;
+
 err:
-	if (ldev->panel)
-		drm_panel_detach(ldev->panel);
+	if (ldev->is_panel_bridge)
+		drm_panel_bridge_remove(bridge);
 
 	clk_disable_unprepare(ldev->pixel_clk);
 
@@ -1148,8 +1008,8 @@ void ltdc_unload(struct drm_device *ddev)
 
 	DRM_DEBUG_DRIVER("\n");
 
-	if (ldev->panel)
-		drm_panel_detach(ldev->panel);
+	if (ldev->is_panel_bridge)
+		drm_panel_bridge_remove(ldev->bridge);
 
 	clk_disable_unprepare(ldev->pixel_clk);
 }
diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
index d7a9c73..d9e899d 100644
--- a/drivers/gpu/drm/stm/ltdc.h
+++ b/drivers/gpu/drm/stm/ltdc.h
@@ -24,7 +24,8 @@ struct ltdc_device {
 	struct drm_fbdev_cma *fbdev;
 	void __iomem *regs;
 	struct clk *pixel_clk;	/* lcd pixel clock */
-	struct drm_panel *panel;
+	struct drm_bridge *bridge;
+	bool is_panel_bridge;
 	struct mutex err_lock;	/* protecting error_status */
 	struct ltdc_caps caps;
 	u32 clut[256];		/* color look up table */
-- 
1.9.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v5 2/7] drm/stm: ltdc: Add panel-bridge support
@ 2017-07-03  8:41   ` Philippe CORNU
  0 siblings, 0 replies; 24+ messages in thread
From: Philippe CORNU @ 2017-07-03  8:41 UTC (permalink / raw)
  To: linux-arm-kernel

Add the panel-bridge support for both panels & bridges (used by DSI host &
HDMI/LVDS bridges).

Signed-off-by: Philippe CORNU <philippe.cornu@st.com>
Reviewed-by: Archit Taneja <architt@codeaurora.org>
---
 drivers/gpu/drm/stm/Kconfig |   2 +-
 drivers/gpu/drm/stm/ltdc.c  | 210 ++++++++------------------------------------
 drivers/gpu/drm/stm/ltdc.h  |   3 +-
 3 files changed, 38 insertions(+), 177 deletions(-)

diff --git a/drivers/gpu/drm/stm/Kconfig b/drivers/gpu/drm/stm/Kconfig
index 2c4817f..4b88223 100644
--- a/drivers/gpu/drm/stm/Kconfig
+++ b/drivers/gpu/drm/stm/Kconfig
@@ -4,7 +4,7 @@ config DRM_STM
 	select DRM_KMS_HELPER
 	select DRM_GEM_CMA_HELPER
 	select DRM_KMS_CMA_HELPER
-	select DRM_PANEL
+	select DRM_PANEL_BRIDGE
 	select VIDEOMODE_HELPERS
 	select FB_PROVIDE_GET_FB_UNMAPPED_AREA
 	default y
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 7f64d5a..e46b427 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -21,7 +21,7 @@
 #include <drm/drm_fb_cma_helper.h>
 #include <drm/drm_gem_cma_helper.h>
 #include <drm/drm_of.h>
-#include <drm/drm_panel.h>
+#include <drm/drm_bridge.h>
 #include <drm/drm_plane_helper.h>
 
 #include <video/videomode.h>
@@ -269,11 +269,6 @@ static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc)
 	return (struct ltdc_device *)enc->dev->dev_private;
 }
 
-static inline struct ltdc_device *connector_to_ltdc(struct drm_connector *con)
-{
-	return (struct ltdc_device *)con->dev->dev_private;
-}
-
 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt)
 {
 	enum ltdc_pix_fmt pf;
@@ -815,130 +810,35 @@ static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
  * DRM_ENCODER
  */
 
-static void ltdc_rgb_encoder_enable(struct drm_encoder *encoder)
-{
-	struct ltdc_device *ldev = encoder_to_ltdc(encoder);
-
-	DRM_DEBUG_DRIVER("\n");
-
-	drm_panel_prepare(ldev->panel);
-	drm_panel_enable(ldev->panel);
-}
-
-static void ltdc_rgb_encoder_disable(struct drm_encoder *encoder)
-{
-	struct ltdc_device *ldev = encoder_to_ltdc(encoder);
-
-	DRM_DEBUG_DRIVER("\n");
-
-	drm_panel_disable(ldev->panel);
-	drm_panel_unprepare(ldev->panel);
-}
-
-static const struct drm_encoder_helper_funcs ltdc_rgb_encoder_helper_funcs = {
-	.enable = ltdc_rgb_encoder_enable,
-	.disable = ltdc_rgb_encoder_disable,
-};
-
-static const struct drm_encoder_funcs ltdc_rgb_encoder_funcs = {
+static const struct drm_encoder_funcs ltdc_encoder_funcs = {
 	.destroy = drm_encoder_cleanup,
 };
 
-static struct drm_encoder *ltdc_rgb_encoder_create(struct drm_device *ddev)
+static int ltdc_encoder_init(struct drm_device *ddev)
 {
+	struct ltdc_device *ldev = ddev->dev_private;
 	struct drm_encoder *encoder;
+	int ret;
 
 	encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL);
 	if (!encoder)
-		return NULL;
+		return -ENOMEM;
 
 	encoder->possible_crtcs = CRTC_MASK;
 	encoder->possible_clones = 0; /* No cloning support */
 
-	drm_encoder_init(ddev, encoder, &ltdc_rgb_encoder_funcs,
+	drm_encoder_init(ddev, encoder, &ltdc_encoder_funcs,
 			 DRM_MODE_ENCODER_DPI, NULL);
 
-	drm_encoder_helper_add(encoder, &ltdc_rgb_encoder_helper_funcs);
-
-	DRM_DEBUG_DRIVER("RGB encoder:%d created\n", encoder->base.id);
-
-	return encoder;
-}
-
-/*
- * DRM_CONNECTOR
- */
-
-static int ltdc_rgb_connector_get_modes(struct drm_connector *connector)
-{
-	struct drm_device *ddev = connector->dev;
-	struct ltdc_device *ldev = ddev->dev_private;
-	int ret = 0;
-
-	DRM_DEBUG_DRIVER("\n");
-
-	if (ldev->panel)
-		ret = drm_panel_get_modes(ldev->panel);
-
-	return ret < 0 ? 0 : ret;
-}
-
-static struct drm_connector_helper_funcs ltdc_rgb_connector_helper_funcs = {
-	.get_modes = ltdc_rgb_connector_get_modes,
-};
-
-static enum drm_connector_status
-ltdc_rgb_connector_detect(struct drm_connector *connector, bool force)
-{
-	struct ltdc_device *ldev = connector_to_ltdc(connector);
-
-	return ldev->panel ? connector_status_connected :
-	       connector_status_disconnected;
-}
-
-static void ltdc_rgb_connector_destroy(struct drm_connector *connector)
-{
-	DRM_DEBUG_DRIVER("\n");
-
-	drm_connector_unregister(connector);
-	drm_connector_cleanup(connector);
-}
-
-static const struct drm_connector_funcs ltdc_rgb_connector_funcs = {
-	.dpms = drm_atomic_helper_connector_dpms,
-	.fill_modes = drm_helper_probe_single_connector_modes,
-	.detect = ltdc_rgb_connector_detect,
-	.destroy = ltdc_rgb_connector_destroy,
-	.reset = drm_atomic_helper_connector_reset,
-	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
-	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-};
-
-struct drm_connector *ltdc_rgb_connector_create(struct drm_device *ddev)
-{
-	struct drm_connector *connector;
-	int err;
-
-	connector = devm_kzalloc(ddev->dev, sizeof(*connector), GFP_KERNEL);
-	if (!connector) {
-		DRM_ERROR("Failed to allocate connector\n");
-		return NULL;
-	}
-
-	connector->polled = DRM_CONNECTOR_POLL_HPD;
-
-	err = drm_connector_init(ddev, connector, &ltdc_rgb_connector_funcs,
-				 DRM_MODE_CONNECTOR_DPI);
-	if (err) {
-		DRM_ERROR("Failed to initialize connector\n");
-		return NULL;
+	ret = drm_bridge_attach(encoder, ldev->bridge, NULL);
+	if (ret) {
+		drm_encoder_cleanup(encoder);
+		return -EINVAL;
 	}
 
-	drm_connector_helper_add(connector, &ltdc_rgb_connector_helper_funcs);
-
-	DRM_DEBUG_DRIVER("RGB connector:%d created\n", connector->base.id);
+	DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id);
 
-	return connector;
+	return 0;
 }
 
 static int ltdc_get_caps(struct drm_device *ddev)
@@ -974,49 +874,14 @@ static int ltdc_get_caps(struct drm_device *ddev)
 	return 0;
 }
 
-static struct drm_panel *ltdc_get_panel(struct drm_device *ddev)
-{
-	struct device *dev = ddev->dev;
-	struct device_node *np = dev->of_node;
-	struct device_node *entity, *port = NULL;
-	struct drm_panel *panel = NULL;
-
-	DRM_DEBUG_DRIVER("\n");
-
-	/*
-	 * Parse ltdc node to get remote port and find RGB panel / HDMI slave
-	 * If a dsi or a bridge (hdmi, lvds...) is connected to ltdc,
-	 * a remote port & RGB panel will not be found.
-	 */
-	for_each_endpoint_of_node(np, entity) {
-		if (!of_device_is_available(entity))
-			continue;
-
-		port = of_graph_get_remote_port_parent(entity);
-		if (port) {
-			panel = of_drm_find_panel(port);
-			of_node_put(port);
-			if (panel) {
-				DRM_DEBUG_DRIVER("remote panel %s\n",
-						 port->full_name);
-			} else {
-				DRM_DEBUG_DRIVER("panel missing\n");
-				of_node_put(entity);
-			}
-		}
-	}
-
-	return panel;
-}
-
 int ltdc_load(struct drm_device *ddev)
 {
 	struct platform_device *pdev = to_platform_device(ddev->dev);
 	struct ltdc_device *ldev = ddev->dev_private;
 	struct device *dev = ddev->dev;
 	struct device_node *np = dev->of_node;
-	struct drm_encoder *encoder;
-	struct drm_connector *connector = NULL;
+	struct drm_bridge *bridge;
+	struct drm_panel *panel;
 	struct drm_crtc *crtc;
 	struct reset_control *rstc;
 	struct resource res;
@@ -1024,9 +889,9 @@ int ltdc_load(struct drm_device *ddev)
 
 	DRM_DEBUG_DRIVER("\n");
 
-	ldev->panel = ltdc_get_panel(ddev);
-	if (!ldev->panel)
-		return -EPROBE_DEFER;
+	ret = drm_of_find_panel_or_bridge(np, 0, 0, &panel, &bridge);
+	if (ret)
+		return ret;
 
 	rstc = of_reset_control_get(np, NULL);
 
@@ -1086,28 +951,22 @@ int ltdc_load(struct drm_device *ddev)
 
 	DRM_INFO("ltdc hw version 0x%08x - ready\n", ldev->caps.hw_version);
 
-	if (ldev->panel) {
-		encoder = ltdc_rgb_encoder_create(ddev);
-		if (!encoder) {
-			DRM_ERROR("Failed to create RGB encoder\n");
-			ret = -EINVAL;
-			goto err;
-		}
-
-		connector = ltdc_rgb_connector_create(ddev);
-		if (!connector) {
-			DRM_ERROR("Failed to create RGB connector\n");
-			ret = -EINVAL;
+	if (panel) {
+		bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DPI);
+		if (IS_ERR(bridge)) {
+			DRM_ERROR("Failed to create panel-bridge\n");
+			ret = PTR_ERR(bridge);
 			goto err;
 		}
+		ldev->is_panel_bridge = true;
+	}
 
-		ret = drm_mode_connector_attach_encoder(connector, encoder);
-		if (ret) {
-			DRM_ERROR("Failed to attach connector to encoder\n");
-			goto err;
-		}
+	ldev->bridge = bridge;
 
-		drm_panel_attach(ldev->panel, connector);
+	ret = ltdc_encoder_init(ddev);
+	if (ret) {
+		DRM_ERROR("Failed to init encoder\n");
+		goto err;
 	}
 
 	crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL);
@@ -1133,9 +992,10 @@ int ltdc_load(struct drm_device *ddev)
 	ddev->irq_enabled = 1;
 
 	return 0;
+
 err:
-	if (ldev->panel)
-		drm_panel_detach(ldev->panel);
+	if (ldev->is_panel_bridge)
+		drm_panel_bridge_remove(bridge);
 
 	clk_disable_unprepare(ldev->pixel_clk);
 
@@ -1148,8 +1008,8 @@ void ltdc_unload(struct drm_device *ddev)
 
 	DRM_DEBUG_DRIVER("\n");
 
-	if (ldev->panel)
-		drm_panel_detach(ldev->panel);
+	if (ldev->is_panel_bridge)
+		drm_panel_bridge_remove(ldev->bridge);
 
 	clk_disable_unprepare(ldev->pixel_clk);
 }
diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
index d7a9c73..d9e899d 100644
--- a/drivers/gpu/drm/stm/ltdc.h
+++ b/drivers/gpu/drm/stm/ltdc.h
@@ -24,7 +24,8 @@ struct ltdc_device {
 	struct drm_fbdev_cma *fbdev;
 	void __iomem *regs;
 	struct clk *pixel_clk;	/* lcd pixel clock */
-	struct drm_panel *panel;
+	struct drm_bridge *bridge;
+	bool is_panel_bridge;
 	struct mutex err_lock;	/* protecting error_status */
 	struct ltdc_caps caps;
 	u32 clut[256];		/* color look up table */
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v5 3/7] dt-bindings: display: Add Synopsys DW MIPI DSI host controller
  2017-07-03  8:41 ` Philippe CORNU
@ 2017-07-03  8:41   ` Philippe CORNU
  -1 siblings, 0 replies; 24+ messages in thread
From: Philippe CORNU @ 2017-07-03  8:41 UTC (permalink / raw)
  To: Alexandre Torgue, Thierry Reding, David Airlie, Maxime Coquelin,
	Russell King, Mark Rutland, Rob Herring, Arnd Bergmann,
	Benjamin Gaignard, Yannick Fertre, Neil Armstrong, Archit Taneja,
	Eric Anholt, Chris Zhong, Andrzej Hajda, Xinliang Liu,
	zourongrong, Xinwei Kong, Chen Feng, Mark Yao
  Cc: linux-arm-kernel, devicetree, Philippe Cornu, Fabien Dessenne,
	dri-devel, Mickael Reulier, Vincent Abriou, Gabriel Fernandez,
	Ludovic Barre

This patch adds documentation of device tree bindings for the
Synopsys DesignWare MIPI DSI host controller.

Signed-off-by: Philippe CORNU <philippe.cornu@st.com>
---
 .../bindings/display/bridge/dw_mipi_dsi.txt        | 32 ++++++++++++++++++++++
 1 file changed, 32 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt

diff --git a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
new file mode 100644
index 0000000..b13adf3
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
@@ -0,0 +1,32 @@
+Synopsys DesignWare MIPI DSI host controller
+============================================
+
+This document defines device tree properties for the Synopsys DesignWare MIPI
+DSI host controller. It doesn't constitue a device tree binding specification
+by itself but is meant to be referenced by platform-specific device tree
+bindings.
+
+When referenced from platform device tree bindings the properties defined in
+this document are defined as follows. The platform device tree bindings are
+responsible for defining whether each optional property is used or not.
+
+- reg: Memory mapped base address and length of the DesignWare MIPI DSI
+  host controller registers. (mandatory)
+
+- clocks: References to all the clocks specified in the clock-names property
+  as specified in [1]. (mandatory)
+
+- clock-names:
+  - "pclk" is the peripheral clock for either AHB and APB. (mandatory)
+  - "px_clk" is the pixel clock for the DPI/RGB input. (optional)
+
+- resets: References to all the resets specified in the reset-names property
+  as specified in [2]. (optional)
+
+- reset-names: string reset name, must be "apb" if used. (optional)
+
+- panel or bridge node: see [3]. (mandatory)
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/reset/reset.txt
+[3] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
-- 
1.9.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v5 3/7] dt-bindings: display: Add Synopsys DW MIPI DSI host controller
@ 2017-07-03  8:41   ` Philippe CORNU
  0 siblings, 0 replies; 24+ messages in thread
From: Philippe CORNU @ 2017-07-03  8:41 UTC (permalink / raw)
  To: linux-arm-kernel

This patch adds documentation of device tree bindings for the
Synopsys DesignWare MIPI DSI host controller.

Signed-off-by: Philippe CORNU <philippe.cornu@st.com>
---
 .../bindings/display/bridge/dw_mipi_dsi.txt        | 32 ++++++++++++++++++++++
 1 file changed, 32 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt

diff --git a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
new file mode 100644
index 0000000..b13adf3
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
@@ -0,0 +1,32 @@
+Synopsys DesignWare MIPI DSI host controller
+============================================
+
+This document defines device tree properties for the Synopsys DesignWare MIPI
+DSI host controller. It doesn't constitue a device tree binding specification
+by itself but is meant to be referenced by platform-specific device tree
+bindings.
+
+When referenced from platform device tree bindings the properties defined in
+this document are defined as follows. The platform device tree bindings are
+responsible for defining whether each optional property is used or not.
+
+- reg: Memory mapped base address and length of the DesignWare MIPI DSI
+  host controller registers. (mandatory)
+
+- clocks: References to all the clocks specified in the clock-names property
+  as specified in [1]. (mandatory)
+
+- clock-names:
+  - "pclk" is the peripheral clock for either AHB and APB. (mandatory)
+  - "px_clk" is the pixel clock for the DPI/RGB input. (optional)
+
+- resets: References to all the resets specified in the reset-names property
+  as specified in [2]. (optional)
+
+- reset-names: string reset name, must be "apb" if used. (optional)
+
+- panel or bridge node: see [3]. (mandatory)
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/reset/reset.txt
+[3] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v5 4/7] drm/bridge/synopsys: Add MIPI DSI host controller bridge
  2017-07-03  8:41 ` Philippe CORNU
@ 2017-07-03  8:41   ` Philippe CORNU
  -1 siblings, 0 replies; 24+ messages in thread
From: Philippe CORNU @ 2017-07-03  8:41 UTC (permalink / raw)
  To: Alexandre Torgue, Thierry Reding, David Airlie, Maxime Coquelin,
	Russell King, Mark Rutland, Rob Herring, Arnd Bergmann,
	Benjamin Gaignard, Yannick Fertre, Neil Armstrong, Archit Taneja,
	Eric Anholt, Chris Zhong, Andrzej Hajda, Xinliang Liu,
	zourongrong, Xinwei Kong, Chen Feng, Mark Yao
  Cc: linux-arm-kernel, devicetree, Philippe Cornu, Fabien Dessenne,
	dri-devel, Mickael Reulier, Vincent Abriou, Gabriel Fernandez,
	Ludovic Barre

Add a Synopsys Designware MIPI DSI host DRM bridge driver, based on the
Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.

Signed-off-by: Philippe CORNU <philippe.cornu@st.com>
---
 drivers/gpu/drm/bridge/synopsys/Kconfig       |   6 +
 drivers/gpu/drm/bridge/synopsys/Makefile      |   2 +
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 979 ++++++++++++++++++++++++++
 include/drm/bridge/dw_mipi_dsi.h              |  39 +
 4 files changed, 1026 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
 create mode 100644 include/drm/bridge/dw_mipi_dsi.h

diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig b/drivers/gpu/drm/bridge/synopsys/Kconfig
index 40d2827..f00ee26 100644
--- a/drivers/gpu/drm/bridge/synopsys/Kconfig
+++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
@@ -21,3 +21,9 @@ config DRM_DW_HDMI_I2S_AUDIO
 	help
 	  Support the I2S Audio interface which is part of the Synopsys
 	  Designware HDMI block.
+
+config DRM_DW_MIPI_DSI
+	tristate
+	select DRM_KMS_HELPER
+	select DRM_MIPI_DSI
+	select DRM_PANEL_BRIDGE
diff --git a/drivers/gpu/drm/bridge/synopsys/Makefile b/drivers/gpu/drm/bridge/synopsys/Makefile
index 17aa7a6..5f57d36 100644
--- a/drivers/gpu/drm/bridge/synopsys/Makefile
+++ b/drivers/gpu/drm/bridge/synopsys/Makefile
@@ -3,3 +3,5 @@
 obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
 obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
 obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
+
+obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw-mipi-dsi.o
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
new file mode 100644
index 0000000..406000e
--- /dev/null
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -0,0 +1,979 @@
+/*
+ * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (C) STMicroelectronics SA 2017
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Modified by Philippe Cornu <philippe.cornu@st.com>
+ * This generic Synopsys DesignWare MIPI DSI host driver is based on the
+ * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <drm/drmP.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_of.h>
+#include <drm/bridge/dw_mipi_dsi.h>
+#include <video/mipi_display.h>
+
+#define DSI_VERSION			0x00
+#define DSI_PWR_UP			0x04
+#define RESET				0
+#define POWERUP				BIT(0)
+
+#define DSI_CLKMGR_CFG			0x08
+#define TO_CLK_DIVIDSION(div)		(((div) & 0xff) << 8)
+#define TX_ESC_CLK_DIVIDSION(div)	(((div) & 0xff) << 0)
+
+#define DSI_DPI_VCID			0x0c
+#define DPI_VID(vid)			(((vid) & 0x3) << 0)
+
+#define DSI_DPI_COLOR_CODING		0x10
+#define EN18_LOOSELY			BIT(8)
+#define DPI_COLOR_CODING_16BIT_1	0x0
+#define DPI_COLOR_CODING_16BIT_2	0x1
+#define DPI_COLOR_CODING_16BIT_3	0x2
+#define DPI_COLOR_CODING_18BIT_1	0x3
+#define DPI_COLOR_CODING_18BIT_2	0x4
+#define DPI_COLOR_CODING_24BIT		0x5
+
+#define DSI_DPI_CFG_POL			0x14
+#define COLORM_ACTIVE_LOW		BIT(4)
+#define SHUTD_ACTIVE_LOW		BIT(3)
+#define HSYNC_ACTIVE_LOW		BIT(2)
+#define VSYNC_ACTIVE_LOW		BIT(1)
+#define DATAEN_ACTIVE_LOW		BIT(0)
+
+#define DSI_DPI_LP_CMD_TIM		0x18
+#define OUTVACT_LPCMD_TIME(p)		(((p) & 0xff) << 16)
+#define INVACT_LPCMD_TIME(p)		((p) & 0xff)
+
+#define DSI_DBI_CFG			0x20
+#define DSI_DBI_CMDSIZE			0x28
+
+#define DSI_PCKHDL_CFG			0x2c
+#define EN_CRC_RX			BIT(4)
+#define EN_ECC_RX			BIT(3)
+#define EN_BTA				BIT(2)
+#define EN_EOTP_RX			BIT(1)
+#define EN_EOTP_TX			BIT(0)
+
+#define DSI_MODE_CFG			0x34
+#define ENABLE_VIDEO_MODE		0
+#define ENABLE_CMD_MODE			BIT(0)
+
+#define DSI_VID_MODE_CFG		0x38
+#define FRAME_BTA_ACK			BIT(14)
+#define ENABLE_LOW_POWER		(0x3f << 8)
+#define ENABLE_LOW_POWER_MASK		(0x3f << 8)
+#define VID_MODE_TYPE_NON_BURST_SYNC_PULSES	0x0
+#define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS	0x1
+#define VID_MODE_TYPE_BURST			0x2
+#define VID_MODE_TYPE_MASK			0x3
+
+#define DSI_VID_PKT_SIZE		0x3c
+#define VID_PKT_SIZE(p)			(((p) & 0x3fff) << 0)
+#define VID_PKT_MAX_SIZE		0x3fff
+
+#define DSI_VID_HSA_TIME		0x48
+#define DSI_VID_HBP_TIME		0x4c
+#define DSI_VID_HLINE_TIME		0x50
+#define DSI_VID_VSA_LINES		0x54
+#define DSI_VID_VBP_LINES		0x58
+#define DSI_VID_VFP_LINES		0x5c
+#define DSI_VID_VACTIVE_LINES		0x60
+#define DSI_CMD_MODE_CFG		0x68
+#define MAX_RD_PKT_SIZE_LP		BIT(24)
+#define DCS_LW_TX_LP			BIT(19)
+#define DCS_SR_0P_TX_LP			BIT(18)
+#define DCS_SW_1P_TX_LP			BIT(17)
+#define DCS_SW_0P_TX_LP			BIT(16)
+#define GEN_LW_TX_LP			BIT(14)
+#define GEN_SR_2P_TX_LP			BIT(13)
+#define GEN_SR_1P_TX_LP			BIT(12)
+#define GEN_SR_0P_TX_LP			BIT(11)
+#define GEN_SW_2P_TX_LP			BIT(10)
+#define GEN_SW_1P_TX_LP			BIT(9)
+#define GEN_SW_0P_TX_LP			BIT(8)
+#define EN_ACK_RQST			BIT(1)
+#define EN_TEAR_FX			BIT(0)
+
+#define CMD_MODE_ALL_LP			(MAX_RD_PKT_SIZE_LP | \
+					 DCS_LW_TX_LP | \
+					 DCS_SR_0P_TX_LP | \
+					 DCS_SW_1P_TX_LP | \
+					 DCS_SW_0P_TX_LP | \
+					 GEN_LW_TX_LP | \
+					 GEN_SR_2P_TX_LP | \
+					 GEN_SR_1P_TX_LP | \
+					 GEN_SR_0P_TX_LP | \
+					 GEN_SW_2P_TX_LP | \
+					 GEN_SW_1P_TX_LP | \
+					 GEN_SW_0P_TX_LP)
+
+#define DSI_GEN_HDR			0x6c
+#define GEN_HDATA(data)			(((data) & 0xffff) << 8)
+#define GEN_HDATA_MASK			(0xffff << 8)
+#define GEN_HTYPE(type)			(((type) & 0xff) << 0)
+#define GEN_HTYPE_MASK			0xff
+
+#define DSI_GEN_PLD_DATA		0x70
+
+#define DSI_CMD_PKT_STATUS		0x74
+#define GEN_CMD_EMPTY			BIT(0)
+#define GEN_CMD_FULL			BIT(1)
+#define GEN_PLD_W_EMPTY			BIT(2)
+#define GEN_PLD_W_FULL			BIT(3)
+#define GEN_PLD_R_EMPTY			BIT(4)
+#define GEN_PLD_R_FULL			BIT(5)
+#define GEN_RD_CMD_BUSY			BIT(6)
+
+#define DSI_TO_CNT_CFG			0x78
+#define HSTX_TO_CNT(p)			(((p) & 0xffff) << 16)
+#define LPRX_TO_CNT(p)			((p) & 0xffff)
+
+#define DSI_BTA_TO_CNT			0x8c
+#define DSI_LPCLK_CTRL			0x94
+#define AUTO_CLKLANE_CTRL		BIT(1)
+#define PHY_TXREQUESTCLKHS		BIT(0)
+
+#define DSI_PHY_TMR_LPCLK_CFG		0x98
+#define PHY_CLKHS2LP_TIME(lbcc)		(((lbcc) & 0x3ff) << 16)
+#define PHY_CLKLP2HS_TIME(lbcc)		((lbcc) & 0x3ff)
+
+#define DSI_PHY_TMR_CFG			0x9c
+#define PHY_HS2LP_TIME(lbcc)		(((lbcc) & 0xff) << 24)
+#define PHY_LP2HS_TIME(lbcc)		(((lbcc) & 0xff) << 16)
+#define MAX_RD_TIME(lbcc)		((lbcc) & 0x7fff)
+
+#define DSI_PHY_RSTZ			0xa0
+#define PHY_DISFORCEPLL			0
+#define PHY_ENFORCEPLL			BIT(3)
+#define PHY_DISABLECLK			0
+#define PHY_ENABLECLK			BIT(2)
+#define PHY_RSTZ			0
+#define PHY_UNRSTZ			BIT(1)
+#define PHY_SHUTDOWNZ			0
+#define PHY_UNSHUTDOWNZ			BIT(0)
+
+#define DSI_PHY_IF_CFG			0xa4
+#define N_LANES(n)			((((n) - 1) & 0x3) << 0)
+#define PHY_STOP_WAIT_TIME(cycle)	(((cycle) & 0xff) << 8)
+
+#define DSI_PHY_STATUS			0xb0
+#define LOCK				BIT(0)
+#define STOP_STATE_CLK_LANE		BIT(2)
+
+#define DSI_PHY_TST_CTRL0		0xb4
+#define PHY_TESTCLK			BIT(1)
+#define PHY_UNTESTCLK			0
+#define PHY_TESTCLR			BIT(0)
+#define PHY_UNTESTCLR			0
+
+#define DSI_PHY_TST_CTRL1		0xb8
+#define PHY_TESTEN			BIT(16)
+#define PHY_UNTESTEN			0
+#define PHY_TESTDOUT(n)			(((n) & 0xff) << 8)
+#define PHY_TESTDIN(n)			(((n) & 0xff) << 0)
+
+#define DSI_INT_ST0			0xbc
+#define DSI_INT_ST1			0xc0
+#define DSI_INT_MSK0			0xc4
+#define DSI_INT_MSK1			0xc8
+
+#define PHY_STATUS_TIMEOUT_US		10000
+#define CMD_PKT_STATUS_TIMEOUT_US	20000
+
+struct dw_mipi_dsi {
+	struct drm_bridge bridge;
+	struct mipi_dsi_host dsi_host;
+	struct drm_bridge *panel_bridge;
+	bool is_panel_bridge;
+	struct device *dev;
+	void __iomem *base;
+
+	struct clk *pclk;
+
+	unsigned int lane_mbps; /* per lane */
+	u32 channel;
+	u32 lanes;
+	u32 format;
+	unsigned long mode_flags;
+
+	const struct dw_mipi_dsi_plat_data *plat_data;
+};
+
+/*
+ * The controller should generate 2 frames before
+ * preparing the peripheral.
+ */
+static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode *mode)
+{
+	int refresh, two_frames;
+
+	refresh = drm_mode_vrefresh(mode);
+	two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
+	msleep(two_frames);
+}
+
+static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
+{
+	return container_of(host, struct dw_mipi_dsi, dsi_host);
+}
+
+static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge)
+{
+	return container_of(bridge, struct dw_mipi_dsi, bridge);
+}
+
+static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
+{
+	writel(val, dsi->base + reg);
+}
+
+static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
+{
+	return readl(dsi->base + reg);
+}
+
+static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
+				   struct mipi_dsi_device *device)
+{
+	struct dw_mipi_dsi *dsi = host_to_dsi(host);
+	struct drm_bridge *bridge;
+	struct drm_panel *panel;
+	int ret;
+
+	if (device->lanes > dsi->plat_data->max_data_lanes) {
+		dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
+			device->lanes);
+		return -EINVAL;
+	}
+
+	dsi->lanes = device->lanes;
+	dsi->channel = device->channel;
+	dsi->format = device->format;
+	dsi->mode_flags = device->mode_flags;
+
+	ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0,
+					  &panel, &bridge);
+	if (ret)
+		return ret;
+
+	if (panel) {
+		bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DSI);
+		if (IS_ERR(bridge))
+			return PTR_ERR(bridge);
+		dsi->is_panel_bridge = true;
+	}
+
+	dsi->panel_bridge = bridge;
+
+	return drm_bridge_add(&dsi->bridge);
+}
+
+static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
+				   struct mipi_dsi_device *device)
+{
+	struct dw_mipi_dsi *dsi = host_to_dsi(host);
+
+	if (dsi->is_panel_bridge)
+		drm_panel_bridge_remove(dsi->panel_bridge);
+
+	drm_bridge_remove(&dsi->bridge);
+
+	return 0;
+}
+
+static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
+				   const struct mipi_dsi_msg *msg)
+{
+	bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
+	u32 val = 0;
+
+	if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
+		val |= EN_ACK_RQST;
+	if (lpm)
+		val |= CMD_MODE_ALL_LP;
+
+	dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
+	dsi_write(dsi, DSI_CMD_MODE_CFG, val);
+}
+
+static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
+{
+	int ret;
+	u32 val, mask;
+
+	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
+				 val, !(val & GEN_CMD_FULL), 1000,
+				 CMD_PKT_STATUS_TIMEOUT_US);
+	if (ret < 0) {
+		dev_err(dsi->dev, "failed to get available command FIFO\n");
+		return ret;
+	}
+
+	dsi_write(dsi, DSI_GEN_HDR, hdr_val);
+
+	mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
+	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
+				 val, (val & mask) == mask,
+				 1000, CMD_PKT_STATUS_TIMEOUT_US);
+	if (ret < 0) {
+		dev_err(dsi->dev, "failed to write command FIFO\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi *dsi,
+				       const struct mipi_dsi_msg *msg)
+{
+	const u8 *tx_buf = msg->tx_buf;
+	u16 data = 0;
+	u32 val;
+
+	if (msg->tx_len > 0)
+		data |= tx_buf[0];
+	if (msg->tx_len > 1)
+		data |= tx_buf[1] << 8;
+
+	if (msg->tx_len > 2) {
+		dev_err(dsi->dev, "too long tx buf length %zu for short write\n",
+			msg->tx_len);
+		return -EINVAL;
+	}
+
+	val = GEN_HDATA(data) | GEN_HTYPE(msg->type);
+	return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
+}
+
+static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
+				      const struct mipi_dsi_msg *msg)
+{
+	const u8 *tx_buf = msg->tx_buf;
+	int len = msg->tx_len, pld_data_bytes = sizeof(u32), ret;
+	u32 hdr_val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
+	u32 remainder;
+	u32 val;
+
+	if (msg->tx_len < 3) {
+		dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
+			msg->tx_len);
+		return -EINVAL;
+	}
+
+	while (DIV_ROUND_UP(len, pld_data_bytes)) {
+		if (len < pld_data_bytes) {
+			remainder = 0;
+			memcpy(&remainder, tx_buf, len);
+			dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
+			len = 0;
+		} else {
+			memcpy(&remainder, tx_buf, pld_data_bytes);
+			dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
+			tx_buf += pld_data_bytes;
+			len -= pld_data_bytes;
+		}
+
+		ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
+					 val, !(val & GEN_PLD_W_FULL), 1000,
+					 CMD_PKT_STATUS_TIMEOUT_US);
+		if (ret < 0) {
+			dev_err(dsi->dev,
+				"failed to get available write payload FIFO\n");
+			return ret;
+		}
+	}
+
+	return dw_mipi_dsi_gen_pkt_hdr_write(dsi, hdr_val);
+}
+
+static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
+					 const struct mipi_dsi_msg *msg)
+{
+	struct dw_mipi_dsi *dsi = host_to_dsi(host);
+	int ret;
+
+	/*
+	 * TODO dw drv improvements
+	 * use mipi_dsi_create_packet() instead of all following
+	 * functions and code (no switch cases, no
+	 * dw_mipi_dsi_dcs_short_write(), only the loop in long_write...)
+	 * and use packet.header...
+	 */
+	dw_mipi_message_config(dsi, msg);
+
+	switch (msg->type) {
+	case MIPI_DSI_DCS_SHORT_WRITE:
+	case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
+	case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
+		ret = dw_mipi_dsi_dcs_short_write(dsi, msg);
+		break;
+	case MIPI_DSI_DCS_LONG_WRITE:
+		ret = dw_mipi_dsi_dcs_long_write(dsi, msg);
+		break;
+	default:
+		dev_err(dsi->dev, "unsupported message type 0x%02x\n",
+			msg->type);
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
+	.attach = dw_mipi_dsi_host_attach,
+	.detach = dw_mipi_dsi_host_detach,
+	.transfer = dw_mipi_dsi_host_transfer,
+};
+
+static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
+{
+	u32 val;
+
+	/*
+	 * TODO dw drv improvements
+	 * enabling low power is panel-dependent, we should use the
+	 * panel configuration here...
+	 */
+	val = ENABLE_LOW_POWER;
+
+	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
+		val |= VID_MODE_TYPE_BURST;
+	else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
+		val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
+	else
+		val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
+
+	dsi_write(dsi, DSI_VID_MODE_CFG, val);
+}
+
+static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
+				 unsigned long mode_flags)
+{
+	dsi_write(dsi, DSI_PWR_UP, RESET);
+
+	if (mode_flags & MIPI_DSI_MODE_VIDEO) {
+		dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
+		dw_mipi_dsi_video_mode_config(dsi);
+		dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
+	} else {
+		dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
+	}
+
+	dsi_write(dsi, DSI_PWR_UP, POWERUP);
+}
+
+static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
+{
+	dsi_write(dsi, DSI_PWR_UP, RESET);
+	dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
+}
+
+static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
+{
+	/*
+	 * The maximum permitted escape clock is 20MHz and it is derived from
+	 * lanebyteclk, which is running at "lane_mbps / 8".  Thus we want:
+	 *
+	 *     (lane_mbps >> 3) / esc_clk_division < 20
+	 * which is:
+	 *     (lane_mbps >> 3) / 20 > esc_clk_division
+	 */
+	u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
+
+	dsi_write(dsi, DSI_PWR_UP, RESET);
+
+	/*
+	 * TODO dw drv improvements
+	 * timeout clock division should be computed with the
+	 * high speed transmission counter timeout and byte lane...
+	 */
+	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
+		  TX_ESC_CLK_DIVIDSION(esc_clk_division));
+}
+
+static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
+				   struct drm_display_mode *mode)
+{
+	u32 val = 0, color = 0;
+
+	switch (dsi->format) {
+	case MIPI_DSI_FMT_RGB888:
+		color = DPI_COLOR_CODING_24BIT;
+		break;
+	case MIPI_DSI_FMT_RGB666:
+		color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
+		break;
+	case MIPI_DSI_FMT_RGB666_PACKED:
+		color = DPI_COLOR_CODING_18BIT_1;
+		break;
+	case MIPI_DSI_FMT_RGB565:
+		color = DPI_COLOR_CODING_16BIT_1;
+		break;
+	}
+
+	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
+		val |= VSYNC_ACTIVE_LOW;
+	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
+		val |= HSYNC_ACTIVE_LOW;
+
+	dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
+	dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
+	dsi_write(dsi, DSI_DPI_CFG_POL, val);
+	/*
+	 * TODO dw drv improvements
+	 * largest packet sizes during hfp or during vsa/vpb/vfp
+	 * should be computed according to byte lane, lane number and only
+	 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
+	 */
+	dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
+		  | INVACT_LPCMD_TIME(4));
+}
+
+static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
+{
+	dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
+}
+
+static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
+					    struct drm_display_mode *mode)
+{
+	/*
+	 * TODO dw drv improvements
+	 * only burst mode is supported here. For non-burst video modes,
+	 * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
+	 * DSI_VNPCR.NPSIZE... especially because this driver supports
+	 * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
+	 */
+	dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
+}
+
+static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
+{
+	/*
+	 * TODO dw drv improvements
+	 * compute high speed transmission counter timeout according
+	 * to the timeout clock division (TO_CLK_DIVIDSION) and byte lane...
+	 */
+	dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
+	/*
+	 * TODO dw drv improvements
+	 * the Bus-Turn-Around Timeout Counter should be computed
+	 * according to byte lane...
+	 */
+	dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
+	dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
+}
+
+/* Get lane byte clock cycles. */
+static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
+					   struct drm_display_mode *mode,
+					   u32 hcomponent)
+{
+	u32 frac, lbcc;
+
+	lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
+
+	frac = lbcc % mode->clock;
+	lbcc = lbcc / mode->clock;
+	if (frac)
+		lbcc++;
+
+	return lbcc;
+}
+
+static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
+					  struct drm_display_mode *mode)
+{
+	u32 htotal, hsa, hbp, lbcc;
+
+	htotal = mode->htotal;
+	hsa = mode->hsync_end - mode->hsync_start;
+	hbp = mode->htotal - mode->hsync_end;
+
+	/*
+	 * TODO dw drv improvements
+	 * computations below may be improved...
+	 */
+	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
+	dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
+
+	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
+	dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
+
+	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
+	dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
+}
+
+static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
+					       struct drm_display_mode *mode)
+{
+	u32 vactive, vsa, vfp, vbp;
+
+	vactive = mode->vdisplay;
+	vsa = mode->vsync_end - mode->vsync_start;
+	vfp = mode->vsync_start - mode->vdisplay;
+	vbp = mode->vtotal - mode->vsync_end;
+
+	dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
+	dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
+	dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
+	dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
+}
+
+static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
+{
+	/*
+	 * TODO dw drv improvements
+	 * data & clock lane timers should be computed according to panel
+	 * blankings and to the automatic clock lane control mode...
+	 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
+	 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
+	 */
+	dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40)
+		  | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
+
+	dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
+		  | PHY_CLKLP2HS_TIME(0x40));
+}
+
+static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
+{
+	/*
+	 * TODO dw drv improvements
+	 * stop wait time should be the maximum between host dsi
+	 * and panel stop wait times
+	 */
+	dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
+		  N_LANES(dsi->lanes));
+}
+
+static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
+{
+	/* Clear PHY state */
+	dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
+		  | PHY_RSTZ | PHY_SHUTDOWNZ);
+	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
+	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
+	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
+}
+
+static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
+{
+	u32 val;
+	int ret;
+
+	dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
+		  PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
+
+	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
+				 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
+	if (ret < 0)
+		DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
+
+	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
+				 val, val & STOP_STATE_CLK_LANE, 1000,
+				 PHY_STATUS_TIMEOUT_US);
+	if (ret < 0)
+		DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
+}
+
+static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
+{
+	dsi_read(dsi, DSI_INT_ST0);
+	dsi_read(dsi, DSI_INT_ST1);
+	dsi_write(dsi, DSI_INT_MSK0, 0);
+	dsi_write(dsi, DSI_INT_MSK1, 0);
+}
+
+static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
+{
+	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
+
+	/*
+	 * Switch to command mode before panel-bridge post_disable &
+	 * panel unprepare.
+	 * Note: panel-bridge disable & panel disable has been called
+	 * before by the drm framework.
+	 */
+	dw_mipi_dsi_set_mode(dsi, 0);
+
+	/*
+	 * TODO Only way found to call panel-bridge post_disable &
+	 * panel unprepare before the dsi "final" disable...
+	 * This needs to be fixed in the drm_bridge framework and the API
+	 * needs to be updated to manage our own call chains...
+	 */
+	dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge);
+
+	dw_mipi_dsi_disable(dsi);
+	clk_disable_unprepare(dsi->pclk);
+	pm_runtime_put(dsi->dev);
+}
+
+void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
+				 struct drm_display_mode *mode,
+				 struct drm_display_mode *adjusted_mode)
+{
+	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
+	const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
+	void *priv_data = dsi->plat_data->priv_data;
+	int ret;
+
+	clk_prepare_enable(dsi->pclk);
+
+	ret = phy_ops->get_lane_mbps(priv_data, mode, dsi->mode_flags,
+				     dsi->lanes, dsi->format, &dsi->lane_mbps);
+	if (ret)
+		DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n");
+
+	pm_runtime_get_sync(dsi->dev);
+	dw_mipi_dsi_init(dsi);
+	dw_mipi_dsi_dpi_config(dsi, mode);
+	dw_mipi_dsi_packet_handler_config(dsi);
+	dw_mipi_dsi_video_mode_config(dsi);
+	dw_mipi_dsi_video_packet_config(dsi, mode);
+	dw_mipi_dsi_command_mode_config(dsi);
+	dw_mipi_dsi_line_timer_config(dsi, mode);
+	dw_mipi_dsi_vertical_timing_config(dsi, mode);
+
+	dw_mipi_dsi_dphy_init(dsi);
+	dw_mipi_dsi_dphy_timing_config(dsi);
+	dw_mipi_dsi_dphy_interface_config(dsi);
+
+	dw_mipi_dsi_clear_err(dsi);
+
+	ret = phy_ops->init(priv_data);
+	if (ret)
+		DRM_DEBUG_DRIVER("Phy init() failed\n");
+
+	dw_mipi_dsi_dphy_enable(dsi);
+
+	dw_mipi_dsi_wait_for_two_frames(mode);
+
+	/* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
+	dw_mipi_dsi_set_mode(dsi, 0);
+}
+
+static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge)
+{
+	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
+
+	/* Switch to video mode for panel-bridge enable & panel enable */
+	dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
+}
+
+static enum drm_mode_status
+dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
+			      const struct drm_display_mode *mode)
+{
+	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
+	const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
+	enum drm_mode_status mode_status = MODE_OK;
+
+	if (pdata->mode_valid)
+		mode_status = pdata->mode_valid(pdata->priv_data, mode);
+
+	return mode_status;
+}
+
+static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge)
+{
+	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
+
+	if (!bridge->encoder) {
+		DRM_ERROR("Parent encoder object not found\n");
+		return -ENODEV;
+	}
+
+	/* Set the encoder type as caller does not know it */
+	bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI;
+
+	/* Attach the panel-bridge to the dsi bridge */
+	return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge);
+}
+
+static struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = {
+	.mode_set     = dw_mipi_dsi_bridge_mode_set,
+	.enable	      = dw_mipi_dsi_bridge_enable,
+	.post_disable = dw_mipi_dsi_bridge_post_disable,
+	.mode_valid   = dw_mipi_dsi_bridge_mode_valid,
+	.attach	      = dw_mipi_dsi_bridge_attach,
+};
+
+static struct dw_mipi_dsi *
+__dw_mipi_dsi_probe(struct platform_device *pdev,
+		    const struct dw_mipi_dsi_plat_data *plat_data)
+{
+	struct device *dev = &pdev->dev;
+	struct reset_control *apb_rst;
+	struct dw_mipi_dsi *dsi;
+	struct resource *res;
+	int ret;
+
+	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
+	if (!dsi)
+		return ERR_PTR(-ENOMEM);
+
+	dsi->dev = dev;
+	dsi->plat_data = plat_data;
+
+	if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps) {
+		DRM_ERROR("Phy not properly configured\n");
+		return ERR_PTR(-ENODEV);
+	}
+
+	if (!plat_data->base) {
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+		if (!res)
+			return ERR_PTR(-ENODEV);
+
+		dsi->base = devm_ioremap_resource(dev, res);
+		if (IS_ERR(dsi->base))
+			return ERR_PTR(-ENODEV);
+
+	} else {
+		dsi->base = plat_data->base;
+	}
+
+	dsi->pclk = devm_clk_get(dev, "pclk");
+	if (IS_ERR(dsi->pclk)) {
+		ret = PTR_ERR(dsi->pclk);
+		dev_err(dev, "Unable to get pclk: %d\n", ret);
+		return ERR_PTR(ret);
+	}
+
+	/*
+	 * Note that the reset was not defined in the initial device tree, so
+	 * we have to be prepared for it not being found.
+	 */
+	apb_rst = devm_reset_control_get(dev, "apb");
+	if (IS_ERR(apb_rst)) {
+		ret = PTR_ERR(apb_rst);
+		if (ret == -ENOENT) {
+			apb_rst = NULL;
+		} else {
+			dev_err(dev, "Unable to get reset control: %d\n", ret);
+			return ERR_PTR(ret);
+		}
+	}
+
+	if (apb_rst) {
+		ret = clk_prepare_enable(dsi->pclk);
+		if (ret) {
+			dev_err(dev, "%s: Failed to enable pclk\n", __func__);
+			return ERR_PTR(ret);
+		}
+
+		reset_control_assert(apb_rst);
+		usleep_range(10, 20);
+		reset_control_deassert(apb_rst);
+
+		clk_disable_unprepare(dsi->pclk);
+	}
+
+	pm_runtime_enable(dev);
+
+	dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
+	dsi->dsi_host.dev = dev;
+	ret = mipi_dsi_host_register(&dsi->dsi_host);
+	if (ret) {
+		dev_err(dev, "Failed to register MIPI host: %d\n", ret);
+		return ERR_PTR(ret);
+	}
+
+	dsi->bridge.driver_private = dsi;
+	dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs;
+#ifdef CONFIG_OF
+	dsi->bridge.of_node = pdev->dev.of_node;
+#endif
+
+	dev_set_drvdata(dev, dsi);
+
+	return dsi;
+}
+
+static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
+{
+	pm_runtime_disable(dsi->dev);
+}
+
+/*
+ * Probe/remove API, used from platforms based on the DRM bridge API.
+ */
+int dw_mipi_dsi_probe(struct platform_device *pdev,
+		      const struct dw_mipi_dsi_plat_data *plat_data)
+{
+	struct dw_mipi_dsi *dsi;
+
+	dsi = __dw_mipi_dsi_probe(pdev, plat_data);
+	if (IS_ERR(dsi))
+		return PTR_ERR(dsi);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe);
+
+void dw_mipi_dsi_remove(struct platform_device *pdev)
+{
+	struct dw_mipi_dsi *dsi = platform_get_drvdata(pdev);
+
+	mipi_dsi_host_unregister(&dsi->dsi_host);
+
+	__dw_mipi_dsi_remove(dsi);
+}
+EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove);
+
+/*
+ * Bind/unbind API, used from platforms based on the component framework.
+ */
+int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
+		     const struct dw_mipi_dsi_plat_data *plat_data)
+{
+	struct dw_mipi_dsi *dsi;
+	int ret;
+
+	dsi = __dw_mipi_dsi_probe(pdev, plat_data);
+	if (IS_ERR(dsi))
+		return PTR_ERR(dsi);
+
+	ret = drm_bridge_attach(encoder, &dsi->bridge, NULL);
+	if (ret) {
+		dw_mipi_dsi_remove(pdev);
+		DRM_ERROR("Failed to initialize bridge with drm\n");
+		return ret;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
+
+void dw_mipi_dsi_unbind(struct device *dev)
+{
+	struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
+
+	__dw_mipi_dsi_remove(dsi);
+}
+EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
+
+MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
+MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
+MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:dw-mipi-dsi");
diff --git a/include/drm/bridge/dw_mipi_dsi.h b/include/drm/bridge/dw_mipi_dsi.h
new file mode 100644
index 0000000..9b30fec
--- /dev/null
+++ b/include/drm/bridge/dw_mipi_dsi.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ *
+ * Authors: Philippe Cornu <philippe.cornu@st.com>
+ *          Yannick Fertre <yannick.fertre@st.com>
+ *
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+#ifndef __DW_MIPI_DSI__
+#define __DW_MIPI_DSI__
+
+struct dw_mipi_dsi_phy_ops {
+	int (*init)(void *priv_data);
+	int (*get_lane_mbps)(void *priv_data, struct drm_display_mode *mode,
+			     unsigned long mode_flags, u32 lanes, u32 format,
+			     unsigned int *lane_mbps);
+};
+
+struct dw_mipi_dsi_plat_data {
+	void __iomem *base;
+	unsigned int max_data_lanes;
+
+	enum drm_mode_status (*mode_valid)(void *priv_data,
+					   const struct drm_display_mode *mode);
+
+	const struct dw_mipi_dsi_phy_ops *phy_ops;
+
+	void *priv_data;
+};
+
+int dw_mipi_dsi_probe(struct platform_device *pdev,
+		      const struct dw_mipi_dsi_plat_data *plat_data);
+void dw_mipi_dsi_remove(struct platform_device *pdev);
+int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
+		     const struct dw_mipi_dsi_plat_data *plat_data);
+void dw_mipi_dsi_unbind(struct device *dev);
+
+#endif /* __DW_MIPI_DSI__ */
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v5 4/7] drm/bridge/synopsys: Add MIPI DSI host controller bridge
@ 2017-07-03  8:41   ` Philippe CORNU
  0 siblings, 0 replies; 24+ messages in thread
From: Philippe CORNU @ 2017-07-03  8:41 UTC (permalink / raw)
  To: linux-arm-kernel

Add a Synopsys Designware MIPI DSI host DRM bridge driver, based on the
Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.

Signed-off-by: Philippe CORNU <philippe.cornu@st.com>
---
 drivers/gpu/drm/bridge/synopsys/Kconfig       |   6 +
 drivers/gpu/drm/bridge/synopsys/Makefile      |   2 +
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 979 ++++++++++++++++++++++++++
 include/drm/bridge/dw_mipi_dsi.h              |  39 +
 4 files changed, 1026 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
 create mode 100644 include/drm/bridge/dw_mipi_dsi.h

diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig b/drivers/gpu/drm/bridge/synopsys/Kconfig
index 40d2827..f00ee26 100644
--- a/drivers/gpu/drm/bridge/synopsys/Kconfig
+++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
@@ -21,3 +21,9 @@ config DRM_DW_HDMI_I2S_AUDIO
 	help
 	  Support the I2S Audio interface which is part of the Synopsys
 	  Designware HDMI block.
+
+config DRM_DW_MIPI_DSI
+	tristate
+	select DRM_KMS_HELPER
+	select DRM_MIPI_DSI
+	select DRM_PANEL_BRIDGE
diff --git a/drivers/gpu/drm/bridge/synopsys/Makefile b/drivers/gpu/drm/bridge/synopsys/Makefile
index 17aa7a6..5f57d36 100644
--- a/drivers/gpu/drm/bridge/synopsys/Makefile
+++ b/drivers/gpu/drm/bridge/synopsys/Makefile
@@ -3,3 +3,5 @@
 obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
 obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
 obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
+
+obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw-mipi-dsi.o
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
new file mode 100644
index 0000000..406000e
--- /dev/null
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -0,0 +1,979 @@
+/*
+ * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (C) STMicroelectronics SA 2017
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Modified by Philippe Cornu <philippe.cornu@st.com>
+ * This generic Synopsys DesignWare MIPI DSI host driver is based on the
+ * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <drm/drmP.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_of.h>
+#include <drm/bridge/dw_mipi_dsi.h>
+#include <video/mipi_display.h>
+
+#define DSI_VERSION			0x00
+#define DSI_PWR_UP			0x04
+#define RESET				0
+#define POWERUP				BIT(0)
+
+#define DSI_CLKMGR_CFG			0x08
+#define TO_CLK_DIVIDSION(div)		(((div) & 0xff) << 8)
+#define TX_ESC_CLK_DIVIDSION(div)	(((div) & 0xff) << 0)
+
+#define DSI_DPI_VCID			0x0c
+#define DPI_VID(vid)			(((vid) & 0x3) << 0)
+
+#define DSI_DPI_COLOR_CODING		0x10
+#define EN18_LOOSELY			BIT(8)
+#define DPI_COLOR_CODING_16BIT_1	0x0
+#define DPI_COLOR_CODING_16BIT_2	0x1
+#define DPI_COLOR_CODING_16BIT_3	0x2
+#define DPI_COLOR_CODING_18BIT_1	0x3
+#define DPI_COLOR_CODING_18BIT_2	0x4
+#define DPI_COLOR_CODING_24BIT		0x5
+
+#define DSI_DPI_CFG_POL			0x14
+#define COLORM_ACTIVE_LOW		BIT(4)
+#define SHUTD_ACTIVE_LOW		BIT(3)
+#define HSYNC_ACTIVE_LOW		BIT(2)
+#define VSYNC_ACTIVE_LOW		BIT(1)
+#define DATAEN_ACTIVE_LOW		BIT(0)
+
+#define DSI_DPI_LP_CMD_TIM		0x18
+#define OUTVACT_LPCMD_TIME(p)		(((p) & 0xff) << 16)
+#define INVACT_LPCMD_TIME(p)		((p) & 0xff)
+
+#define DSI_DBI_CFG			0x20
+#define DSI_DBI_CMDSIZE			0x28
+
+#define DSI_PCKHDL_CFG			0x2c
+#define EN_CRC_RX			BIT(4)
+#define EN_ECC_RX			BIT(3)
+#define EN_BTA				BIT(2)
+#define EN_EOTP_RX			BIT(1)
+#define EN_EOTP_TX			BIT(0)
+
+#define DSI_MODE_CFG			0x34
+#define ENABLE_VIDEO_MODE		0
+#define ENABLE_CMD_MODE			BIT(0)
+
+#define DSI_VID_MODE_CFG		0x38
+#define FRAME_BTA_ACK			BIT(14)
+#define ENABLE_LOW_POWER		(0x3f << 8)
+#define ENABLE_LOW_POWER_MASK		(0x3f << 8)
+#define VID_MODE_TYPE_NON_BURST_SYNC_PULSES	0x0
+#define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS	0x1
+#define VID_MODE_TYPE_BURST			0x2
+#define VID_MODE_TYPE_MASK			0x3
+
+#define DSI_VID_PKT_SIZE		0x3c
+#define VID_PKT_SIZE(p)			(((p) & 0x3fff) << 0)
+#define VID_PKT_MAX_SIZE		0x3fff
+
+#define DSI_VID_HSA_TIME		0x48
+#define DSI_VID_HBP_TIME		0x4c
+#define DSI_VID_HLINE_TIME		0x50
+#define DSI_VID_VSA_LINES		0x54
+#define DSI_VID_VBP_LINES		0x58
+#define DSI_VID_VFP_LINES		0x5c
+#define DSI_VID_VACTIVE_LINES		0x60
+#define DSI_CMD_MODE_CFG		0x68
+#define MAX_RD_PKT_SIZE_LP		BIT(24)
+#define DCS_LW_TX_LP			BIT(19)
+#define DCS_SR_0P_TX_LP			BIT(18)
+#define DCS_SW_1P_TX_LP			BIT(17)
+#define DCS_SW_0P_TX_LP			BIT(16)
+#define GEN_LW_TX_LP			BIT(14)
+#define GEN_SR_2P_TX_LP			BIT(13)
+#define GEN_SR_1P_TX_LP			BIT(12)
+#define GEN_SR_0P_TX_LP			BIT(11)
+#define GEN_SW_2P_TX_LP			BIT(10)
+#define GEN_SW_1P_TX_LP			BIT(9)
+#define GEN_SW_0P_TX_LP			BIT(8)
+#define EN_ACK_RQST			BIT(1)
+#define EN_TEAR_FX			BIT(0)
+
+#define CMD_MODE_ALL_LP			(MAX_RD_PKT_SIZE_LP | \
+					 DCS_LW_TX_LP | \
+					 DCS_SR_0P_TX_LP | \
+					 DCS_SW_1P_TX_LP | \
+					 DCS_SW_0P_TX_LP | \
+					 GEN_LW_TX_LP | \
+					 GEN_SR_2P_TX_LP | \
+					 GEN_SR_1P_TX_LP | \
+					 GEN_SR_0P_TX_LP | \
+					 GEN_SW_2P_TX_LP | \
+					 GEN_SW_1P_TX_LP | \
+					 GEN_SW_0P_TX_LP)
+
+#define DSI_GEN_HDR			0x6c
+#define GEN_HDATA(data)			(((data) & 0xffff) << 8)
+#define GEN_HDATA_MASK			(0xffff << 8)
+#define GEN_HTYPE(type)			(((type) & 0xff) << 0)
+#define GEN_HTYPE_MASK			0xff
+
+#define DSI_GEN_PLD_DATA		0x70
+
+#define DSI_CMD_PKT_STATUS		0x74
+#define GEN_CMD_EMPTY			BIT(0)
+#define GEN_CMD_FULL			BIT(1)
+#define GEN_PLD_W_EMPTY			BIT(2)
+#define GEN_PLD_W_FULL			BIT(3)
+#define GEN_PLD_R_EMPTY			BIT(4)
+#define GEN_PLD_R_FULL			BIT(5)
+#define GEN_RD_CMD_BUSY			BIT(6)
+
+#define DSI_TO_CNT_CFG			0x78
+#define HSTX_TO_CNT(p)			(((p) & 0xffff) << 16)
+#define LPRX_TO_CNT(p)			((p) & 0xffff)
+
+#define DSI_BTA_TO_CNT			0x8c
+#define DSI_LPCLK_CTRL			0x94
+#define AUTO_CLKLANE_CTRL		BIT(1)
+#define PHY_TXREQUESTCLKHS		BIT(0)
+
+#define DSI_PHY_TMR_LPCLK_CFG		0x98
+#define PHY_CLKHS2LP_TIME(lbcc)		(((lbcc) & 0x3ff) << 16)
+#define PHY_CLKLP2HS_TIME(lbcc)		((lbcc) & 0x3ff)
+
+#define DSI_PHY_TMR_CFG			0x9c
+#define PHY_HS2LP_TIME(lbcc)		(((lbcc) & 0xff) << 24)
+#define PHY_LP2HS_TIME(lbcc)		(((lbcc) & 0xff) << 16)
+#define MAX_RD_TIME(lbcc)		((lbcc) & 0x7fff)
+
+#define DSI_PHY_RSTZ			0xa0
+#define PHY_DISFORCEPLL			0
+#define PHY_ENFORCEPLL			BIT(3)
+#define PHY_DISABLECLK			0
+#define PHY_ENABLECLK			BIT(2)
+#define PHY_RSTZ			0
+#define PHY_UNRSTZ			BIT(1)
+#define PHY_SHUTDOWNZ			0
+#define PHY_UNSHUTDOWNZ			BIT(0)
+
+#define DSI_PHY_IF_CFG			0xa4
+#define N_LANES(n)			((((n) - 1) & 0x3) << 0)
+#define PHY_STOP_WAIT_TIME(cycle)	(((cycle) & 0xff) << 8)
+
+#define DSI_PHY_STATUS			0xb0
+#define LOCK				BIT(0)
+#define STOP_STATE_CLK_LANE		BIT(2)
+
+#define DSI_PHY_TST_CTRL0		0xb4
+#define PHY_TESTCLK			BIT(1)
+#define PHY_UNTESTCLK			0
+#define PHY_TESTCLR			BIT(0)
+#define PHY_UNTESTCLR			0
+
+#define DSI_PHY_TST_CTRL1		0xb8
+#define PHY_TESTEN			BIT(16)
+#define PHY_UNTESTEN			0
+#define PHY_TESTDOUT(n)			(((n) & 0xff) << 8)
+#define PHY_TESTDIN(n)			(((n) & 0xff) << 0)
+
+#define DSI_INT_ST0			0xbc
+#define DSI_INT_ST1			0xc0
+#define DSI_INT_MSK0			0xc4
+#define DSI_INT_MSK1			0xc8
+
+#define PHY_STATUS_TIMEOUT_US		10000
+#define CMD_PKT_STATUS_TIMEOUT_US	20000
+
+struct dw_mipi_dsi {
+	struct drm_bridge bridge;
+	struct mipi_dsi_host dsi_host;
+	struct drm_bridge *panel_bridge;
+	bool is_panel_bridge;
+	struct device *dev;
+	void __iomem *base;
+
+	struct clk *pclk;
+
+	unsigned int lane_mbps; /* per lane */
+	u32 channel;
+	u32 lanes;
+	u32 format;
+	unsigned long mode_flags;
+
+	const struct dw_mipi_dsi_plat_data *plat_data;
+};
+
+/*
+ * The controller should generate 2 frames before
+ * preparing the peripheral.
+ */
+static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode *mode)
+{
+	int refresh, two_frames;
+
+	refresh = drm_mode_vrefresh(mode);
+	two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
+	msleep(two_frames);
+}
+
+static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
+{
+	return container_of(host, struct dw_mipi_dsi, dsi_host);
+}
+
+static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge)
+{
+	return container_of(bridge, struct dw_mipi_dsi, bridge);
+}
+
+static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
+{
+	writel(val, dsi->base + reg);
+}
+
+static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
+{
+	return readl(dsi->base + reg);
+}
+
+static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
+				   struct mipi_dsi_device *device)
+{
+	struct dw_mipi_dsi *dsi = host_to_dsi(host);
+	struct drm_bridge *bridge;
+	struct drm_panel *panel;
+	int ret;
+
+	if (device->lanes > dsi->plat_data->max_data_lanes) {
+		dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
+			device->lanes);
+		return -EINVAL;
+	}
+
+	dsi->lanes = device->lanes;
+	dsi->channel = device->channel;
+	dsi->format = device->format;
+	dsi->mode_flags = device->mode_flags;
+
+	ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0,
+					  &panel, &bridge);
+	if (ret)
+		return ret;
+
+	if (panel) {
+		bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DSI);
+		if (IS_ERR(bridge))
+			return PTR_ERR(bridge);
+		dsi->is_panel_bridge = true;
+	}
+
+	dsi->panel_bridge = bridge;
+
+	return drm_bridge_add(&dsi->bridge);
+}
+
+static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
+				   struct mipi_dsi_device *device)
+{
+	struct dw_mipi_dsi *dsi = host_to_dsi(host);
+
+	if (dsi->is_panel_bridge)
+		drm_panel_bridge_remove(dsi->panel_bridge);
+
+	drm_bridge_remove(&dsi->bridge);
+
+	return 0;
+}
+
+static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
+				   const struct mipi_dsi_msg *msg)
+{
+	bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
+	u32 val = 0;
+
+	if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
+		val |= EN_ACK_RQST;
+	if (lpm)
+		val |= CMD_MODE_ALL_LP;
+
+	dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
+	dsi_write(dsi, DSI_CMD_MODE_CFG, val);
+}
+
+static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
+{
+	int ret;
+	u32 val, mask;
+
+	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
+				 val, !(val & GEN_CMD_FULL), 1000,
+				 CMD_PKT_STATUS_TIMEOUT_US);
+	if (ret < 0) {
+		dev_err(dsi->dev, "failed to get available command FIFO\n");
+		return ret;
+	}
+
+	dsi_write(dsi, DSI_GEN_HDR, hdr_val);
+
+	mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
+	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
+				 val, (val & mask) == mask,
+				 1000, CMD_PKT_STATUS_TIMEOUT_US);
+	if (ret < 0) {
+		dev_err(dsi->dev, "failed to write command FIFO\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi *dsi,
+				       const struct mipi_dsi_msg *msg)
+{
+	const u8 *tx_buf = msg->tx_buf;
+	u16 data = 0;
+	u32 val;
+
+	if (msg->tx_len > 0)
+		data |= tx_buf[0];
+	if (msg->tx_len > 1)
+		data |= tx_buf[1] << 8;
+
+	if (msg->tx_len > 2) {
+		dev_err(dsi->dev, "too long tx buf length %zu for short write\n",
+			msg->tx_len);
+		return -EINVAL;
+	}
+
+	val = GEN_HDATA(data) | GEN_HTYPE(msg->type);
+	return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
+}
+
+static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
+				      const struct mipi_dsi_msg *msg)
+{
+	const u8 *tx_buf = msg->tx_buf;
+	int len = msg->tx_len, pld_data_bytes = sizeof(u32), ret;
+	u32 hdr_val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
+	u32 remainder;
+	u32 val;
+
+	if (msg->tx_len < 3) {
+		dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
+			msg->tx_len);
+		return -EINVAL;
+	}
+
+	while (DIV_ROUND_UP(len, pld_data_bytes)) {
+		if (len < pld_data_bytes) {
+			remainder = 0;
+			memcpy(&remainder, tx_buf, len);
+			dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
+			len = 0;
+		} else {
+			memcpy(&remainder, tx_buf, pld_data_bytes);
+			dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
+			tx_buf += pld_data_bytes;
+			len -= pld_data_bytes;
+		}
+
+		ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
+					 val, !(val & GEN_PLD_W_FULL), 1000,
+					 CMD_PKT_STATUS_TIMEOUT_US);
+		if (ret < 0) {
+			dev_err(dsi->dev,
+				"failed to get available write payload FIFO\n");
+			return ret;
+		}
+	}
+
+	return dw_mipi_dsi_gen_pkt_hdr_write(dsi, hdr_val);
+}
+
+static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
+					 const struct mipi_dsi_msg *msg)
+{
+	struct dw_mipi_dsi *dsi = host_to_dsi(host);
+	int ret;
+
+	/*
+	 * TODO dw drv improvements
+	 * use mipi_dsi_create_packet() instead of all following
+	 * functions and code (no switch cases, no
+	 * dw_mipi_dsi_dcs_short_write(), only the loop in long_write...)
+	 * and use packet.header...
+	 */
+	dw_mipi_message_config(dsi, msg);
+
+	switch (msg->type) {
+	case MIPI_DSI_DCS_SHORT_WRITE:
+	case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
+	case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
+		ret = dw_mipi_dsi_dcs_short_write(dsi, msg);
+		break;
+	case MIPI_DSI_DCS_LONG_WRITE:
+		ret = dw_mipi_dsi_dcs_long_write(dsi, msg);
+		break;
+	default:
+		dev_err(dsi->dev, "unsupported message type 0x%02x\n",
+			msg->type);
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
+	.attach = dw_mipi_dsi_host_attach,
+	.detach = dw_mipi_dsi_host_detach,
+	.transfer = dw_mipi_dsi_host_transfer,
+};
+
+static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
+{
+	u32 val;
+
+	/*
+	 * TODO dw drv improvements
+	 * enabling low power is panel-dependent, we should use the
+	 * panel configuration here...
+	 */
+	val = ENABLE_LOW_POWER;
+
+	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
+		val |= VID_MODE_TYPE_BURST;
+	else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
+		val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
+	else
+		val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
+
+	dsi_write(dsi, DSI_VID_MODE_CFG, val);
+}
+
+static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
+				 unsigned long mode_flags)
+{
+	dsi_write(dsi, DSI_PWR_UP, RESET);
+
+	if (mode_flags & MIPI_DSI_MODE_VIDEO) {
+		dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
+		dw_mipi_dsi_video_mode_config(dsi);
+		dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
+	} else {
+		dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
+	}
+
+	dsi_write(dsi, DSI_PWR_UP, POWERUP);
+}
+
+static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
+{
+	dsi_write(dsi, DSI_PWR_UP, RESET);
+	dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
+}
+
+static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
+{
+	/*
+	 * The maximum permitted escape clock is 20MHz and it is derived from
+	 * lanebyteclk, which is running at "lane_mbps / 8".  Thus we want:
+	 *
+	 *     (lane_mbps >> 3) / esc_clk_division < 20
+	 * which is:
+	 *     (lane_mbps >> 3) / 20 > esc_clk_division
+	 */
+	u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
+
+	dsi_write(dsi, DSI_PWR_UP, RESET);
+
+	/*
+	 * TODO dw drv improvements
+	 * timeout clock division should be computed with the
+	 * high speed transmission counter timeout and byte lane...
+	 */
+	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
+		  TX_ESC_CLK_DIVIDSION(esc_clk_division));
+}
+
+static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
+				   struct drm_display_mode *mode)
+{
+	u32 val = 0, color = 0;
+
+	switch (dsi->format) {
+	case MIPI_DSI_FMT_RGB888:
+		color = DPI_COLOR_CODING_24BIT;
+		break;
+	case MIPI_DSI_FMT_RGB666:
+		color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
+		break;
+	case MIPI_DSI_FMT_RGB666_PACKED:
+		color = DPI_COLOR_CODING_18BIT_1;
+		break;
+	case MIPI_DSI_FMT_RGB565:
+		color = DPI_COLOR_CODING_16BIT_1;
+		break;
+	}
+
+	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
+		val |= VSYNC_ACTIVE_LOW;
+	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
+		val |= HSYNC_ACTIVE_LOW;
+
+	dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
+	dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
+	dsi_write(dsi, DSI_DPI_CFG_POL, val);
+	/*
+	 * TODO dw drv improvements
+	 * largest packet sizes during hfp or during vsa/vpb/vfp
+	 * should be computed according to byte lane, lane number and only
+	 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
+	 */
+	dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
+		  | INVACT_LPCMD_TIME(4));
+}
+
+static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
+{
+	dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
+}
+
+static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
+					    struct drm_display_mode *mode)
+{
+	/*
+	 * TODO dw drv improvements
+	 * only burst mode is supported here. For non-burst video modes,
+	 * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
+	 * DSI_VNPCR.NPSIZE... especially because this driver supports
+	 * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
+	 */
+	dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
+}
+
+static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
+{
+	/*
+	 * TODO dw drv improvements
+	 * compute high speed transmission counter timeout according
+	 * to the timeout clock division (TO_CLK_DIVIDSION) and byte lane...
+	 */
+	dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
+	/*
+	 * TODO dw drv improvements
+	 * the Bus-Turn-Around Timeout Counter should be computed
+	 * according to byte lane...
+	 */
+	dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
+	dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
+}
+
+/* Get lane byte clock cycles. */
+static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
+					   struct drm_display_mode *mode,
+					   u32 hcomponent)
+{
+	u32 frac, lbcc;
+
+	lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
+
+	frac = lbcc % mode->clock;
+	lbcc = lbcc / mode->clock;
+	if (frac)
+		lbcc++;
+
+	return lbcc;
+}
+
+static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
+					  struct drm_display_mode *mode)
+{
+	u32 htotal, hsa, hbp, lbcc;
+
+	htotal = mode->htotal;
+	hsa = mode->hsync_end - mode->hsync_start;
+	hbp = mode->htotal - mode->hsync_end;
+
+	/*
+	 * TODO dw drv improvements
+	 * computations below may be improved...
+	 */
+	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
+	dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
+
+	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
+	dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
+
+	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
+	dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
+}
+
+static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
+					       struct drm_display_mode *mode)
+{
+	u32 vactive, vsa, vfp, vbp;
+
+	vactive = mode->vdisplay;
+	vsa = mode->vsync_end - mode->vsync_start;
+	vfp = mode->vsync_start - mode->vdisplay;
+	vbp = mode->vtotal - mode->vsync_end;
+
+	dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
+	dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
+	dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
+	dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
+}
+
+static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
+{
+	/*
+	 * TODO dw drv improvements
+	 * data & clock lane timers should be computed according to panel
+	 * blankings and to the automatic clock lane control mode...
+	 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
+	 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
+	 */
+	dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40)
+		  | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
+
+	dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
+		  | PHY_CLKLP2HS_TIME(0x40));
+}
+
+static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
+{
+	/*
+	 * TODO dw drv improvements
+	 * stop wait time should be the maximum between host dsi
+	 * and panel stop wait times
+	 */
+	dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
+		  N_LANES(dsi->lanes));
+}
+
+static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
+{
+	/* Clear PHY state */
+	dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
+		  | PHY_RSTZ | PHY_SHUTDOWNZ);
+	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
+	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
+	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
+}
+
+static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
+{
+	u32 val;
+	int ret;
+
+	dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
+		  PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
+
+	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
+				 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
+	if (ret < 0)
+		DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
+
+	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
+				 val, val & STOP_STATE_CLK_LANE, 1000,
+				 PHY_STATUS_TIMEOUT_US);
+	if (ret < 0)
+		DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
+}
+
+static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
+{
+	dsi_read(dsi, DSI_INT_ST0);
+	dsi_read(dsi, DSI_INT_ST1);
+	dsi_write(dsi, DSI_INT_MSK0, 0);
+	dsi_write(dsi, DSI_INT_MSK1, 0);
+}
+
+static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
+{
+	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
+
+	/*
+	 * Switch to command mode before panel-bridge post_disable &
+	 * panel unprepare.
+	 * Note: panel-bridge disable & panel disable has been called
+	 * before by the drm framework.
+	 */
+	dw_mipi_dsi_set_mode(dsi, 0);
+
+	/*
+	 * TODO Only way found to call panel-bridge post_disable &
+	 * panel unprepare before the dsi "final" disable...
+	 * This needs to be fixed in the drm_bridge framework and the API
+	 * needs to be updated to manage our own call chains...
+	 */
+	dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge);
+
+	dw_mipi_dsi_disable(dsi);
+	clk_disable_unprepare(dsi->pclk);
+	pm_runtime_put(dsi->dev);
+}
+
+void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
+				 struct drm_display_mode *mode,
+				 struct drm_display_mode *adjusted_mode)
+{
+	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
+	const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
+	void *priv_data = dsi->plat_data->priv_data;
+	int ret;
+
+	clk_prepare_enable(dsi->pclk);
+
+	ret = phy_ops->get_lane_mbps(priv_data, mode, dsi->mode_flags,
+				     dsi->lanes, dsi->format, &dsi->lane_mbps);
+	if (ret)
+		DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n");
+
+	pm_runtime_get_sync(dsi->dev);
+	dw_mipi_dsi_init(dsi);
+	dw_mipi_dsi_dpi_config(dsi, mode);
+	dw_mipi_dsi_packet_handler_config(dsi);
+	dw_mipi_dsi_video_mode_config(dsi);
+	dw_mipi_dsi_video_packet_config(dsi, mode);
+	dw_mipi_dsi_command_mode_config(dsi);
+	dw_mipi_dsi_line_timer_config(dsi, mode);
+	dw_mipi_dsi_vertical_timing_config(dsi, mode);
+
+	dw_mipi_dsi_dphy_init(dsi);
+	dw_mipi_dsi_dphy_timing_config(dsi);
+	dw_mipi_dsi_dphy_interface_config(dsi);
+
+	dw_mipi_dsi_clear_err(dsi);
+
+	ret = phy_ops->init(priv_data);
+	if (ret)
+		DRM_DEBUG_DRIVER("Phy init() failed\n");
+
+	dw_mipi_dsi_dphy_enable(dsi);
+
+	dw_mipi_dsi_wait_for_two_frames(mode);
+
+	/* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
+	dw_mipi_dsi_set_mode(dsi, 0);
+}
+
+static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge)
+{
+	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
+
+	/* Switch to video mode for panel-bridge enable & panel enable */
+	dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
+}
+
+static enum drm_mode_status
+dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
+			      const struct drm_display_mode *mode)
+{
+	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
+	const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
+	enum drm_mode_status mode_status = MODE_OK;
+
+	if (pdata->mode_valid)
+		mode_status = pdata->mode_valid(pdata->priv_data, mode);
+
+	return mode_status;
+}
+
+static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge)
+{
+	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
+
+	if (!bridge->encoder) {
+		DRM_ERROR("Parent encoder object not found\n");
+		return -ENODEV;
+	}
+
+	/* Set the encoder type as caller does not know it */
+	bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI;
+
+	/* Attach the panel-bridge to the dsi bridge */
+	return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge);
+}
+
+static struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = {
+	.mode_set     = dw_mipi_dsi_bridge_mode_set,
+	.enable	      = dw_mipi_dsi_bridge_enable,
+	.post_disable = dw_mipi_dsi_bridge_post_disable,
+	.mode_valid   = dw_mipi_dsi_bridge_mode_valid,
+	.attach	      = dw_mipi_dsi_bridge_attach,
+};
+
+static struct dw_mipi_dsi *
+__dw_mipi_dsi_probe(struct platform_device *pdev,
+		    const struct dw_mipi_dsi_plat_data *plat_data)
+{
+	struct device *dev = &pdev->dev;
+	struct reset_control *apb_rst;
+	struct dw_mipi_dsi *dsi;
+	struct resource *res;
+	int ret;
+
+	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
+	if (!dsi)
+		return ERR_PTR(-ENOMEM);
+
+	dsi->dev = dev;
+	dsi->plat_data = plat_data;
+
+	if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps) {
+		DRM_ERROR("Phy not properly configured\n");
+		return ERR_PTR(-ENODEV);
+	}
+
+	if (!plat_data->base) {
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+		if (!res)
+			return ERR_PTR(-ENODEV);
+
+		dsi->base = devm_ioremap_resource(dev, res);
+		if (IS_ERR(dsi->base))
+			return ERR_PTR(-ENODEV);
+
+	} else {
+		dsi->base = plat_data->base;
+	}
+
+	dsi->pclk = devm_clk_get(dev, "pclk");
+	if (IS_ERR(dsi->pclk)) {
+		ret = PTR_ERR(dsi->pclk);
+		dev_err(dev, "Unable to get pclk: %d\n", ret);
+		return ERR_PTR(ret);
+	}
+
+	/*
+	 * Note that the reset was not defined in the initial device tree, so
+	 * we have to be prepared for it not being found.
+	 */
+	apb_rst = devm_reset_control_get(dev, "apb");
+	if (IS_ERR(apb_rst)) {
+		ret = PTR_ERR(apb_rst);
+		if (ret == -ENOENT) {
+			apb_rst = NULL;
+		} else {
+			dev_err(dev, "Unable to get reset control: %d\n", ret);
+			return ERR_PTR(ret);
+		}
+	}
+
+	if (apb_rst) {
+		ret = clk_prepare_enable(dsi->pclk);
+		if (ret) {
+			dev_err(dev, "%s: Failed to enable pclk\n", __func__);
+			return ERR_PTR(ret);
+		}
+
+		reset_control_assert(apb_rst);
+		usleep_range(10, 20);
+		reset_control_deassert(apb_rst);
+
+		clk_disable_unprepare(dsi->pclk);
+	}
+
+	pm_runtime_enable(dev);
+
+	dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
+	dsi->dsi_host.dev = dev;
+	ret = mipi_dsi_host_register(&dsi->dsi_host);
+	if (ret) {
+		dev_err(dev, "Failed to register MIPI host: %d\n", ret);
+		return ERR_PTR(ret);
+	}
+
+	dsi->bridge.driver_private = dsi;
+	dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs;
+#ifdef CONFIG_OF
+	dsi->bridge.of_node = pdev->dev.of_node;
+#endif
+
+	dev_set_drvdata(dev, dsi);
+
+	return dsi;
+}
+
+static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
+{
+	pm_runtime_disable(dsi->dev);
+}
+
+/*
+ * Probe/remove API, used from platforms based on the DRM bridge API.
+ */
+int dw_mipi_dsi_probe(struct platform_device *pdev,
+		      const struct dw_mipi_dsi_plat_data *plat_data)
+{
+	struct dw_mipi_dsi *dsi;
+
+	dsi = __dw_mipi_dsi_probe(pdev, plat_data);
+	if (IS_ERR(dsi))
+		return PTR_ERR(dsi);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe);
+
+void dw_mipi_dsi_remove(struct platform_device *pdev)
+{
+	struct dw_mipi_dsi *dsi = platform_get_drvdata(pdev);
+
+	mipi_dsi_host_unregister(&dsi->dsi_host);
+
+	__dw_mipi_dsi_remove(dsi);
+}
+EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove);
+
+/*
+ * Bind/unbind API, used from platforms based on the component framework.
+ */
+int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
+		     const struct dw_mipi_dsi_plat_data *plat_data)
+{
+	struct dw_mipi_dsi *dsi;
+	int ret;
+
+	dsi = __dw_mipi_dsi_probe(pdev, plat_data);
+	if (IS_ERR(dsi))
+		return PTR_ERR(dsi);
+
+	ret = drm_bridge_attach(encoder, &dsi->bridge, NULL);
+	if (ret) {
+		dw_mipi_dsi_remove(pdev);
+		DRM_ERROR("Failed to initialize bridge with drm\n");
+		return ret;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
+
+void dw_mipi_dsi_unbind(struct device *dev)
+{
+	struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
+
+	__dw_mipi_dsi_remove(dsi);
+}
+EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
+
+MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
+MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
+MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:dw-mipi-dsi");
diff --git a/include/drm/bridge/dw_mipi_dsi.h b/include/drm/bridge/dw_mipi_dsi.h
new file mode 100644
index 0000000..9b30fec
--- /dev/null
+++ b/include/drm/bridge/dw_mipi_dsi.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ *
+ * Authors: Philippe Cornu <philippe.cornu@st.com>
+ *          Yannick Fertre <yannick.fertre@st.com>
+ *
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+#ifndef __DW_MIPI_DSI__
+#define __DW_MIPI_DSI__
+
+struct dw_mipi_dsi_phy_ops {
+	int (*init)(void *priv_data);
+	int (*get_lane_mbps)(void *priv_data, struct drm_display_mode *mode,
+			     unsigned long mode_flags, u32 lanes, u32 format,
+			     unsigned int *lane_mbps);
+};
+
+struct dw_mipi_dsi_plat_data {
+	void __iomem *base;
+	unsigned int max_data_lanes;
+
+	enum drm_mode_status (*mode_valid)(void *priv_data,
+					   const struct drm_display_mode *mode);
+
+	const struct dw_mipi_dsi_phy_ops *phy_ops;
+
+	void *priv_data;
+};
+
+int dw_mipi_dsi_probe(struct platform_device *pdev,
+		      const struct dw_mipi_dsi_plat_data *plat_data);
+void dw_mipi_dsi_remove(struct platform_device *pdev);
+int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
+		     const struct dw_mipi_dsi_plat_data *plat_data);
+void dw_mipi_dsi_unbind(struct device *dev);
+
+#endif /* __DW_MIPI_DSI__ */
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v5 5/7] dt-bindings: display: stm32: remove st-display-subsystem parent node requirement
  2017-07-03  8:41 ` Philippe CORNU
@ 2017-07-03  8:41   ` Philippe CORNU
  -1 siblings, 0 replies; 24+ messages in thread
From: Philippe CORNU @ 2017-07-03  8:41 UTC (permalink / raw)
  To: Alexandre Torgue, Thierry Reding, David Airlie, Maxime Coquelin,
	Russell King, Mark Rutland, Rob Herring, Arnd Bergmann,
	Benjamin Gaignard, Yannick Fertre, Neil Armstrong, Archit Taneja,
	Eric Anholt, Chris Zhong, Andrzej Hajda, Xinliang Liu,
	zourongrong, Xinwei Kong, Chen Feng, Mark Yao
  Cc: linux-arm-kernel, devicetree, Philippe Cornu, Fabien Dessenne,
	dri-devel, Mickael Reulier, Vincent Abriou, Gabriel Fernandez,
	Ludovic Barre

There is no need anymore to have a "st-display-subsystem" parent node
in the device tree for the ltdc.

Signed-off-by: Philippe CORNU <philippe.cornu@st.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/display/st,stm32-ltdc.txt | 1 -
 1 file changed, 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
index 8e14769..90a8459 100644
--- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
+++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
@@ -1,7 +1,6 @@
 * STMicroelectronics STM32 lcd-tft display controller
 
 - ltdc: lcd-tft display controller host
-  must be a sub-node of st-display-subsystem
   Required properties:
   - compatible: "st,stm32-ltdc"
   - reg: Physical base address of the IP registers and length of memory mapped region.
-- 
1.9.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v5 5/7] dt-bindings: display: stm32: remove st-display-subsystem parent node requirement
@ 2017-07-03  8:41   ` Philippe CORNU
  0 siblings, 0 replies; 24+ messages in thread
From: Philippe CORNU @ 2017-07-03  8:41 UTC (permalink / raw)
  To: linux-arm-kernel

There is no need anymore to have a "st-display-subsystem" parent node
in the device tree for the ltdc.

Signed-off-by: Philippe CORNU <philippe.cornu@st.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/display/st,stm32-ltdc.txt | 1 -
 1 file changed, 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
index 8e14769..90a8459 100644
--- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
+++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
@@ -1,7 +1,6 @@
 * STMicroelectronics STM32 lcd-tft display controller
 
 - ltdc: lcd-tft display controller host
-  must be a sub-node of st-display-subsystem
   Required properties:
   - compatible: "st,stm32-ltdc"
   - reg: Physical base address of the IP registers and length of memory mapped region.
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v5 6/7] dt-bindings: display: stm32: Add DSI controller
  2017-07-03  8:41 ` Philippe CORNU
@ 2017-07-03  8:41   ` Philippe CORNU
  -1 siblings, 0 replies; 24+ messages in thread
From: Philippe CORNU @ 2017-07-03  8:41 UTC (permalink / raw)
  To: Alexandre Torgue, Thierry Reding, David Airlie, Maxime Coquelin,
	Russell King, Mark Rutland, Rob Herring, Arnd Bergmann,
	Benjamin Gaignard, Yannick Fertre, Neil Armstrong, Archit Taneja,
	Eric Anholt, Chris Zhong, Andrzej Hajda, Xinliang Liu,
	zourongrong, Xinwei Kong, Chen Feng, Mark Yao
  Cc: linux-arm-kernel, devicetree, Philippe Cornu, Fabien Dessenne,
	dri-devel, Mickael Reulier, Vincent Abriou, Gabriel Fernandez,
	Ludovic Barre

This patch adds documentation of device tree bindings for the STM32 DSI
controller based on the Synopsys DesignWare MIPI DSI host controller.

Signed-off-by: Philippe CORNU <philippe.cornu@st.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/display/st,stm32-ltdc.txt  | 104 ++++++++++++++++++++-
 1 file changed, 103 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
index 90a8459..74b5ac7 100644
--- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
+++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
@@ -12,8 +12,40 @@
   Required nodes:
     - Video port for RGB output.
 
-Example:
+* STMicroelectronics STM32 DSI controller specific extensions to Synopsys
+  DesignWare MIPI DSI host controller
 
+The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI
+DSI host controller. For all mandatory properties & nodes, please refer
+to the related documentation in [5].
+
+Mandatory properties specific to STM32 DSI:
+- #address-cells: Should be <1>.
+- #size-cells: Should be <0>.
+- compatible: "st,stm32-dsi".
+- clock-names:
+  - phy pll reference clock string name, must be "ref".
+- resets: see [5].
+- reset-names: see [5].
+
+Mandatory nodes specific to STM32 DSI:
+- ports: A node containing DSI input & output port nodes with endpoint
+  definitions as documented in [3] & [4].
+  - port@0: DSI input port node, connected to the ltdc rgb output port.
+  - port@1: DSI output port node, connected to a panel or a bridge input port.
+- panel or bridge node: A node containing the panel or bridge description as
+  documented in [6].
+  - port: panel or bridge port node, connected to the DSI output port (port@1).
+
+Note: You can find more documentation in the following references
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/reset/reset.txt
+[3] Documentation/devicetree/bindings/media/video-interfaces.txt
+[4] Documentation/devicetree/bindings/graph.txt
+[5] Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
+[6] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
+
+Example 1: RGB panel
 / {
 	...
 	soc {
@@ -33,3 +65,73 @@ Example:
 		};
 	};
 };
+
+Example 2: DSI panel
+
+/ {
+	...
+	soc {
+	...
+		ltdc: display-controller@40016800 {
+			compatible = "st,stm32-ltdc";
+			reg = <0x40016800 0x200>;
+			interrupts = <88>, <89>;
+			resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
+			clocks = <&rcc 1 CLK_LCD>;
+			clock-names = "lcd";
+
+			port {
+				ltdc_out_dsi: endpoint {
+					remote-endpoint = <&dsi_in>;
+				};
+			};
+		};
+
+
+		dsi: dsi@40016c00 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-dsi";
+			reg = <0x40016c00 0x800>;
+			clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
+			clock-names = "ref", "pclk";
+			resets = <&rcc STM32F4_APB2_RESET(DSI)>;
+			reset-names = "apb";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					dsi_in: endpoint {
+						remote-endpoint = <&ltdc_out_dsi>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					dsi_out: endpoint {
+						remote-endpoint = <&dsi_in_panel>;
+					};
+				};
+
+			};
+
+			panel-dsi@0 {
+				reg = <0>; /* dsi virtual channel (0..3) */
+				compatible = ...;
+				enable-gpios = ...;
+
+				port {
+					dsi_in_panel: endpoint {
+						remote-endpoint = <&dsi_out>;
+					};
+				};
+
+			};
+
+		};
+
+	};
+};
-- 
1.9.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v5 6/7] dt-bindings: display: stm32: Add DSI controller
@ 2017-07-03  8:41   ` Philippe CORNU
  0 siblings, 0 replies; 24+ messages in thread
From: Philippe CORNU @ 2017-07-03  8:41 UTC (permalink / raw)
  To: linux-arm-kernel

This patch adds documentation of device tree bindings for the STM32 DSI
controller based on the Synopsys DesignWare MIPI DSI host controller.

Signed-off-by: Philippe CORNU <philippe.cornu@st.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/display/st,stm32-ltdc.txt  | 104 ++++++++++++++++++++-
 1 file changed, 103 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
index 90a8459..74b5ac7 100644
--- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
+++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
@@ -12,8 +12,40 @@
   Required nodes:
     - Video port for RGB output.
 
-Example:
+* STMicroelectronics STM32 DSI controller specific extensions to Synopsys
+  DesignWare MIPI DSI host controller
 
+The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI
+DSI host controller. For all mandatory properties & nodes, please refer
+to the related documentation in [5].
+
+Mandatory properties specific to STM32 DSI:
+- #address-cells: Should be <1>.
+- #size-cells: Should be <0>.
+- compatible: "st,stm32-dsi".
+- clock-names:
+  - phy pll reference clock string name, must be "ref".
+- resets: see [5].
+- reset-names: see [5].
+
+Mandatory nodes specific to STM32 DSI:
+- ports: A node containing DSI input & output port nodes with endpoint
+  definitions as documented in [3] & [4].
+  - port at 0: DSI input port node, connected to the ltdc rgb output port.
+  - port at 1: DSI output port node, connected to a panel or a bridge input port.
+- panel or bridge node: A node containing the panel or bridge description as
+  documented in [6].
+  - port: panel or bridge port node, connected to the DSI output port (port at 1).
+
+Note: You can find more documentation in the following references
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/reset/reset.txt
+[3] Documentation/devicetree/bindings/media/video-interfaces.txt
+[4] Documentation/devicetree/bindings/graph.txt
+[5] Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
+[6] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
+
+Example 1: RGB panel
 / {
 	...
 	soc {
@@ -33,3 +65,73 @@ Example:
 		};
 	};
 };
+
+Example 2: DSI panel
+
+/ {
+	...
+	soc {
+	...
+		ltdc: display-controller at 40016800 {
+			compatible = "st,stm32-ltdc";
+			reg = <0x40016800 0x200>;
+			interrupts = <88>, <89>;
+			resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
+			clocks = <&rcc 1 CLK_LCD>;
+			clock-names = "lcd";
+
+			port {
+				ltdc_out_dsi: endpoint {
+					remote-endpoint = <&dsi_in>;
+				};
+			};
+		};
+
+
+		dsi: dsi at 40016c00 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-dsi";
+			reg = <0x40016c00 0x800>;
+			clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
+			clock-names = "ref", "pclk";
+			resets = <&rcc STM32F4_APB2_RESET(DSI)>;
+			reset-names = "apb";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port at 0 {
+					reg = <0>;
+					dsi_in: endpoint {
+						remote-endpoint = <&ltdc_out_dsi>;
+					};
+				};
+
+				port at 1 {
+					reg = <1>;
+					dsi_out: endpoint {
+						remote-endpoint = <&dsi_in_panel>;
+					};
+				};
+
+			};
+
+			panel-dsi at 0 {
+				reg = <0>; /* dsi virtual channel (0..3) */
+				compatible = ...;
+				enable-gpios = ...;
+
+				port {
+					dsi_in_panel: endpoint {
+						remote-endpoint = <&dsi_out>;
+					};
+				};
+
+			};
+
+		};
+
+	};
+};
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v5 7/7] drm/stm: Add STM32 DSI controller driver
  2017-07-03  8:41 ` Philippe CORNU
@ 2017-07-03  8:41   ` Philippe CORNU
  -1 siblings, 0 replies; 24+ messages in thread
From: Philippe CORNU @ 2017-07-03  8:41 UTC (permalink / raw)
  To: Alexandre Torgue, Thierry Reding, David Airlie, Maxime Coquelin,
	Russell King, Mark Rutland, Rob Herring, Arnd Bergmann,
	Benjamin Gaignard, Yannick Fertre, Neil Armstrong, Archit Taneja,
	Eric Anholt, Chris Zhong, Andrzej Hajda, Xinliang Liu,
	zourongrong, Xinwei Kong, Chen Feng, Mark Yao
  Cc: linux-arm-kernel, devicetree, Philippe Cornu, Fabien Dessenne,
	dri-devel, Mickael Reulier, Vincent Abriou, Gabriel Fernandez,
	Ludovic Barre

Add the STM32 DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.

Signed-off-by: Philippe CORNU <philippe.cornu@st.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Archit Taneja <architt@codeaurora.org>
---
 drivers/gpu/drm/stm/Kconfig           |   7 +
 drivers/gpu/drm/stm/Makefile          |   2 +
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 352 ++++++++++++++++++++++++++++++++++
 3 files changed, 361 insertions(+)
 create mode 100644 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c

diff --git a/drivers/gpu/drm/stm/Kconfig b/drivers/gpu/drm/stm/Kconfig
index 4b88223..f9462bc 100644
--- a/drivers/gpu/drm/stm/Kconfig
+++ b/drivers/gpu/drm/stm/Kconfig
@@ -14,3 +14,10 @@ config DRM_STM
 	  STMicroelectronics STM32 MCUs.
 	  To compile this driver as a module, choose M here: the module
 	  will be called stm-drm.
+
+config DRM_STM_DSI
+	tristate "STMicroelectronics specific extensions for Synopsys MIPI DSI"
+	depends on DRM_STM
+	select DRM_DW_MIPI_DSI
+	help
+	  Choose this option for MIPI DSI support on STMicroelectronics SoC.
diff --git a/drivers/gpu/drm/stm/Makefile b/drivers/gpu/drm/stm/Makefile
index a09ecf4..d883adc 100644
--- a/drivers/gpu/drm/stm/Makefile
+++ b/drivers/gpu/drm/stm/Makefile
@@ -2,4 +2,6 @@ stm-drm-y := \
 	drv.o \
 	ltdc.o
 
+obj-$(CONFIG_DRM_STM_DSI) += dw_mipi_dsi-stm.o
+
 obj-$(CONFIG_DRM_STM) += stm-drm.o
diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
new file mode 100644
index 0000000..16ae00e
--- /dev/null
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -0,0 +1,352 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ *
+ * Authors: Philippe Cornu <philippe.cornu@st.com>
+ *          Yannick Fertre <yannick.fertre@st.com>
+ *
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+#include <linux/clk.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <drm/drmP.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/bridge/dw_mipi_dsi.h>
+#include <video/mipi_display.h>
+
+/* DSI wrapper register & bit definitions */
+/* Note: registers are named as in the Reference Manual */
+#define DSI_WCFGR	0x0400		/* Wrapper ConFiGuration Reg */
+#define WCFGR_DSIM	BIT(0)		/* DSI Mode */
+#define WCFGR_COLMUX	GENMASK(3, 1)	/* COLor MUltipleXing */
+
+#define DSI_WCR		0x0404		/* Wrapper Control Reg */
+#define WCR_DSIEN	BIT(3)		/* DSI ENable */
+
+#define DSI_WISR	0x040C		/* Wrapper Interrupt and Status Reg */
+#define WISR_PLLLS	BIT(8)		/* PLL Lock Status */
+#define WISR_RRS	BIT(12)		/* Regulator Ready Status */
+
+#define DSI_WPCR0	0x0418		/* Wrapper Phy Conf Reg 0 */
+#define WPCR0_UIX4	GENMASK(5, 0)	/* Unit Interval X 4 */
+#define WPCR0_TDDL	BIT(16)		/* Turn Disable Data Lanes */
+
+#define DSI_WRPCR	0x0430		/* Wrapper Regulator & Pll Ctrl Reg */
+#define WRPCR_PLLEN	BIT(0)		/* PLL ENable */
+#define WRPCR_NDIV	GENMASK(8, 2)	/* pll loop DIVision Factor */
+#define WRPCR_IDF	GENMASK(14, 11)	/* pll Input Division Factor */
+#define WRPCR_ODF	GENMASK(17, 16)	/* pll Output Division Factor */
+#define WRPCR_REGEN	BIT(24)		/* REGulator ENable */
+#define WRPCR_BGREN	BIT(28)		/* BandGap Reference ENable */
+#define IDF_MIN		1
+#define IDF_MAX		7
+#define NDIV_MIN	10
+#define NDIV_MAX	125
+#define ODF_MIN		1
+#define ODF_MAX		8
+
+/* dsi color format coding according to the datasheet */
+enum dsi_color {
+	DSI_RGB565_CONF1,
+	DSI_RGB565_CONF2,
+	DSI_RGB565_CONF3,
+	DSI_RGB666_CONF1,
+	DSI_RGB666_CONF2,
+	DSI_RGB888,
+};
+
+#define LANE_MIN_KBPS	31250
+#define LANE_MAX_KBPS	500000
+
+/* Sleep & timeout for regulator on/off, pll lock/unlock & fifo empty */
+#define SLEEP_US	1000
+#define TIMEOUT_US	200000
+
+struct dw_mipi_dsi_stm {
+	void __iomem *base;
+	struct clk *pllref_clk;
+};
+
+static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val)
+{
+	writel(val, dsi->base + reg);
+}
+
+static inline u32 dsi_read(struct dw_mipi_dsi_stm *dsi, u32 reg)
+{
+	return readl(dsi->base + reg);
+}
+
+static inline void dsi_set(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask)
+{
+	dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
+}
+
+static inline void dsi_clear(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask)
+{
+	dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask);
+}
+
+static inline void dsi_update_bits(struct dw_mipi_dsi_stm *dsi, u32 reg,
+				   u32 mask, u32 val)
+{
+	dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
+}
+
+static enum dsi_color dsi_color_from_mipi(enum mipi_dsi_pixel_format fmt)
+{
+	switch (fmt) {
+	case MIPI_DSI_FMT_RGB888:
+		return DSI_RGB888;
+	case MIPI_DSI_FMT_RGB666:
+		return DSI_RGB666_CONF2;
+	case MIPI_DSI_FMT_RGB666_PACKED:
+		return DSI_RGB666_CONF1;
+	case MIPI_DSI_FMT_RGB565:
+		return DSI_RGB565_CONF1;
+	default:
+		DRM_DEBUG_DRIVER("MIPI color invalid, so we use rgb888\n");
+	}
+	return DSI_RGB888;
+}
+
+static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf)
+{
+	/* prevent from division by 0 */
+	if (idf * odf)
+		return DIV_ROUND_CLOSEST(clkin_khz * ndiv, idf * odf);
+
+	return 0;
+}
+
+static int dsi_pll_get_params(int clkin_khz, int clkout_khz,
+			      int *idf, int *ndiv, int *odf)
+{
+	int i, o, n, n_min, n_max;
+	int fvco_min, fvco_max, delta, best_delta; /* all in khz */
+
+	/* Early checks preventing division by 0 & odd results */
+	if ((clkin_khz <= 0) || (clkout_khz <= 0))
+		return -EINVAL;
+
+	fvco_min = LANE_MIN_KBPS * 2 * ODF_MAX;
+	fvco_max = LANE_MAX_KBPS * 2 * ODF_MIN;
+
+	best_delta = 1000000; /* big started value (1000000khz) */
+
+	for (i = IDF_MIN; i <= IDF_MAX; i++) {
+		/* Compute ndiv range according to Fvco */
+		n_min = ((fvco_min * i) / (2 * clkin_khz)) + 1;
+		n_max = (fvco_max * i) / (2 * clkin_khz);
+
+		/* No need to continue idf loop if we reach ndiv max */
+		if (n_min >= NDIV_MAX)
+			break;
+
+		/* Clamp ndiv to valid values */
+		if (n_min < NDIV_MIN)
+			n_min = NDIV_MIN;
+		if (n_max > NDIV_MAX)
+			n_max = NDIV_MAX;
+
+		for (o = ODF_MIN; o <= ODF_MAX; o *= 2) {
+			n = DIV_ROUND_CLOSEST(i * o * clkout_khz, clkin_khz);
+			/* Check ndiv according to vco range */
+			if ((n < n_min) || (n > n_max))
+				continue;
+			/* Check if new delta is better & saves parameters */
+			delta = dsi_pll_get_clkout_khz(clkin_khz, i, n, o) -
+				clkout_khz;
+			if (delta < 0)
+				delta = -delta;
+			if (delta < best_delta) {
+				*idf = i;
+				*ndiv = n;
+				*odf = o;
+				best_delta = delta;
+			}
+			/* fast return in case of "perfect result" */
+			if (!delta)
+				return 0;
+		}
+	}
+
+	return 0;
+}
+
+static int dw_mipi_dsi_phy_init(void *priv_data)
+{
+	struct dw_mipi_dsi_stm *dsi = priv_data;
+	u32 val;
+	int ret;
+
+	/* Enable the regulator */
+	dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
+	ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS,
+				 SLEEP_US, TIMEOUT_US);
+	if (ret)
+		DRM_DEBUG_DRIVER("!TIMEOUT! waiting REGU, let's continue\n");
+
+	/* Enable the DSI PLL & wait for its lock */
+	dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN);
+	ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
+				 SLEEP_US, TIMEOUT_US);
+	if (ret)
+		DRM_DEBUG_DRIVER("!TIMEOUT! waiting PLL, let's continue\n");
+
+	/* Enable the DSI wrapper */
+	dsi_set(dsi, DSI_WCR, WCR_DSIEN);
+
+	return 0;
+}
+
+static int
+dw_mipi_dsi_get_lane_mbps(void *priv_data, struct drm_display_mode *mode,
+			  unsigned long mode_flags, u32 lanes, u32 format,
+			  unsigned int *lane_mbps)
+{
+	struct dw_mipi_dsi_stm *dsi = priv_data;
+	unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
+	int ret, bpp;
+	u32 val;
+
+	pll_in_khz = (unsigned int)(clk_get_rate(dsi->pllref_clk) / 1000);
+
+	/* Compute requested pll out */
+	bpp = mipi_dsi_pixel_format_to_bpp(format);
+	pll_out_khz = mode->clock * bpp / lanes;
+	/* Add 20% to pll out to be higher than pixel bw (burst mode only) */
+	pll_out_khz = (pll_out_khz * 12) / 10;
+	if (pll_out_khz > LANE_MAX_KBPS) {
+		pll_out_khz = LANE_MAX_KBPS;
+		DRM_WARN("Warning max phy mbps is used\n");
+	}
+	if (pll_out_khz < LANE_MIN_KBPS) {
+		pll_out_khz = LANE_MIN_KBPS;
+		DRM_WARN("Warning min phy mbps is used\n");
+	}
+
+	/* Compute best pll parameters */
+	idf = 0;
+	ndiv = 0;
+	odf = 0;
+	ret = dsi_pll_get_params(pll_in_khz, pll_out_khz, &idf, &ndiv, &odf);
+	if (ret)
+		DRM_WARN("Warning dsi_pll_get_params(): bad params\n");
+
+	/* Get the adjusted pll out value */
+	pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
+
+	/* Set the PLL division factors */
+	dsi_update_bits(dsi, DSI_WRPCR,	WRPCR_NDIV | WRPCR_IDF | WRPCR_ODF,
+			(ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16));
+
+	/* Compute uix4 & set the bit period in high-speed mode */
+	val = 4000000 / pll_out_khz;
+	dsi_update_bits(dsi, DSI_WPCR0, WPCR0_UIX4, val);
+
+	/* Select video mode by resetting DSIM bit */
+	dsi_clear(dsi, DSI_WCFGR, WCFGR_DSIM);
+
+	/* Select the color coding */
+	dsi_update_bits(dsi, DSI_WCFGR, WCFGR_COLMUX,
+			dsi_color_from_mipi(format) << 1);
+
+	*lane_mbps = pll_out_khz / 1000;
+
+	DRM_DEBUG_DRIVER("pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n",
+			 pll_in_khz, pll_out_khz, *lane_mbps);
+
+	return 0;
+}
+
+static struct dw_mipi_dsi_phy_ops dw_mipi_dsi_stm_phy_ops = {
+	.init = dw_mipi_dsi_phy_init,
+	.get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
+};
+
+static struct dw_mipi_dsi_plat_data dw_mipi_dsi_stm_plat_data = {
+	.max_data_lanes = 2,
+	.phy_ops = &dw_mipi_dsi_stm_phy_ops,
+};
+
+static const struct of_device_id dw_mipi_dsi_stm_dt_ids[] = {
+	{ .compatible = "st,stm32-dsi", .data = &dw_mipi_dsi_stm_plat_data, },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, dw_mipi_dsi_stm_dt_ids);
+
+static int dw_mipi_dsi_stm_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct dw_mipi_dsi_stm *dsi;
+	struct resource *res;
+	int ret;
+
+	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
+	if (!dsi)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		DRM_ERROR("Unable to get resource\n");
+		return -ENODEV;
+	}
+
+	dsi->base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(dsi->base)) {
+		DRM_ERROR("Unable to get dsi registers\n");
+		return PTR_ERR(dsi->base);
+	}
+
+	dsi->pllref_clk = devm_clk_get(dev, "ref");
+	if (IS_ERR(dsi->pllref_clk)) {
+		ret = PTR_ERR(dsi->pllref_clk);
+		dev_err(dev, "Unable to get pll reference clock: %d\n", ret);
+		return ret;
+	}
+
+	ret = clk_prepare_enable(dsi->pllref_clk);
+	if (ret) {
+		dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
+		return ret;
+	}
+
+	dw_mipi_dsi_stm_plat_data.base = dsi->base;
+	dw_mipi_dsi_stm_plat_data.priv_data = dsi;
+
+	ret = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);
+	if (ret) {
+		DRM_ERROR("Failed to initialize mipi dsi host\n");
+		clk_disable_unprepare(dsi->pllref_clk);
+	}
+
+	return ret;
+}
+
+static int dw_mipi_dsi_stm_remove(struct platform_device *pdev)
+{
+	struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data;
+
+	clk_disable_unprepare(dsi->pllref_clk);
+	dw_mipi_dsi_remove(pdev);
+
+	return 0;
+}
+
+static struct platform_driver dw_mipi_dsi_stm_driver = {
+	.probe		= dw_mipi_dsi_stm_probe,
+	.remove		= dw_mipi_dsi_stm_remove,
+	.driver		= {
+		.of_match_table = dw_mipi_dsi_stm_dt_ids,
+		.name	= "dw_mipi_dsi-stm",
+	},
+};
+
+module_platform_driver(dw_mipi_dsi_stm_driver);
+
+MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
+MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
+MODULE_DESCRIPTION("STMicroelectronics DW MIPI DSI host controller driver");
+MODULE_LICENSE("GPL v2");
-- 
1.9.1

_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v5 7/7] drm/stm: Add STM32 DSI controller driver
@ 2017-07-03  8:41   ` Philippe CORNU
  0 siblings, 0 replies; 24+ messages in thread
From: Philippe CORNU @ 2017-07-03  8:41 UTC (permalink / raw)
  To: linux-arm-kernel

Add the STM32 DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.

Signed-off-by: Philippe CORNU <philippe.cornu@st.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Archit Taneja <architt@codeaurora.org>
---
 drivers/gpu/drm/stm/Kconfig           |   7 +
 drivers/gpu/drm/stm/Makefile          |   2 +
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 352 ++++++++++++++++++++++++++++++++++
 3 files changed, 361 insertions(+)
 create mode 100644 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c

diff --git a/drivers/gpu/drm/stm/Kconfig b/drivers/gpu/drm/stm/Kconfig
index 4b88223..f9462bc 100644
--- a/drivers/gpu/drm/stm/Kconfig
+++ b/drivers/gpu/drm/stm/Kconfig
@@ -14,3 +14,10 @@ config DRM_STM
 	  STMicroelectronics STM32 MCUs.
 	  To compile this driver as a module, choose M here: the module
 	  will be called stm-drm.
+
+config DRM_STM_DSI
+	tristate "STMicroelectronics specific extensions for Synopsys MIPI DSI"
+	depends on DRM_STM
+	select DRM_DW_MIPI_DSI
+	help
+	  Choose this option for MIPI DSI support on STMicroelectronics SoC.
diff --git a/drivers/gpu/drm/stm/Makefile b/drivers/gpu/drm/stm/Makefile
index a09ecf4..d883adc 100644
--- a/drivers/gpu/drm/stm/Makefile
+++ b/drivers/gpu/drm/stm/Makefile
@@ -2,4 +2,6 @@ stm-drm-y := \
 	drv.o \
 	ltdc.o
 
+obj-$(CONFIG_DRM_STM_DSI) += dw_mipi_dsi-stm.o
+
 obj-$(CONFIG_DRM_STM) += stm-drm.o
diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
new file mode 100644
index 0000000..16ae00e
--- /dev/null
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -0,0 +1,352 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ *
+ * Authors: Philippe Cornu <philippe.cornu@st.com>
+ *          Yannick Fertre <yannick.fertre@st.com>
+ *
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+#include <linux/clk.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <drm/drmP.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/bridge/dw_mipi_dsi.h>
+#include <video/mipi_display.h>
+
+/* DSI wrapper register & bit definitions */
+/* Note: registers are named as in the Reference Manual */
+#define DSI_WCFGR	0x0400		/* Wrapper ConFiGuration Reg */
+#define WCFGR_DSIM	BIT(0)		/* DSI Mode */
+#define WCFGR_COLMUX	GENMASK(3, 1)	/* COLor MUltipleXing */
+
+#define DSI_WCR		0x0404		/* Wrapper Control Reg */
+#define WCR_DSIEN	BIT(3)		/* DSI ENable */
+
+#define DSI_WISR	0x040C		/* Wrapper Interrupt and Status Reg */
+#define WISR_PLLLS	BIT(8)		/* PLL Lock Status */
+#define WISR_RRS	BIT(12)		/* Regulator Ready Status */
+
+#define DSI_WPCR0	0x0418		/* Wrapper Phy Conf Reg 0 */
+#define WPCR0_UIX4	GENMASK(5, 0)	/* Unit Interval X 4 */
+#define WPCR0_TDDL	BIT(16)		/* Turn Disable Data Lanes */
+
+#define DSI_WRPCR	0x0430		/* Wrapper Regulator & Pll Ctrl Reg */
+#define WRPCR_PLLEN	BIT(0)		/* PLL ENable */
+#define WRPCR_NDIV	GENMASK(8, 2)	/* pll loop DIVision Factor */
+#define WRPCR_IDF	GENMASK(14, 11)	/* pll Input Division Factor */
+#define WRPCR_ODF	GENMASK(17, 16)	/* pll Output Division Factor */
+#define WRPCR_REGEN	BIT(24)		/* REGulator ENable */
+#define WRPCR_BGREN	BIT(28)		/* BandGap Reference ENable */
+#define IDF_MIN		1
+#define IDF_MAX		7
+#define NDIV_MIN	10
+#define NDIV_MAX	125
+#define ODF_MIN		1
+#define ODF_MAX		8
+
+/* dsi color format coding according to the datasheet */
+enum dsi_color {
+	DSI_RGB565_CONF1,
+	DSI_RGB565_CONF2,
+	DSI_RGB565_CONF3,
+	DSI_RGB666_CONF1,
+	DSI_RGB666_CONF2,
+	DSI_RGB888,
+};
+
+#define LANE_MIN_KBPS	31250
+#define LANE_MAX_KBPS	500000
+
+/* Sleep & timeout for regulator on/off, pll lock/unlock & fifo empty */
+#define SLEEP_US	1000
+#define TIMEOUT_US	200000
+
+struct dw_mipi_dsi_stm {
+	void __iomem *base;
+	struct clk *pllref_clk;
+};
+
+static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val)
+{
+	writel(val, dsi->base + reg);
+}
+
+static inline u32 dsi_read(struct dw_mipi_dsi_stm *dsi, u32 reg)
+{
+	return readl(dsi->base + reg);
+}
+
+static inline void dsi_set(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask)
+{
+	dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
+}
+
+static inline void dsi_clear(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask)
+{
+	dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask);
+}
+
+static inline void dsi_update_bits(struct dw_mipi_dsi_stm *dsi, u32 reg,
+				   u32 mask, u32 val)
+{
+	dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
+}
+
+static enum dsi_color dsi_color_from_mipi(enum mipi_dsi_pixel_format fmt)
+{
+	switch (fmt) {
+	case MIPI_DSI_FMT_RGB888:
+		return DSI_RGB888;
+	case MIPI_DSI_FMT_RGB666:
+		return DSI_RGB666_CONF2;
+	case MIPI_DSI_FMT_RGB666_PACKED:
+		return DSI_RGB666_CONF1;
+	case MIPI_DSI_FMT_RGB565:
+		return DSI_RGB565_CONF1;
+	default:
+		DRM_DEBUG_DRIVER("MIPI color invalid, so we use rgb888\n");
+	}
+	return DSI_RGB888;
+}
+
+static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf)
+{
+	/* prevent from division by 0 */
+	if (idf * odf)
+		return DIV_ROUND_CLOSEST(clkin_khz * ndiv, idf * odf);
+
+	return 0;
+}
+
+static int dsi_pll_get_params(int clkin_khz, int clkout_khz,
+			      int *idf, int *ndiv, int *odf)
+{
+	int i, o, n, n_min, n_max;
+	int fvco_min, fvco_max, delta, best_delta; /* all in khz */
+
+	/* Early checks preventing division by 0 & odd results */
+	if ((clkin_khz <= 0) || (clkout_khz <= 0))
+		return -EINVAL;
+
+	fvco_min = LANE_MIN_KBPS * 2 * ODF_MAX;
+	fvco_max = LANE_MAX_KBPS * 2 * ODF_MIN;
+
+	best_delta = 1000000; /* big started value (1000000khz) */
+
+	for (i = IDF_MIN; i <= IDF_MAX; i++) {
+		/* Compute ndiv range according to Fvco */
+		n_min = ((fvco_min * i) / (2 * clkin_khz)) + 1;
+		n_max = (fvco_max * i) / (2 * clkin_khz);
+
+		/* No need to continue idf loop if we reach ndiv max */
+		if (n_min >= NDIV_MAX)
+			break;
+
+		/* Clamp ndiv to valid values */
+		if (n_min < NDIV_MIN)
+			n_min = NDIV_MIN;
+		if (n_max > NDIV_MAX)
+			n_max = NDIV_MAX;
+
+		for (o = ODF_MIN; o <= ODF_MAX; o *= 2) {
+			n = DIV_ROUND_CLOSEST(i * o * clkout_khz, clkin_khz);
+			/* Check ndiv according to vco range */
+			if ((n < n_min) || (n > n_max))
+				continue;
+			/* Check if new delta is better & saves parameters */
+			delta = dsi_pll_get_clkout_khz(clkin_khz, i, n, o) -
+				clkout_khz;
+			if (delta < 0)
+				delta = -delta;
+			if (delta < best_delta) {
+				*idf = i;
+				*ndiv = n;
+				*odf = o;
+				best_delta = delta;
+			}
+			/* fast return in case of "perfect result" */
+			if (!delta)
+				return 0;
+		}
+	}
+
+	return 0;
+}
+
+static int dw_mipi_dsi_phy_init(void *priv_data)
+{
+	struct dw_mipi_dsi_stm *dsi = priv_data;
+	u32 val;
+	int ret;
+
+	/* Enable the regulator */
+	dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
+	ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS,
+				 SLEEP_US, TIMEOUT_US);
+	if (ret)
+		DRM_DEBUG_DRIVER("!TIMEOUT! waiting REGU, let's continue\n");
+
+	/* Enable the DSI PLL & wait for its lock */
+	dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN);
+	ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
+				 SLEEP_US, TIMEOUT_US);
+	if (ret)
+		DRM_DEBUG_DRIVER("!TIMEOUT! waiting PLL, let's continue\n");
+
+	/* Enable the DSI wrapper */
+	dsi_set(dsi, DSI_WCR, WCR_DSIEN);
+
+	return 0;
+}
+
+static int
+dw_mipi_dsi_get_lane_mbps(void *priv_data, struct drm_display_mode *mode,
+			  unsigned long mode_flags, u32 lanes, u32 format,
+			  unsigned int *lane_mbps)
+{
+	struct dw_mipi_dsi_stm *dsi = priv_data;
+	unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
+	int ret, bpp;
+	u32 val;
+
+	pll_in_khz = (unsigned int)(clk_get_rate(dsi->pllref_clk) / 1000);
+
+	/* Compute requested pll out */
+	bpp = mipi_dsi_pixel_format_to_bpp(format);
+	pll_out_khz = mode->clock * bpp / lanes;
+	/* Add 20% to pll out to be higher than pixel bw (burst mode only) */
+	pll_out_khz = (pll_out_khz * 12) / 10;
+	if (pll_out_khz > LANE_MAX_KBPS) {
+		pll_out_khz = LANE_MAX_KBPS;
+		DRM_WARN("Warning max phy mbps is used\n");
+	}
+	if (pll_out_khz < LANE_MIN_KBPS) {
+		pll_out_khz = LANE_MIN_KBPS;
+		DRM_WARN("Warning min phy mbps is used\n");
+	}
+
+	/* Compute best pll parameters */
+	idf = 0;
+	ndiv = 0;
+	odf = 0;
+	ret = dsi_pll_get_params(pll_in_khz, pll_out_khz, &idf, &ndiv, &odf);
+	if (ret)
+		DRM_WARN("Warning dsi_pll_get_params(): bad params\n");
+
+	/* Get the adjusted pll out value */
+	pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
+
+	/* Set the PLL division factors */
+	dsi_update_bits(dsi, DSI_WRPCR,	WRPCR_NDIV | WRPCR_IDF | WRPCR_ODF,
+			(ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16));
+
+	/* Compute uix4 & set the bit period in high-speed mode */
+	val = 4000000 / pll_out_khz;
+	dsi_update_bits(dsi, DSI_WPCR0, WPCR0_UIX4, val);
+
+	/* Select video mode by resetting DSIM bit */
+	dsi_clear(dsi, DSI_WCFGR, WCFGR_DSIM);
+
+	/* Select the color coding */
+	dsi_update_bits(dsi, DSI_WCFGR, WCFGR_COLMUX,
+			dsi_color_from_mipi(format) << 1);
+
+	*lane_mbps = pll_out_khz / 1000;
+
+	DRM_DEBUG_DRIVER("pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n",
+			 pll_in_khz, pll_out_khz, *lane_mbps);
+
+	return 0;
+}
+
+static struct dw_mipi_dsi_phy_ops dw_mipi_dsi_stm_phy_ops = {
+	.init = dw_mipi_dsi_phy_init,
+	.get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
+};
+
+static struct dw_mipi_dsi_plat_data dw_mipi_dsi_stm_plat_data = {
+	.max_data_lanes = 2,
+	.phy_ops = &dw_mipi_dsi_stm_phy_ops,
+};
+
+static const struct of_device_id dw_mipi_dsi_stm_dt_ids[] = {
+	{ .compatible = "st,stm32-dsi", .data = &dw_mipi_dsi_stm_plat_data, },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, dw_mipi_dsi_stm_dt_ids);
+
+static int dw_mipi_dsi_stm_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct dw_mipi_dsi_stm *dsi;
+	struct resource *res;
+	int ret;
+
+	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
+	if (!dsi)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		DRM_ERROR("Unable to get resource\n");
+		return -ENODEV;
+	}
+
+	dsi->base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(dsi->base)) {
+		DRM_ERROR("Unable to get dsi registers\n");
+		return PTR_ERR(dsi->base);
+	}
+
+	dsi->pllref_clk = devm_clk_get(dev, "ref");
+	if (IS_ERR(dsi->pllref_clk)) {
+		ret = PTR_ERR(dsi->pllref_clk);
+		dev_err(dev, "Unable to get pll reference clock: %d\n", ret);
+		return ret;
+	}
+
+	ret = clk_prepare_enable(dsi->pllref_clk);
+	if (ret) {
+		dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
+		return ret;
+	}
+
+	dw_mipi_dsi_stm_plat_data.base = dsi->base;
+	dw_mipi_dsi_stm_plat_data.priv_data = dsi;
+
+	ret = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);
+	if (ret) {
+		DRM_ERROR("Failed to initialize mipi dsi host\n");
+		clk_disable_unprepare(dsi->pllref_clk);
+	}
+
+	return ret;
+}
+
+static int dw_mipi_dsi_stm_remove(struct platform_device *pdev)
+{
+	struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data;
+
+	clk_disable_unprepare(dsi->pllref_clk);
+	dw_mipi_dsi_remove(pdev);
+
+	return 0;
+}
+
+static struct platform_driver dw_mipi_dsi_stm_driver = {
+	.probe		= dw_mipi_dsi_stm_probe,
+	.remove		= dw_mipi_dsi_stm_remove,
+	.driver		= {
+		.of_match_table = dw_mipi_dsi_stm_dt_ids,
+		.name	= "dw_mipi_dsi-stm",
+	},
+};
+
+module_platform_driver(dw_mipi_dsi_stm_driver);
+
+MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
+MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
+MODULE_DESCRIPTION("STMicroelectronics DW MIPI DSI host controller driver");
+MODULE_LICENSE("GPL v2");
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* Re: [PATCH v5 3/7] dt-bindings: display: Add Synopsys DW MIPI DSI host controller
  2017-07-03  8:41   ` Philippe CORNU
@ 2017-07-07 15:53       ` Rob Herring
  -1 siblings, 0 replies; 24+ messages in thread
From: Rob Herring @ 2017-07-07 15:53 UTC (permalink / raw)
  To: Philippe CORNU
  Cc: Alexandre Torgue, Thierry Reding, David Airlie, Maxime Coquelin,
	Russell King, Mark Rutland, Arnd Bergmann, Benjamin Gaignard,
	Yannick Fertre, Neil Armstrong, Archit Taneja, Eric Anholt,
	Chris Zhong, Andrzej Hajda, Xinliang Liu,
	zourongrong-Re5JQEeQqe8AvxtiuMwx3w, Xinwei Kong, Chen Feng,
	Mark Yao, Mickael Reulier

On Mon, Jul 03, 2017 at 10:41:23AM +0200, Philippe CORNU wrote:
> This patch adds documentation of device tree bindings for the
> Synopsys DesignWare MIPI DSI host controller.
> 
> Signed-off-by: Philippe CORNU <philippe.cornu-qxv4g6HH51o@public.gmane.org>
> ---
>  .../bindings/display/bridge/dw_mipi_dsi.txt        | 32 ++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply	[flat|nested] 24+ messages in thread
* [PATCH v5 3/7] dt-bindings: display: Add Synopsys DW MIPI DSI host controller
@ 2017-07-07 15:53       ` Rob Herring
  0 siblings, 0 replies; 24+ messages in thread
From: Rob Herring @ 2017-07-07 15:53 UTC (permalink / raw)
  To: linux-arm-kernel

On Mon, Jul 03, 2017 at 10:41:23AM +0200, Philippe CORNU wrote:
> This patch adds documentation of device tree bindings for the
> Synopsys DesignWare MIPI DSI host controller.
> 
> Signed-off-by: Philippe CORNU <philippe.cornu@st.com>
> ---
>  .../bindings/display/bridge/dw_mipi_dsi.txt        | 32 ++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v5 4/7] drm/bridge/synopsys: Add MIPI DSI host controller bridge
  2017-07-03  8:41   ` Philippe CORNU
@ 2017-07-12  6:05     ` Archit Taneja
  -1 siblings, 0 replies; 24+ messages in thread
From: Archit Taneja @ 2017-07-12  6:05 UTC (permalink / raw)
  To: Philippe CORNU, Alexandre Torgue, Thierry Reding, David Airlie,
	Maxime Coquelin, Russell King, Mark Rutland, Rob Herring,
	Arnd Bergmann, Benjamin Gaignard, Yannick Fertre, Neil Armstrong,
	Eric Anholt, Chris Zhong, Andrzej Hajda, Xinliang Liu,
	zourongrong, Xinwei Kong, Chen Feng, Mark Yao
  Cc: devicetree, dri-devel, Fabien Dessenne, Ludovic Barre,
	Mickael Reulier, Vincent Abriou, Gabriel Fernandez,
	linux-arm-kernel



On 07/03/2017 02:11 PM, Philippe CORNU wrote:
> Add a Synopsys Designware MIPI DSI host DRM bridge driver, based on the
> Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
> 

The patch looks good now. One thing that needs to be updated is to make
drm_bridge_add() not return anything.

The later patches in the series would be dependent on this patch, right?
Since the ST patches go via drm-misc too, we could either push all these
together, or I could push the bridge driver to drm-misc-next, and the ST
patches can be pushed after. Any preference? If not, I'll do the latter.

Archit


> Signed-off-by: Philippe CORNU <philippe.cornu@st.com>
> ---
>   drivers/gpu/drm/bridge/synopsys/Kconfig       |   6 +
>   drivers/gpu/drm/bridge/synopsys/Makefile      |   2 +
>   drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 979 ++++++++++++++++++++++++++
>   include/drm/bridge/dw_mipi_dsi.h              |  39 +
>   4 files changed, 1026 insertions(+)
>   create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>   create mode 100644 include/drm/bridge/dw_mipi_dsi.h
> 
> diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig b/drivers/gpu/drm/bridge/synopsys/Kconfig
> index 40d2827..f00ee26 100644
> --- a/drivers/gpu/drm/bridge/synopsys/Kconfig
> +++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
> @@ -21,3 +21,9 @@ config DRM_DW_HDMI_I2S_AUDIO
>   	help
>   	  Support the I2S Audio interface which is part of the Synopsys
>   	  Designware HDMI block.
> +
> +config DRM_DW_MIPI_DSI
> +	tristate
> +	select DRM_KMS_HELPER
> +	select DRM_MIPI_DSI
> +	select DRM_PANEL_BRIDGE
> diff --git a/drivers/gpu/drm/bridge/synopsys/Makefile b/drivers/gpu/drm/bridge/synopsys/Makefile
> index 17aa7a6..5f57d36 100644
> --- a/drivers/gpu/drm/bridge/synopsys/Makefile
> +++ b/drivers/gpu/drm/bridge/synopsys/Makefile
> @@ -3,3 +3,5 @@
>   obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
>   obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
>   obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
> +
> +obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw-mipi-dsi.o
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> new file mode 100644
> index 0000000..406000e
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> @@ -0,0 +1,979 @@
> +/*
> + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
> + * Copyright (C) STMicroelectronics SA 2017
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * Modified by Philippe Cornu <philippe.cornu@st.com>
> + * This generic Synopsys DesignWare MIPI DSI host driver is based on the
> + * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/iopoll.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/reset.h>
> +#include <drm/drmP.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_bridge.h>
> +#include <drm/drm_crtc.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_mipi_dsi.h>
> +#include <drm/drm_of.h>
> +#include <drm/bridge/dw_mipi_dsi.h>
> +#include <video/mipi_display.h>
> +
> +#define DSI_VERSION			0x00
> +#define DSI_PWR_UP			0x04
> +#define RESET				0
> +#define POWERUP				BIT(0)
> +
> +#define DSI_CLKMGR_CFG			0x08
> +#define TO_CLK_DIVIDSION(div)		(((div) & 0xff) << 8)
> +#define TX_ESC_CLK_DIVIDSION(div)	(((div) & 0xff) << 0)
> +
> +#define DSI_DPI_VCID			0x0c
> +#define DPI_VID(vid)			(((vid) & 0x3) << 0)
> +
> +#define DSI_DPI_COLOR_CODING		0x10
> +#define EN18_LOOSELY			BIT(8)
> +#define DPI_COLOR_CODING_16BIT_1	0x0
> +#define DPI_COLOR_CODING_16BIT_2	0x1
> +#define DPI_COLOR_CODING_16BIT_3	0x2
> +#define DPI_COLOR_CODING_18BIT_1	0x3
> +#define DPI_COLOR_CODING_18BIT_2	0x4
> +#define DPI_COLOR_CODING_24BIT		0x5
> +
> +#define DSI_DPI_CFG_POL			0x14
> +#define COLORM_ACTIVE_LOW		BIT(4)
> +#define SHUTD_ACTIVE_LOW		BIT(3)
> +#define HSYNC_ACTIVE_LOW		BIT(2)
> +#define VSYNC_ACTIVE_LOW		BIT(1)
> +#define DATAEN_ACTIVE_LOW		BIT(0)
> +
> +#define DSI_DPI_LP_CMD_TIM		0x18
> +#define OUTVACT_LPCMD_TIME(p)		(((p) & 0xff) << 16)
> +#define INVACT_LPCMD_TIME(p)		((p) & 0xff)
> +
> +#define DSI_DBI_CFG			0x20
> +#define DSI_DBI_CMDSIZE			0x28
> +
> +#define DSI_PCKHDL_CFG			0x2c
> +#define EN_CRC_RX			BIT(4)
> +#define EN_ECC_RX			BIT(3)
> +#define EN_BTA				BIT(2)
> +#define EN_EOTP_RX			BIT(1)
> +#define EN_EOTP_TX			BIT(0)
> +
> +#define DSI_MODE_CFG			0x34
> +#define ENABLE_VIDEO_MODE		0
> +#define ENABLE_CMD_MODE			BIT(0)
> +
> +#define DSI_VID_MODE_CFG		0x38
> +#define FRAME_BTA_ACK			BIT(14)
> +#define ENABLE_LOW_POWER		(0x3f << 8)
> +#define ENABLE_LOW_POWER_MASK		(0x3f << 8)
> +#define VID_MODE_TYPE_NON_BURST_SYNC_PULSES	0x0
> +#define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS	0x1
> +#define VID_MODE_TYPE_BURST			0x2
> +#define VID_MODE_TYPE_MASK			0x3
> +
> +#define DSI_VID_PKT_SIZE		0x3c
> +#define VID_PKT_SIZE(p)			(((p) & 0x3fff) << 0)
> +#define VID_PKT_MAX_SIZE		0x3fff
> +
> +#define DSI_VID_HSA_TIME		0x48
> +#define DSI_VID_HBP_TIME		0x4c
> +#define DSI_VID_HLINE_TIME		0x50
> +#define DSI_VID_VSA_LINES		0x54
> +#define DSI_VID_VBP_LINES		0x58
> +#define DSI_VID_VFP_LINES		0x5c
> +#define DSI_VID_VACTIVE_LINES		0x60
> +#define DSI_CMD_MODE_CFG		0x68
> +#define MAX_RD_PKT_SIZE_LP		BIT(24)
> +#define DCS_LW_TX_LP			BIT(19)
> +#define DCS_SR_0P_TX_LP			BIT(18)
> +#define DCS_SW_1P_TX_LP			BIT(17)
> +#define DCS_SW_0P_TX_LP			BIT(16)
> +#define GEN_LW_TX_LP			BIT(14)
> +#define GEN_SR_2P_TX_LP			BIT(13)
> +#define GEN_SR_1P_TX_LP			BIT(12)
> +#define GEN_SR_0P_TX_LP			BIT(11)
> +#define GEN_SW_2P_TX_LP			BIT(10)
> +#define GEN_SW_1P_TX_LP			BIT(9)
> +#define GEN_SW_0P_TX_LP			BIT(8)
> +#define EN_ACK_RQST			BIT(1)
> +#define EN_TEAR_FX			BIT(0)
> +
> +#define CMD_MODE_ALL_LP			(MAX_RD_PKT_SIZE_LP | \
> +					 DCS_LW_TX_LP | \
> +					 DCS_SR_0P_TX_LP | \
> +					 DCS_SW_1P_TX_LP | \
> +					 DCS_SW_0P_TX_LP | \
> +					 GEN_LW_TX_LP | \
> +					 GEN_SR_2P_TX_LP | \
> +					 GEN_SR_1P_TX_LP | \
> +					 GEN_SR_0P_TX_LP | \
> +					 GEN_SW_2P_TX_LP | \
> +					 GEN_SW_1P_TX_LP | \
> +					 GEN_SW_0P_TX_LP)
> +
> +#define DSI_GEN_HDR			0x6c
> +#define GEN_HDATA(data)			(((data) & 0xffff) << 8)
> +#define GEN_HDATA_MASK			(0xffff << 8)
> +#define GEN_HTYPE(type)			(((type) & 0xff) << 0)
> +#define GEN_HTYPE_MASK			0xff
> +
> +#define DSI_GEN_PLD_DATA		0x70
> +
> +#define DSI_CMD_PKT_STATUS		0x74
> +#define GEN_CMD_EMPTY			BIT(0)
> +#define GEN_CMD_FULL			BIT(1)
> +#define GEN_PLD_W_EMPTY			BIT(2)
> +#define GEN_PLD_W_FULL			BIT(3)
> +#define GEN_PLD_R_EMPTY			BIT(4)
> +#define GEN_PLD_R_FULL			BIT(5)
> +#define GEN_RD_CMD_BUSY			BIT(6)
> +
> +#define DSI_TO_CNT_CFG			0x78
> +#define HSTX_TO_CNT(p)			(((p) & 0xffff) << 16)
> +#define LPRX_TO_CNT(p)			((p) & 0xffff)
> +
> +#define DSI_BTA_TO_CNT			0x8c
> +#define DSI_LPCLK_CTRL			0x94
> +#define AUTO_CLKLANE_CTRL		BIT(1)
> +#define PHY_TXREQUESTCLKHS		BIT(0)
> +
> +#define DSI_PHY_TMR_LPCLK_CFG		0x98
> +#define PHY_CLKHS2LP_TIME(lbcc)		(((lbcc) & 0x3ff) << 16)
> +#define PHY_CLKLP2HS_TIME(lbcc)		((lbcc) & 0x3ff)
> +
> +#define DSI_PHY_TMR_CFG			0x9c
> +#define PHY_HS2LP_TIME(lbcc)		(((lbcc) & 0xff) << 24)
> +#define PHY_LP2HS_TIME(lbcc)		(((lbcc) & 0xff) << 16)
> +#define MAX_RD_TIME(lbcc)		((lbcc) & 0x7fff)
> +
> +#define DSI_PHY_RSTZ			0xa0
> +#define PHY_DISFORCEPLL			0
> +#define PHY_ENFORCEPLL			BIT(3)
> +#define PHY_DISABLECLK			0
> +#define PHY_ENABLECLK			BIT(2)
> +#define PHY_RSTZ			0
> +#define PHY_UNRSTZ			BIT(1)
> +#define PHY_SHUTDOWNZ			0
> +#define PHY_UNSHUTDOWNZ			BIT(0)
> +
> +#define DSI_PHY_IF_CFG			0xa4
> +#define N_LANES(n)			((((n) - 1) & 0x3) << 0)
> +#define PHY_STOP_WAIT_TIME(cycle)	(((cycle) & 0xff) << 8)
> +
> +#define DSI_PHY_STATUS			0xb0
> +#define LOCK				BIT(0)
> +#define STOP_STATE_CLK_LANE		BIT(2)
> +
> +#define DSI_PHY_TST_CTRL0		0xb4
> +#define PHY_TESTCLK			BIT(1)
> +#define PHY_UNTESTCLK			0
> +#define PHY_TESTCLR			BIT(0)
> +#define PHY_UNTESTCLR			0
> +
> +#define DSI_PHY_TST_CTRL1		0xb8
> +#define PHY_TESTEN			BIT(16)
> +#define PHY_UNTESTEN			0
> +#define PHY_TESTDOUT(n)			(((n) & 0xff) << 8)
> +#define PHY_TESTDIN(n)			(((n) & 0xff) << 0)
> +
> +#define DSI_INT_ST0			0xbc
> +#define DSI_INT_ST1			0xc0
> +#define DSI_INT_MSK0			0xc4
> +#define DSI_INT_MSK1			0xc8
> +
> +#define PHY_STATUS_TIMEOUT_US		10000
> +#define CMD_PKT_STATUS_TIMEOUT_US	20000
> +
> +struct dw_mipi_dsi {
> +	struct drm_bridge bridge;
> +	struct mipi_dsi_host dsi_host;
> +	struct drm_bridge *panel_bridge;
> +	bool is_panel_bridge;
> +	struct device *dev;
> +	void __iomem *base;
> +
> +	struct clk *pclk;
> +
> +	unsigned int lane_mbps; /* per lane */
> +	u32 channel;
> +	u32 lanes;
> +	u32 format;
> +	unsigned long mode_flags;
> +
> +	const struct dw_mipi_dsi_plat_data *plat_data;
> +};
> +
> +/*
> + * The controller should generate 2 frames before
> + * preparing the peripheral.
> + */
> +static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode *mode)
> +{
> +	int refresh, two_frames;
> +
> +	refresh = drm_mode_vrefresh(mode);
> +	two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
> +	msleep(two_frames);
> +}
> +
> +static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
> +{
> +	return container_of(host, struct dw_mipi_dsi, dsi_host);
> +}
> +
> +static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge)
> +{
> +	return container_of(bridge, struct dw_mipi_dsi, bridge);
> +}
> +
> +static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
> +{
> +	writel(val, dsi->base + reg);
> +}
> +
> +static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
> +{
> +	return readl(dsi->base + reg);
> +}
> +
> +static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
> +				   struct mipi_dsi_device *device)
> +{
> +	struct dw_mipi_dsi *dsi = host_to_dsi(host);
> +	struct drm_bridge *bridge;
> +	struct drm_panel *panel;
> +	int ret;
> +
> +	if (device->lanes > dsi->plat_data->max_data_lanes) {
> +		dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
> +			device->lanes);
> +		return -EINVAL;
> +	}
> +
> +	dsi->lanes = device->lanes;
> +	dsi->channel = device->channel;
> +	dsi->format = device->format;
> +	dsi->mode_flags = device->mode_flags;
> +
> +	ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0,
> +					  &panel, &bridge);
> +	if (ret)
> +		return ret;
> +
> +	if (panel) {
> +		bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DSI);
> +		if (IS_ERR(bridge))
> +			return PTR_ERR(bridge);
> +		dsi->is_panel_bridge = true;
> +	}
> +
> +	dsi->panel_bridge = bridge;
> +
> +	return drm_bridge_add(&dsi->bridge);
> +}
> +
> +static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
> +				   struct mipi_dsi_device *device)
> +{
> +	struct dw_mipi_dsi *dsi = host_to_dsi(host);
> +
> +	if (dsi->is_panel_bridge)
> +		drm_panel_bridge_remove(dsi->panel_bridge);
> +
> +	drm_bridge_remove(&dsi->bridge);
> +
> +	return 0;
> +}
> +
> +static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
> +				   const struct mipi_dsi_msg *msg)
> +{
> +	bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
> +	u32 val = 0;
> +
> +	if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
> +		val |= EN_ACK_RQST;
> +	if (lpm)
> +		val |= CMD_MODE_ALL_LP;
> +
> +	dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
> +	dsi_write(dsi, DSI_CMD_MODE_CFG, val);
> +}
> +
> +static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
> +{
> +	int ret;
> +	u32 val, mask;
> +
> +	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> +				 val, !(val & GEN_CMD_FULL), 1000,
> +				 CMD_PKT_STATUS_TIMEOUT_US);
> +	if (ret < 0) {
> +		dev_err(dsi->dev, "failed to get available command FIFO\n");
> +		return ret;
> +	}
> +
> +	dsi_write(dsi, DSI_GEN_HDR, hdr_val);
> +
> +	mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
> +	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> +				 val, (val & mask) == mask,
> +				 1000, CMD_PKT_STATUS_TIMEOUT_US);
> +	if (ret < 0) {
> +		dev_err(dsi->dev, "failed to write command FIFO\n");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi *dsi,
> +				       const struct mipi_dsi_msg *msg)
> +{
> +	const u8 *tx_buf = msg->tx_buf;
> +	u16 data = 0;
> +	u32 val;
> +
> +	if (msg->tx_len > 0)
> +		data |= tx_buf[0];
> +	if (msg->tx_len > 1)
> +		data |= tx_buf[1] << 8;
> +
> +	if (msg->tx_len > 2) {
> +		dev_err(dsi->dev, "too long tx buf length %zu for short write\n",
> +			msg->tx_len);
> +		return -EINVAL;
> +	}
> +
> +	val = GEN_HDATA(data) | GEN_HTYPE(msg->type);
> +	return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
> +}
> +
> +static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
> +				      const struct mipi_dsi_msg *msg)
> +{
> +	const u8 *tx_buf = msg->tx_buf;
> +	int len = msg->tx_len, pld_data_bytes = sizeof(u32), ret;
> +	u32 hdr_val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
> +	u32 remainder;
> +	u32 val;
> +
> +	if (msg->tx_len < 3) {
> +		dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
> +			msg->tx_len);
> +		return -EINVAL;
> +	}
> +
> +	while (DIV_ROUND_UP(len, pld_data_bytes)) {
> +		if (len < pld_data_bytes) {
> +			remainder = 0;
> +			memcpy(&remainder, tx_buf, len);
> +			dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
> +			len = 0;
> +		} else {
> +			memcpy(&remainder, tx_buf, pld_data_bytes);
> +			dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
> +			tx_buf += pld_data_bytes;
> +			len -= pld_data_bytes;
> +		}
> +
> +		ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> +					 val, !(val & GEN_PLD_W_FULL), 1000,
> +					 CMD_PKT_STATUS_TIMEOUT_US);
> +		if (ret < 0) {
> +			dev_err(dsi->dev,
> +				"failed to get available write payload FIFO\n");
> +			return ret;
> +		}
> +	}
> +
> +	return dw_mipi_dsi_gen_pkt_hdr_write(dsi, hdr_val);
> +}
> +
> +static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
> +					 const struct mipi_dsi_msg *msg)
> +{
> +	struct dw_mipi_dsi *dsi = host_to_dsi(host);
> +	int ret;
> +
> +	/*
> +	 * TODO dw drv improvements
> +	 * use mipi_dsi_create_packet() instead of all following
> +	 * functions and code (no switch cases, no
> +	 * dw_mipi_dsi_dcs_short_write(), only the loop in long_write...)
> +	 * and use packet.header...
> +	 */
> +	dw_mipi_message_config(dsi, msg);
> +
> +	switch (msg->type) {
> +	case MIPI_DSI_DCS_SHORT_WRITE:
> +	case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
> +	case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
> +		ret = dw_mipi_dsi_dcs_short_write(dsi, msg);
> +		break;
> +	case MIPI_DSI_DCS_LONG_WRITE:
> +		ret = dw_mipi_dsi_dcs_long_write(dsi, msg);
> +		break;
> +	default:
> +		dev_err(dsi->dev, "unsupported message type 0x%02x\n",
> +			msg->type);
> +		ret = -EINVAL;
> +	}
> +
> +	return ret;
> +}
> +
> +static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
> +	.attach = dw_mipi_dsi_host_attach,
> +	.detach = dw_mipi_dsi_host_detach,
> +	.transfer = dw_mipi_dsi_host_transfer,
> +};
> +
> +static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
> +{
> +	u32 val;
> +
> +	/*
> +	 * TODO dw drv improvements
> +	 * enabling low power is panel-dependent, we should use the
> +	 * panel configuration here...
> +	 */
> +	val = ENABLE_LOW_POWER;
> +
> +	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
> +		val |= VID_MODE_TYPE_BURST;
> +	else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
> +		val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
> +	else
> +		val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
> +
> +	dsi_write(dsi, DSI_VID_MODE_CFG, val);
> +}
> +
> +static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
> +				 unsigned long mode_flags)
> +{
> +	dsi_write(dsi, DSI_PWR_UP, RESET);
> +
> +	if (mode_flags & MIPI_DSI_MODE_VIDEO) {
> +		dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
> +		dw_mipi_dsi_video_mode_config(dsi);
> +		dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
> +	} else {
> +		dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
> +	}
> +
> +	dsi_write(dsi, DSI_PWR_UP, POWERUP);
> +}
> +
> +static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
> +{
> +	dsi_write(dsi, DSI_PWR_UP, RESET);
> +	dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
> +}
> +
> +static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
> +{
> +	/*
> +	 * The maximum permitted escape clock is 20MHz and it is derived from
> +	 * lanebyteclk, which is running at "lane_mbps / 8".  Thus we want:
> +	 *
> +	 *     (lane_mbps >> 3) / esc_clk_division < 20
> +	 * which is:
> +	 *     (lane_mbps >> 3) / 20 > esc_clk_division
> +	 */
> +	u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
> +
> +	dsi_write(dsi, DSI_PWR_UP, RESET);
> +
> +	/*
> +	 * TODO dw drv improvements
> +	 * timeout clock division should be computed with the
> +	 * high speed transmission counter timeout and byte lane...
> +	 */
> +	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
> +		  TX_ESC_CLK_DIVIDSION(esc_clk_division));
> +}
> +
> +static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
> +				   struct drm_display_mode *mode)
> +{
> +	u32 val = 0, color = 0;
> +
> +	switch (dsi->format) {
> +	case MIPI_DSI_FMT_RGB888:
> +		color = DPI_COLOR_CODING_24BIT;
> +		break;
> +	case MIPI_DSI_FMT_RGB666:
> +		color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
> +		break;
> +	case MIPI_DSI_FMT_RGB666_PACKED:
> +		color = DPI_COLOR_CODING_18BIT_1;
> +		break;
> +	case MIPI_DSI_FMT_RGB565:
> +		color = DPI_COLOR_CODING_16BIT_1;
> +		break;
> +	}
> +
> +	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
> +		val |= VSYNC_ACTIVE_LOW;
> +	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
> +		val |= HSYNC_ACTIVE_LOW;
> +
> +	dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
> +	dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
> +	dsi_write(dsi, DSI_DPI_CFG_POL, val);
> +	/*
> +	 * TODO dw drv improvements
> +	 * largest packet sizes during hfp or during vsa/vpb/vfp
> +	 * should be computed according to byte lane, lane number and only
> +	 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
> +	 */
> +	dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
> +		  | INVACT_LPCMD_TIME(4));
> +}
> +
> +static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
> +{
> +	dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
> +}
> +
> +static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
> +					    struct drm_display_mode *mode)
> +{
> +	/*
> +	 * TODO dw drv improvements
> +	 * only burst mode is supported here. For non-burst video modes,
> +	 * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
> +	 * DSI_VNPCR.NPSIZE... especially because this driver supports
> +	 * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
> +	 */
> +	dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
> +}
> +
> +static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
> +{
> +	/*
> +	 * TODO dw drv improvements
> +	 * compute high speed transmission counter timeout according
> +	 * to the timeout clock division (TO_CLK_DIVIDSION) and byte lane...
> +	 */
> +	dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
> +	/*
> +	 * TODO dw drv improvements
> +	 * the Bus-Turn-Around Timeout Counter should be computed
> +	 * according to byte lane...
> +	 */
> +	dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
> +	dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
> +}
> +
> +/* Get lane byte clock cycles. */
> +static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
> +					   struct drm_display_mode *mode,
> +					   u32 hcomponent)
> +{
> +	u32 frac, lbcc;
> +
> +	lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
> +
> +	frac = lbcc % mode->clock;
> +	lbcc = lbcc / mode->clock;
> +	if (frac)
> +		lbcc++;
> +
> +	return lbcc;
> +}
> +
> +static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
> +					  struct drm_display_mode *mode)
> +{
> +	u32 htotal, hsa, hbp, lbcc;
> +
> +	htotal = mode->htotal;
> +	hsa = mode->hsync_end - mode->hsync_start;
> +	hbp = mode->htotal - mode->hsync_end;
> +
> +	/*
> +	 * TODO dw drv improvements
> +	 * computations below may be improved...
> +	 */
> +	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
> +	dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
> +
> +	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
> +	dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
> +
> +	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
> +	dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
> +}
> +
> +static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
> +					       struct drm_display_mode *mode)
> +{
> +	u32 vactive, vsa, vfp, vbp;
> +
> +	vactive = mode->vdisplay;
> +	vsa = mode->vsync_end - mode->vsync_start;
> +	vfp = mode->vsync_start - mode->vdisplay;
> +	vbp = mode->vtotal - mode->vsync_end;
> +
> +	dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
> +	dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
> +	dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
> +	dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
> +}
> +
> +static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
> +{
> +	/*
> +	 * TODO dw drv improvements
> +	 * data & clock lane timers should be computed according to panel
> +	 * blankings and to the automatic clock lane control mode...
> +	 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
> +	 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
> +	 */
> +	dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40)
> +		  | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
> +
> +	dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
> +		  | PHY_CLKLP2HS_TIME(0x40));
> +}
> +
> +static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
> +{
> +	/*
> +	 * TODO dw drv improvements
> +	 * stop wait time should be the maximum between host dsi
> +	 * and panel stop wait times
> +	 */
> +	dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
> +		  N_LANES(dsi->lanes));
> +}
> +
> +static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
> +{
> +	/* Clear PHY state */
> +	dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
> +		  | PHY_RSTZ | PHY_SHUTDOWNZ);
> +	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
> +	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
> +	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
> +}
> +
> +static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
> +{
> +	u32 val;
> +	int ret;
> +
> +	dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
> +		  PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
> +
> +	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
> +				 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
> +	if (ret < 0)
> +		DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
> +
> +	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
> +				 val, val & STOP_STATE_CLK_LANE, 1000,
> +				 PHY_STATUS_TIMEOUT_US);
> +	if (ret < 0)
> +		DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
> +}
> +
> +static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
> +{
> +	dsi_read(dsi, DSI_INT_ST0);
> +	dsi_read(dsi, DSI_INT_ST1);
> +	dsi_write(dsi, DSI_INT_MSK0, 0);
> +	dsi_write(dsi, DSI_INT_MSK1, 0);
> +}
> +
> +static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
> +{
> +	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
> +
> +	/*
> +	 * Switch to command mode before panel-bridge post_disable &
> +	 * panel unprepare.
> +	 * Note: panel-bridge disable & panel disable has been called
> +	 * before by the drm framework.
> +	 */
> +	dw_mipi_dsi_set_mode(dsi, 0);
> +
> +	/*
> +	 * TODO Only way found to call panel-bridge post_disable &
> +	 * panel unprepare before the dsi "final" disable...
> +	 * This needs to be fixed in the drm_bridge framework and the API
> +	 * needs to be updated to manage our own call chains...
> +	 */
> +	dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge);
> +
> +	dw_mipi_dsi_disable(dsi);
> +	clk_disable_unprepare(dsi->pclk);
> +	pm_runtime_put(dsi->dev);
> +}
> +
> +void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
> +				 struct drm_display_mode *mode,
> +				 struct drm_display_mode *adjusted_mode)
> +{
> +	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
> +	const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
> +	void *priv_data = dsi->plat_data->priv_data;
> +	int ret;
> +
> +	clk_prepare_enable(dsi->pclk);
> +
> +	ret = phy_ops->get_lane_mbps(priv_data, mode, dsi->mode_flags,
> +				     dsi->lanes, dsi->format, &dsi->lane_mbps);
> +	if (ret)
> +		DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n");
> +
> +	pm_runtime_get_sync(dsi->dev);
> +	dw_mipi_dsi_init(dsi);
> +	dw_mipi_dsi_dpi_config(dsi, mode);
> +	dw_mipi_dsi_packet_handler_config(dsi);
> +	dw_mipi_dsi_video_mode_config(dsi);
> +	dw_mipi_dsi_video_packet_config(dsi, mode);
> +	dw_mipi_dsi_command_mode_config(dsi);
> +	dw_mipi_dsi_line_timer_config(dsi, mode);
> +	dw_mipi_dsi_vertical_timing_config(dsi, mode);
> +
> +	dw_mipi_dsi_dphy_init(dsi);
> +	dw_mipi_dsi_dphy_timing_config(dsi);
> +	dw_mipi_dsi_dphy_interface_config(dsi);
> +
> +	dw_mipi_dsi_clear_err(dsi);
> +
> +	ret = phy_ops->init(priv_data);
> +	if (ret)
> +		DRM_DEBUG_DRIVER("Phy init() failed\n");
> +
> +	dw_mipi_dsi_dphy_enable(dsi);
> +
> +	dw_mipi_dsi_wait_for_two_frames(mode);
> +
> +	/* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
> +	dw_mipi_dsi_set_mode(dsi, 0);
> +}
> +
> +static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge)
> +{
> +	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
> +
> +	/* Switch to video mode for panel-bridge enable & panel enable */
> +	dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
> +}
> +
> +static enum drm_mode_status
> +dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
> +			      const struct drm_display_mode *mode)
> +{
> +	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
> +	const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
> +	enum drm_mode_status mode_status = MODE_OK;
> +
> +	if (pdata->mode_valid)
> +		mode_status = pdata->mode_valid(pdata->priv_data, mode);
> +
> +	return mode_status;
> +}
> +
> +static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge)
> +{
> +	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
> +
> +	if (!bridge->encoder) {
> +		DRM_ERROR("Parent encoder object not found\n");
> +		return -ENODEV;
> +	}
> +
> +	/* Set the encoder type as caller does not know it */
> +	bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI;
> +
> +	/* Attach the panel-bridge to the dsi bridge */
> +	return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge);
> +}
> +
> +static struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = {
> +	.mode_set     = dw_mipi_dsi_bridge_mode_set,
> +	.enable	      = dw_mipi_dsi_bridge_enable,
> +	.post_disable = dw_mipi_dsi_bridge_post_disable,
> +	.mode_valid   = dw_mipi_dsi_bridge_mode_valid,
> +	.attach	      = dw_mipi_dsi_bridge_attach,
> +};
> +
> +static struct dw_mipi_dsi *
> +__dw_mipi_dsi_probe(struct platform_device *pdev,
> +		    const struct dw_mipi_dsi_plat_data *plat_data)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct reset_control *apb_rst;
> +	struct dw_mipi_dsi *dsi;
> +	struct resource *res;
> +	int ret;
> +
> +	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
> +	if (!dsi)
> +		return ERR_PTR(-ENOMEM);
> +
> +	dsi->dev = dev;
> +	dsi->plat_data = plat_data;
> +
> +	if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps) {
> +		DRM_ERROR("Phy not properly configured\n");
> +		return ERR_PTR(-ENODEV);
> +	}
> +
> +	if (!plat_data->base) {
> +		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +		if (!res)
> +			return ERR_PTR(-ENODEV);
> +
> +		dsi->base = devm_ioremap_resource(dev, res);
> +		if (IS_ERR(dsi->base))
> +			return ERR_PTR(-ENODEV);
> +
> +	} else {
> +		dsi->base = plat_data->base;
> +	}
> +
> +	dsi->pclk = devm_clk_get(dev, "pclk");
> +	if (IS_ERR(dsi->pclk)) {
> +		ret = PTR_ERR(dsi->pclk);
> +		dev_err(dev, "Unable to get pclk: %d\n", ret);
> +		return ERR_PTR(ret);
> +	}
> +
> +	/*
> +	 * Note that the reset was not defined in the initial device tree, so
> +	 * we have to be prepared for it not being found.
> +	 */
> +	apb_rst = devm_reset_control_get(dev, "apb");
> +	if (IS_ERR(apb_rst)) {
> +		ret = PTR_ERR(apb_rst);
> +		if (ret == -ENOENT) {
> +			apb_rst = NULL;
> +		} else {
> +			dev_err(dev, "Unable to get reset control: %d\n", ret);
> +			return ERR_PTR(ret);
> +		}
> +	}
> +
> +	if (apb_rst) {
> +		ret = clk_prepare_enable(dsi->pclk);
> +		if (ret) {
> +			dev_err(dev, "%s: Failed to enable pclk\n", __func__);
> +			return ERR_PTR(ret);
> +		}
> +
> +		reset_control_assert(apb_rst);
> +		usleep_range(10, 20);
> +		reset_control_deassert(apb_rst);
> +
> +		clk_disable_unprepare(dsi->pclk);
> +	}
> +
> +	pm_runtime_enable(dev);
> +
> +	dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
> +	dsi->dsi_host.dev = dev;
> +	ret = mipi_dsi_host_register(&dsi->dsi_host);
> +	if (ret) {
> +		dev_err(dev, "Failed to register MIPI host: %d\n", ret);
> +		return ERR_PTR(ret);
> +	}
> +
> +	dsi->bridge.driver_private = dsi;
> +	dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs;
> +#ifdef CONFIG_OF
> +	dsi->bridge.of_node = pdev->dev.of_node;
> +#endif
> +
> +	dev_set_drvdata(dev, dsi);
> +
> +	return dsi;
> +}
> +
> +static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
> +{
> +	pm_runtime_disable(dsi->dev);
> +}
> +
> +/*
> + * Probe/remove API, used from platforms based on the DRM bridge API.
> + */
> +int dw_mipi_dsi_probe(struct platform_device *pdev,
> +		      const struct dw_mipi_dsi_plat_data *plat_data)
> +{
> +	struct dw_mipi_dsi *dsi;
> +
> +	dsi = __dw_mipi_dsi_probe(pdev, plat_data);
> +	if (IS_ERR(dsi))
> +		return PTR_ERR(dsi);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe);
> +
> +void dw_mipi_dsi_remove(struct platform_device *pdev)
> +{
> +	struct dw_mipi_dsi *dsi = platform_get_drvdata(pdev);
> +
> +	mipi_dsi_host_unregister(&dsi->dsi_host);
> +
> +	__dw_mipi_dsi_remove(dsi);
> +}
> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove);
> +
> +/*
> + * Bind/unbind API, used from platforms based on the component framework.
> + */
> +int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
> +		     const struct dw_mipi_dsi_plat_data *plat_data)
> +{
> +	struct dw_mipi_dsi *dsi;
> +	int ret;
> +
> +	dsi = __dw_mipi_dsi_probe(pdev, plat_data);
> +	if (IS_ERR(dsi))
> +		return PTR_ERR(dsi);
> +
> +	ret = drm_bridge_attach(encoder, &dsi->bridge, NULL);
> +	if (ret) {
> +		dw_mipi_dsi_remove(pdev);
> +		DRM_ERROR("Failed to initialize bridge with drm\n");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
> +
> +void dw_mipi_dsi_unbind(struct device *dev)
> +{
> +	struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
> +
> +	__dw_mipi_dsi_remove(dsi);
> +}
> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
> +
> +MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
> +MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
> +MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
> +MODULE_LICENSE("GPL");
> +MODULE_ALIAS("platform:dw-mipi-dsi");
> diff --git a/include/drm/bridge/dw_mipi_dsi.h b/include/drm/bridge/dw_mipi_dsi.h
> new file mode 100644
> index 0000000..9b30fec
> --- /dev/null
> +++ b/include/drm/bridge/dw_mipi_dsi.h
> @@ -0,0 +1,39 @@
> +/*
> + * Copyright (C) STMicroelectronics SA 2017
> + *
> + * Authors: Philippe Cornu <philippe.cornu@st.com>
> + *          Yannick Fertre <yannick.fertre@st.com>
> + *
> + * License terms:  GNU General Public License (GPL), version 2
> + */
> +
> +#ifndef __DW_MIPI_DSI__
> +#define __DW_MIPI_DSI__
> +
> +struct dw_mipi_dsi_phy_ops {
> +	int (*init)(void *priv_data);
> +	int (*get_lane_mbps)(void *priv_data, struct drm_display_mode *mode,
> +			     unsigned long mode_flags, u32 lanes, u32 format,
> +			     unsigned int *lane_mbps);
> +};
> +
> +struct dw_mipi_dsi_plat_data {
> +	void __iomem *base;
> +	unsigned int max_data_lanes;
> +
> +	enum drm_mode_status (*mode_valid)(void *priv_data,
> +					   const struct drm_display_mode *mode);
> +
> +	const struct dw_mipi_dsi_phy_ops *phy_ops;
> +
> +	void *priv_data;
> +};
> +
> +int dw_mipi_dsi_probe(struct platform_device *pdev,
> +		      const struct dw_mipi_dsi_plat_data *plat_data);
> +void dw_mipi_dsi_remove(struct platform_device *pdev);
> +int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
> +		     const struct dw_mipi_dsi_plat_data *plat_data);
> +void dw_mipi_dsi_unbind(struct device *dev);
> +
> +#endif /* __DW_MIPI_DSI__ */
> 

-- 
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^ permalink raw reply	[flat|nested] 24+ messages in thread
* [PATCH v5 4/7] drm/bridge/synopsys: Add MIPI DSI host controller bridge
@ 2017-07-12  6:05     ` Archit Taneja
  0 siblings, 0 replies; 24+ messages in thread
From: Archit Taneja @ 2017-07-12  6:05 UTC (permalink / raw)
  To: linux-arm-kernel



On 07/03/2017 02:11 PM, Philippe CORNU wrote:
> Add a Synopsys Designware MIPI DSI host DRM bridge driver, based on the
> Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
> 

The patch looks good now. One thing that needs to be updated is to make
drm_bridge_add() not return anything.

The later patches in the series would be dependent on this patch, right?
Since the ST patches go via drm-misc too, we could either push all these
together, or I could push the bridge driver to drm-misc-next, and the ST
patches can be pushed after. Any preference? If not, I'll do the latter.

Archit


> Signed-off-by: Philippe CORNU <philippe.cornu@st.com>
> ---
>   drivers/gpu/drm/bridge/synopsys/Kconfig       |   6 +
>   drivers/gpu/drm/bridge/synopsys/Makefile      |   2 +
>   drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 979 ++++++++++++++++++++++++++
>   include/drm/bridge/dw_mipi_dsi.h              |  39 +
>   4 files changed, 1026 insertions(+)
>   create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>   create mode 100644 include/drm/bridge/dw_mipi_dsi.h
> 
> diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig b/drivers/gpu/drm/bridge/synopsys/Kconfig
> index 40d2827..f00ee26 100644
> --- a/drivers/gpu/drm/bridge/synopsys/Kconfig
> +++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
> @@ -21,3 +21,9 @@ config DRM_DW_HDMI_I2S_AUDIO
>   	help
>   	  Support the I2S Audio interface which is part of the Synopsys
>   	  Designware HDMI block.
> +
> +config DRM_DW_MIPI_DSI
> +	tristate
> +	select DRM_KMS_HELPER
> +	select DRM_MIPI_DSI
> +	select DRM_PANEL_BRIDGE
> diff --git a/drivers/gpu/drm/bridge/synopsys/Makefile b/drivers/gpu/drm/bridge/synopsys/Makefile
> index 17aa7a6..5f57d36 100644
> --- a/drivers/gpu/drm/bridge/synopsys/Makefile
> +++ b/drivers/gpu/drm/bridge/synopsys/Makefile
> @@ -3,3 +3,5 @@
>   obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
>   obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
>   obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
> +
> +obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw-mipi-dsi.o
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> new file mode 100644
> index 0000000..406000e
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> @@ -0,0 +1,979 @@
> +/*
> + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
> + * Copyright (C) STMicroelectronics SA 2017
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * Modified by Philippe Cornu <philippe.cornu@st.com>
> + * This generic Synopsys DesignWare MIPI DSI host driver is based on the
> + * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/iopoll.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/reset.h>
> +#include <drm/drmP.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_bridge.h>
> +#include <drm/drm_crtc.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_mipi_dsi.h>
> +#include <drm/drm_of.h>
> +#include <drm/bridge/dw_mipi_dsi.h>
> +#include <video/mipi_display.h>
> +
> +#define DSI_VERSION			0x00
> +#define DSI_PWR_UP			0x04
> +#define RESET				0
> +#define POWERUP				BIT(0)
> +
> +#define DSI_CLKMGR_CFG			0x08
> +#define TO_CLK_DIVIDSION(div)		(((div) & 0xff) << 8)
> +#define TX_ESC_CLK_DIVIDSION(div)	(((div) & 0xff) << 0)
> +
> +#define DSI_DPI_VCID			0x0c
> +#define DPI_VID(vid)			(((vid) & 0x3) << 0)
> +
> +#define DSI_DPI_COLOR_CODING		0x10
> +#define EN18_LOOSELY			BIT(8)
> +#define DPI_COLOR_CODING_16BIT_1	0x0
> +#define DPI_COLOR_CODING_16BIT_2	0x1
> +#define DPI_COLOR_CODING_16BIT_3	0x2
> +#define DPI_COLOR_CODING_18BIT_1	0x3
> +#define DPI_COLOR_CODING_18BIT_2	0x4
> +#define DPI_COLOR_CODING_24BIT		0x5
> +
> +#define DSI_DPI_CFG_POL			0x14
> +#define COLORM_ACTIVE_LOW		BIT(4)
> +#define SHUTD_ACTIVE_LOW		BIT(3)
> +#define HSYNC_ACTIVE_LOW		BIT(2)
> +#define VSYNC_ACTIVE_LOW		BIT(1)
> +#define DATAEN_ACTIVE_LOW		BIT(0)
> +
> +#define DSI_DPI_LP_CMD_TIM		0x18
> +#define OUTVACT_LPCMD_TIME(p)		(((p) & 0xff) << 16)
> +#define INVACT_LPCMD_TIME(p)		((p) & 0xff)
> +
> +#define DSI_DBI_CFG			0x20
> +#define DSI_DBI_CMDSIZE			0x28
> +
> +#define DSI_PCKHDL_CFG			0x2c
> +#define EN_CRC_RX			BIT(4)
> +#define EN_ECC_RX			BIT(3)
> +#define EN_BTA				BIT(2)
> +#define EN_EOTP_RX			BIT(1)
> +#define EN_EOTP_TX			BIT(0)
> +
> +#define DSI_MODE_CFG			0x34
> +#define ENABLE_VIDEO_MODE		0
> +#define ENABLE_CMD_MODE			BIT(0)
> +
> +#define DSI_VID_MODE_CFG		0x38
> +#define FRAME_BTA_ACK			BIT(14)
> +#define ENABLE_LOW_POWER		(0x3f << 8)
> +#define ENABLE_LOW_POWER_MASK		(0x3f << 8)
> +#define VID_MODE_TYPE_NON_BURST_SYNC_PULSES	0x0
> +#define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS	0x1
> +#define VID_MODE_TYPE_BURST			0x2
> +#define VID_MODE_TYPE_MASK			0x3
> +
> +#define DSI_VID_PKT_SIZE		0x3c
> +#define VID_PKT_SIZE(p)			(((p) & 0x3fff) << 0)
> +#define VID_PKT_MAX_SIZE		0x3fff
> +
> +#define DSI_VID_HSA_TIME		0x48
> +#define DSI_VID_HBP_TIME		0x4c
> +#define DSI_VID_HLINE_TIME		0x50
> +#define DSI_VID_VSA_LINES		0x54
> +#define DSI_VID_VBP_LINES		0x58
> +#define DSI_VID_VFP_LINES		0x5c
> +#define DSI_VID_VACTIVE_LINES		0x60
> +#define DSI_CMD_MODE_CFG		0x68
> +#define MAX_RD_PKT_SIZE_LP		BIT(24)
> +#define DCS_LW_TX_LP			BIT(19)
> +#define DCS_SR_0P_TX_LP			BIT(18)
> +#define DCS_SW_1P_TX_LP			BIT(17)
> +#define DCS_SW_0P_TX_LP			BIT(16)
> +#define GEN_LW_TX_LP			BIT(14)
> +#define GEN_SR_2P_TX_LP			BIT(13)
> +#define GEN_SR_1P_TX_LP			BIT(12)
> +#define GEN_SR_0P_TX_LP			BIT(11)
> +#define GEN_SW_2P_TX_LP			BIT(10)
> +#define GEN_SW_1P_TX_LP			BIT(9)
> +#define GEN_SW_0P_TX_LP			BIT(8)
> +#define EN_ACK_RQST			BIT(1)
> +#define EN_TEAR_FX			BIT(0)
> +
> +#define CMD_MODE_ALL_LP			(MAX_RD_PKT_SIZE_LP | \
> +					 DCS_LW_TX_LP | \
> +					 DCS_SR_0P_TX_LP | \
> +					 DCS_SW_1P_TX_LP | \
> +					 DCS_SW_0P_TX_LP | \
> +					 GEN_LW_TX_LP | \
> +					 GEN_SR_2P_TX_LP | \
> +					 GEN_SR_1P_TX_LP | \
> +					 GEN_SR_0P_TX_LP | \
> +					 GEN_SW_2P_TX_LP | \
> +					 GEN_SW_1P_TX_LP | \
> +					 GEN_SW_0P_TX_LP)
> +
> +#define DSI_GEN_HDR			0x6c
> +#define GEN_HDATA(data)			(((data) & 0xffff) << 8)
> +#define GEN_HDATA_MASK			(0xffff << 8)
> +#define GEN_HTYPE(type)			(((type) & 0xff) << 0)
> +#define GEN_HTYPE_MASK			0xff
> +
> +#define DSI_GEN_PLD_DATA		0x70
> +
> +#define DSI_CMD_PKT_STATUS		0x74
> +#define GEN_CMD_EMPTY			BIT(0)
> +#define GEN_CMD_FULL			BIT(1)
> +#define GEN_PLD_W_EMPTY			BIT(2)
> +#define GEN_PLD_W_FULL			BIT(3)
> +#define GEN_PLD_R_EMPTY			BIT(4)
> +#define GEN_PLD_R_FULL			BIT(5)
> +#define GEN_RD_CMD_BUSY			BIT(6)
> +
> +#define DSI_TO_CNT_CFG			0x78
> +#define HSTX_TO_CNT(p)			(((p) & 0xffff) << 16)
> +#define LPRX_TO_CNT(p)			((p) & 0xffff)
> +
> +#define DSI_BTA_TO_CNT			0x8c
> +#define DSI_LPCLK_CTRL			0x94
> +#define AUTO_CLKLANE_CTRL		BIT(1)
> +#define PHY_TXREQUESTCLKHS		BIT(0)
> +
> +#define DSI_PHY_TMR_LPCLK_CFG		0x98
> +#define PHY_CLKHS2LP_TIME(lbcc)		(((lbcc) & 0x3ff) << 16)
> +#define PHY_CLKLP2HS_TIME(lbcc)		((lbcc) & 0x3ff)
> +
> +#define DSI_PHY_TMR_CFG			0x9c
> +#define PHY_HS2LP_TIME(lbcc)		(((lbcc) & 0xff) << 24)
> +#define PHY_LP2HS_TIME(lbcc)		(((lbcc) & 0xff) << 16)
> +#define MAX_RD_TIME(lbcc)		((lbcc) & 0x7fff)
> +
> +#define DSI_PHY_RSTZ			0xa0
> +#define PHY_DISFORCEPLL			0
> +#define PHY_ENFORCEPLL			BIT(3)
> +#define PHY_DISABLECLK			0
> +#define PHY_ENABLECLK			BIT(2)
> +#define PHY_RSTZ			0
> +#define PHY_UNRSTZ			BIT(1)
> +#define PHY_SHUTDOWNZ			0
> +#define PHY_UNSHUTDOWNZ			BIT(0)
> +
> +#define DSI_PHY_IF_CFG			0xa4
> +#define N_LANES(n)			((((n) - 1) & 0x3) << 0)
> +#define PHY_STOP_WAIT_TIME(cycle)	(((cycle) & 0xff) << 8)
> +
> +#define DSI_PHY_STATUS			0xb0
> +#define LOCK				BIT(0)
> +#define STOP_STATE_CLK_LANE		BIT(2)
> +
> +#define DSI_PHY_TST_CTRL0		0xb4
> +#define PHY_TESTCLK			BIT(1)
> +#define PHY_UNTESTCLK			0
> +#define PHY_TESTCLR			BIT(0)
> +#define PHY_UNTESTCLR			0
> +
> +#define DSI_PHY_TST_CTRL1		0xb8
> +#define PHY_TESTEN			BIT(16)
> +#define PHY_UNTESTEN			0
> +#define PHY_TESTDOUT(n)			(((n) & 0xff) << 8)
> +#define PHY_TESTDIN(n)			(((n) & 0xff) << 0)
> +
> +#define DSI_INT_ST0			0xbc
> +#define DSI_INT_ST1			0xc0
> +#define DSI_INT_MSK0			0xc4
> +#define DSI_INT_MSK1			0xc8
> +
> +#define PHY_STATUS_TIMEOUT_US		10000
> +#define CMD_PKT_STATUS_TIMEOUT_US	20000
> +
> +struct dw_mipi_dsi {
> +	struct drm_bridge bridge;
> +	struct mipi_dsi_host dsi_host;
> +	struct drm_bridge *panel_bridge;
> +	bool is_panel_bridge;
> +	struct device *dev;
> +	void __iomem *base;
> +
> +	struct clk *pclk;
> +
> +	unsigned int lane_mbps; /* per lane */
> +	u32 channel;
> +	u32 lanes;
> +	u32 format;
> +	unsigned long mode_flags;
> +
> +	const struct dw_mipi_dsi_plat_data *plat_data;
> +};
> +
> +/*
> + * The controller should generate 2 frames before
> + * preparing the peripheral.
> + */
> +static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode *mode)
> +{
> +	int refresh, two_frames;
> +
> +	refresh = drm_mode_vrefresh(mode);
> +	two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
> +	msleep(two_frames);
> +}
> +
> +static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
> +{
> +	return container_of(host, struct dw_mipi_dsi, dsi_host);
> +}
> +
> +static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge)
> +{
> +	return container_of(bridge, struct dw_mipi_dsi, bridge);
> +}
> +
> +static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
> +{
> +	writel(val, dsi->base + reg);
> +}
> +
> +static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
> +{
> +	return readl(dsi->base + reg);
> +}
> +
> +static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
> +				   struct mipi_dsi_device *device)
> +{
> +	struct dw_mipi_dsi *dsi = host_to_dsi(host);
> +	struct drm_bridge *bridge;
> +	struct drm_panel *panel;
> +	int ret;
> +
> +	if (device->lanes > dsi->plat_data->max_data_lanes) {
> +		dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
> +			device->lanes);
> +		return -EINVAL;
> +	}
> +
> +	dsi->lanes = device->lanes;
> +	dsi->channel = device->channel;
> +	dsi->format = device->format;
> +	dsi->mode_flags = device->mode_flags;
> +
> +	ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0,
> +					  &panel, &bridge);
> +	if (ret)
> +		return ret;
> +
> +	if (panel) {
> +		bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DSI);
> +		if (IS_ERR(bridge))
> +			return PTR_ERR(bridge);
> +		dsi->is_panel_bridge = true;
> +	}
> +
> +	dsi->panel_bridge = bridge;
> +
> +	return drm_bridge_add(&dsi->bridge);
> +}
> +
> +static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
> +				   struct mipi_dsi_device *device)
> +{
> +	struct dw_mipi_dsi *dsi = host_to_dsi(host);
> +
> +	if (dsi->is_panel_bridge)
> +		drm_panel_bridge_remove(dsi->panel_bridge);
> +
> +	drm_bridge_remove(&dsi->bridge);
> +
> +	return 0;
> +}
> +
> +static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
> +				   const struct mipi_dsi_msg *msg)
> +{
> +	bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
> +	u32 val = 0;
> +
> +	if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
> +		val |= EN_ACK_RQST;
> +	if (lpm)
> +		val |= CMD_MODE_ALL_LP;
> +
> +	dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
> +	dsi_write(dsi, DSI_CMD_MODE_CFG, val);
> +}
> +
> +static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
> +{
> +	int ret;
> +	u32 val, mask;
> +
> +	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> +				 val, !(val & GEN_CMD_FULL), 1000,
> +				 CMD_PKT_STATUS_TIMEOUT_US);
> +	if (ret < 0) {
> +		dev_err(dsi->dev, "failed to get available command FIFO\n");
> +		return ret;
> +	}
> +
> +	dsi_write(dsi, DSI_GEN_HDR, hdr_val);
> +
> +	mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
> +	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> +				 val, (val & mask) == mask,
> +				 1000, CMD_PKT_STATUS_TIMEOUT_US);
> +	if (ret < 0) {
> +		dev_err(dsi->dev, "failed to write command FIFO\n");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi *dsi,
> +				       const struct mipi_dsi_msg *msg)
> +{
> +	const u8 *tx_buf = msg->tx_buf;
> +	u16 data = 0;
> +	u32 val;
> +
> +	if (msg->tx_len > 0)
> +		data |= tx_buf[0];
> +	if (msg->tx_len > 1)
> +		data |= tx_buf[1] << 8;
> +
> +	if (msg->tx_len > 2) {
> +		dev_err(dsi->dev, "too long tx buf length %zu for short write\n",
> +			msg->tx_len);
> +		return -EINVAL;
> +	}
> +
> +	val = GEN_HDATA(data) | GEN_HTYPE(msg->type);
> +	return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
> +}
> +
> +static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
> +				      const struct mipi_dsi_msg *msg)
> +{
> +	const u8 *tx_buf = msg->tx_buf;
> +	int len = msg->tx_len, pld_data_bytes = sizeof(u32), ret;
> +	u32 hdr_val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
> +	u32 remainder;
> +	u32 val;
> +
> +	if (msg->tx_len < 3) {
> +		dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
> +			msg->tx_len);
> +		return -EINVAL;
> +	}
> +
> +	while (DIV_ROUND_UP(len, pld_data_bytes)) {
> +		if (len < pld_data_bytes) {
> +			remainder = 0;
> +			memcpy(&remainder, tx_buf, len);
> +			dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
> +			len = 0;
> +		} else {
> +			memcpy(&remainder, tx_buf, pld_data_bytes);
> +			dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
> +			tx_buf += pld_data_bytes;
> +			len -= pld_data_bytes;
> +		}
> +
> +		ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> +					 val, !(val & GEN_PLD_W_FULL), 1000,
> +					 CMD_PKT_STATUS_TIMEOUT_US);
> +		if (ret < 0) {
> +			dev_err(dsi->dev,
> +				"failed to get available write payload FIFO\n");
> +			return ret;
> +		}
> +	}
> +
> +	return dw_mipi_dsi_gen_pkt_hdr_write(dsi, hdr_val);
> +}
> +
> +static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
> +					 const struct mipi_dsi_msg *msg)
> +{
> +	struct dw_mipi_dsi *dsi = host_to_dsi(host);
> +	int ret;
> +
> +	/*
> +	 * TODO dw drv improvements
> +	 * use mipi_dsi_create_packet() instead of all following
> +	 * functions and code (no switch cases, no
> +	 * dw_mipi_dsi_dcs_short_write(), only the loop in long_write...)
> +	 * and use packet.header...
> +	 */
> +	dw_mipi_message_config(dsi, msg);
> +
> +	switch (msg->type) {
> +	case MIPI_DSI_DCS_SHORT_WRITE:
> +	case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
> +	case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
> +		ret = dw_mipi_dsi_dcs_short_write(dsi, msg);
> +		break;
> +	case MIPI_DSI_DCS_LONG_WRITE:
> +		ret = dw_mipi_dsi_dcs_long_write(dsi, msg);
> +		break;
> +	default:
> +		dev_err(dsi->dev, "unsupported message type 0x%02x\n",
> +			msg->type);
> +		ret = -EINVAL;
> +	}
> +
> +	return ret;
> +}
> +
> +static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
> +	.attach = dw_mipi_dsi_host_attach,
> +	.detach = dw_mipi_dsi_host_detach,
> +	.transfer = dw_mipi_dsi_host_transfer,
> +};
> +
> +static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
> +{
> +	u32 val;
> +
> +	/*
> +	 * TODO dw drv improvements
> +	 * enabling low power is panel-dependent, we should use the
> +	 * panel configuration here...
> +	 */
> +	val = ENABLE_LOW_POWER;
> +
> +	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
> +		val |= VID_MODE_TYPE_BURST;
> +	else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
> +		val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
> +	else
> +		val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
> +
> +	dsi_write(dsi, DSI_VID_MODE_CFG, val);
> +}
> +
> +static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
> +				 unsigned long mode_flags)
> +{
> +	dsi_write(dsi, DSI_PWR_UP, RESET);
> +
> +	if (mode_flags & MIPI_DSI_MODE_VIDEO) {
> +		dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
> +		dw_mipi_dsi_video_mode_config(dsi);
> +		dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
> +	} else {
> +		dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
> +	}
> +
> +	dsi_write(dsi, DSI_PWR_UP, POWERUP);
> +}
> +
> +static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
> +{
> +	dsi_write(dsi, DSI_PWR_UP, RESET);
> +	dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
> +}
> +
> +static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
> +{
> +	/*
> +	 * The maximum permitted escape clock is 20MHz and it is derived from
> +	 * lanebyteclk, which is running at "lane_mbps / 8".  Thus we want:
> +	 *
> +	 *     (lane_mbps >> 3) / esc_clk_division < 20
> +	 * which is:
> +	 *     (lane_mbps >> 3) / 20 > esc_clk_division
> +	 */
> +	u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
> +
> +	dsi_write(dsi, DSI_PWR_UP, RESET);
> +
> +	/*
> +	 * TODO dw drv improvements
> +	 * timeout clock division should be computed with the
> +	 * high speed transmission counter timeout and byte lane...
> +	 */
> +	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
> +		  TX_ESC_CLK_DIVIDSION(esc_clk_division));
> +}
> +
> +static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
> +				   struct drm_display_mode *mode)
> +{
> +	u32 val = 0, color = 0;
> +
> +	switch (dsi->format) {
> +	case MIPI_DSI_FMT_RGB888:
> +		color = DPI_COLOR_CODING_24BIT;
> +		break;
> +	case MIPI_DSI_FMT_RGB666:
> +		color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
> +		break;
> +	case MIPI_DSI_FMT_RGB666_PACKED:
> +		color = DPI_COLOR_CODING_18BIT_1;
> +		break;
> +	case MIPI_DSI_FMT_RGB565:
> +		color = DPI_COLOR_CODING_16BIT_1;
> +		break;
> +	}
> +
> +	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
> +		val |= VSYNC_ACTIVE_LOW;
> +	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
> +		val |= HSYNC_ACTIVE_LOW;
> +
> +	dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
> +	dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
> +	dsi_write(dsi, DSI_DPI_CFG_POL, val);
> +	/*
> +	 * TODO dw drv improvements
> +	 * largest packet sizes during hfp or during vsa/vpb/vfp
> +	 * should be computed according to byte lane, lane number and only
> +	 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
> +	 */
> +	dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
> +		  | INVACT_LPCMD_TIME(4));
> +}
> +
> +static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
> +{
> +	dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
> +}
> +
> +static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
> +					    struct drm_display_mode *mode)
> +{
> +	/*
> +	 * TODO dw drv improvements
> +	 * only burst mode is supported here. For non-burst video modes,
> +	 * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
> +	 * DSI_VNPCR.NPSIZE... especially because this driver supports
> +	 * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
> +	 */
> +	dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
> +}
> +
> +static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
> +{
> +	/*
> +	 * TODO dw drv improvements
> +	 * compute high speed transmission counter timeout according
> +	 * to the timeout clock division (TO_CLK_DIVIDSION) and byte lane...
> +	 */
> +	dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
> +	/*
> +	 * TODO dw drv improvements
> +	 * the Bus-Turn-Around Timeout Counter should be computed
> +	 * according to byte lane...
> +	 */
> +	dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
> +	dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
> +}
> +
> +/* Get lane byte clock cycles. */
> +static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
> +					   struct drm_display_mode *mode,
> +					   u32 hcomponent)
> +{
> +	u32 frac, lbcc;
> +
> +	lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
> +
> +	frac = lbcc % mode->clock;
> +	lbcc = lbcc / mode->clock;
> +	if (frac)
> +		lbcc++;
> +
> +	return lbcc;
> +}
> +
> +static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
> +					  struct drm_display_mode *mode)
> +{
> +	u32 htotal, hsa, hbp, lbcc;
> +
> +	htotal = mode->htotal;
> +	hsa = mode->hsync_end - mode->hsync_start;
> +	hbp = mode->htotal - mode->hsync_end;
> +
> +	/*
> +	 * TODO dw drv improvements
> +	 * computations below may be improved...
> +	 */
> +	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
> +	dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
> +
> +	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
> +	dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
> +
> +	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
> +	dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
> +}
> +
> +static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
> +					       struct drm_display_mode *mode)
> +{
> +	u32 vactive, vsa, vfp, vbp;
> +
> +	vactive = mode->vdisplay;
> +	vsa = mode->vsync_end - mode->vsync_start;
> +	vfp = mode->vsync_start - mode->vdisplay;
> +	vbp = mode->vtotal - mode->vsync_end;
> +
> +	dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
> +	dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
> +	dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
> +	dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
> +}
> +
> +static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
> +{
> +	/*
> +	 * TODO dw drv improvements
> +	 * data & clock lane timers should be computed according to panel
> +	 * blankings and to the automatic clock lane control mode...
> +	 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
> +	 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
> +	 */
> +	dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40)
> +		  | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
> +
> +	dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
> +		  | PHY_CLKLP2HS_TIME(0x40));
> +}
> +
> +static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
> +{
> +	/*
> +	 * TODO dw drv improvements
> +	 * stop wait time should be the maximum between host dsi
> +	 * and panel stop wait times
> +	 */
> +	dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
> +		  N_LANES(dsi->lanes));
> +}
> +
> +static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
> +{
> +	/* Clear PHY state */
> +	dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
> +		  | PHY_RSTZ | PHY_SHUTDOWNZ);
> +	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
> +	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
> +	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
> +}
> +
> +static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
> +{
> +	u32 val;
> +	int ret;
> +
> +	dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
> +		  PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
> +
> +	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
> +				 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
> +	if (ret < 0)
> +		DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
> +
> +	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
> +				 val, val & STOP_STATE_CLK_LANE, 1000,
> +				 PHY_STATUS_TIMEOUT_US);
> +	if (ret < 0)
> +		DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
> +}
> +
> +static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
> +{
> +	dsi_read(dsi, DSI_INT_ST0);
> +	dsi_read(dsi, DSI_INT_ST1);
> +	dsi_write(dsi, DSI_INT_MSK0, 0);
> +	dsi_write(dsi, DSI_INT_MSK1, 0);
> +}
> +
> +static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
> +{
> +	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
> +
> +	/*
> +	 * Switch to command mode before panel-bridge post_disable &
> +	 * panel unprepare.
> +	 * Note: panel-bridge disable & panel disable has been called
> +	 * before by the drm framework.
> +	 */
> +	dw_mipi_dsi_set_mode(dsi, 0);
> +
> +	/*
> +	 * TODO Only way found to call panel-bridge post_disable &
> +	 * panel unprepare before the dsi "final" disable...
> +	 * This needs to be fixed in the drm_bridge framework and the API
> +	 * needs to be updated to manage our own call chains...
> +	 */
> +	dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge);
> +
> +	dw_mipi_dsi_disable(dsi);
> +	clk_disable_unprepare(dsi->pclk);
> +	pm_runtime_put(dsi->dev);
> +}
> +
> +void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
> +				 struct drm_display_mode *mode,
> +				 struct drm_display_mode *adjusted_mode)
> +{
> +	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
> +	const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
> +	void *priv_data = dsi->plat_data->priv_data;
> +	int ret;
> +
> +	clk_prepare_enable(dsi->pclk);
> +
> +	ret = phy_ops->get_lane_mbps(priv_data, mode, dsi->mode_flags,
> +				     dsi->lanes, dsi->format, &dsi->lane_mbps);
> +	if (ret)
> +		DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n");
> +
> +	pm_runtime_get_sync(dsi->dev);
> +	dw_mipi_dsi_init(dsi);
> +	dw_mipi_dsi_dpi_config(dsi, mode);
> +	dw_mipi_dsi_packet_handler_config(dsi);
> +	dw_mipi_dsi_video_mode_config(dsi);
> +	dw_mipi_dsi_video_packet_config(dsi, mode);
> +	dw_mipi_dsi_command_mode_config(dsi);
> +	dw_mipi_dsi_line_timer_config(dsi, mode);
> +	dw_mipi_dsi_vertical_timing_config(dsi, mode);
> +
> +	dw_mipi_dsi_dphy_init(dsi);
> +	dw_mipi_dsi_dphy_timing_config(dsi);
> +	dw_mipi_dsi_dphy_interface_config(dsi);
> +
> +	dw_mipi_dsi_clear_err(dsi);
> +
> +	ret = phy_ops->init(priv_data);
> +	if (ret)
> +		DRM_DEBUG_DRIVER("Phy init() failed\n");
> +
> +	dw_mipi_dsi_dphy_enable(dsi);
> +
> +	dw_mipi_dsi_wait_for_two_frames(mode);
> +
> +	/* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
> +	dw_mipi_dsi_set_mode(dsi, 0);
> +}
> +
> +static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge)
> +{
> +	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
> +
> +	/* Switch to video mode for panel-bridge enable & panel enable */
> +	dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
> +}
> +
> +static enum drm_mode_status
> +dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
> +			      const struct drm_display_mode *mode)
> +{
> +	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
> +	const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
> +	enum drm_mode_status mode_status = MODE_OK;
> +
> +	if (pdata->mode_valid)
> +		mode_status = pdata->mode_valid(pdata->priv_data, mode);
> +
> +	return mode_status;
> +}
> +
> +static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge)
> +{
> +	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
> +
> +	if (!bridge->encoder) {
> +		DRM_ERROR("Parent encoder object not found\n");
> +		return -ENODEV;
> +	}
> +
> +	/* Set the encoder type as caller does not know it */
> +	bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI;
> +
> +	/* Attach the panel-bridge to the dsi bridge */
> +	return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge);
> +}
> +
> +static struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = {
> +	.mode_set     = dw_mipi_dsi_bridge_mode_set,
> +	.enable	      = dw_mipi_dsi_bridge_enable,
> +	.post_disable = dw_mipi_dsi_bridge_post_disable,
> +	.mode_valid   = dw_mipi_dsi_bridge_mode_valid,
> +	.attach	      = dw_mipi_dsi_bridge_attach,
> +};
> +
> +static struct dw_mipi_dsi *
> +__dw_mipi_dsi_probe(struct platform_device *pdev,
> +		    const struct dw_mipi_dsi_plat_data *plat_data)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct reset_control *apb_rst;
> +	struct dw_mipi_dsi *dsi;
> +	struct resource *res;
> +	int ret;
> +
> +	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
> +	if (!dsi)
> +		return ERR_PTR(-ENOMEM);
> +
> +	dsi->dev = dev;
> +	dsi->plat_data = plat_data;
> +
> +	if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps) {
> +		DRM_ERROR("Phy not properly configured\n");
> +		return ERR_PTR(-ENODEV);
> +	}
> +
> +	if (!plat_data->base) {
> +		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +		if (!res)
> +			return ERR_PTR(-ENODEV);
> +
> +		dsi->base = devm_ioremap_resource(dev, res);
> +		if (IS_ERR(dsi->base))
> +			return ERR_PTR(-ENODEV);
> +
> +	} else {
> +		dsi->base = plat_data->base;
> +	}
> +
> +	dsi->pclk = devm_clk_get(dev, "pclk");
> +	if (IS_ERR(dsi->pclk)) {
> +		ret = PTR_ERR(dsi->pclk);
> +		dev_err(dev, "Unable to get pclk: %d\n", ret);
> +		return ERR_PTR(ret);
> +	}
> +
> +	/*
> +	 * Note that the reset was not defined in the initial device tree, so
> +	 * we have to be prepared for it not being found.
> +	 */
> +	apb_rst = devm_reset_control_get(dev, "apb");
> +	if (IS_ERR(apb_rst)) {
> +		ret = PTR_ERR(apb_rst);
> +		if (ret == -ENOENT) {
> +			apb_rst = NULL;
> +		} else {
> +			dev_err(dev, "Unable to get reset control: %d\n", ret);
> +			return ERR_PTR(ret);
> +		}
> +	}
> +
> +	if (apb_rst) {
> +		ret = clk_prepare_enable(dsi->pclk);
> +		if (ret) {
> +			dev_err(dev, "%s: Failed to enable pclk\n", __func__);
> +			return ERR_PTR(ret);
> +		}
> +
> +		reset_control_assert(apb_rst);
> +		usleep_range(10, 20);
> +		reset_control_deassert(apb_rst);
> +
> +		clk_disable_unprepare(dsi->pclk);
> +	}
> +
> +	pm_runtime_enable(dev);
> +
> +	dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
> +	dsi->dsi_host.dev = dev;
> +	ret = mipi_dsi_host_register(&dsi->dsi_host);
> +	if (ret) {
> +		dev_err(dev, "Failed to register MIPI host: %d\n", ret);
> +		return ERR_PTR(ret);
> +	}
> +
> +	dsi->bridge.driver_private = dsi;
> +	dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs;
> +#ifdef CONFIG_OF
> +	dsi->bridge.of_node = pdev->dev.of_node;
> +#endif
> +
> +	dev_set_drvdata(dev, dsi);
> +
> +	return dsi;
> +}
> +
> +static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
> +{
> +	pm_runtime_disable(dsi->dev);
> +}
> +
> +/*
> + * Probe/remove API, used from platforms based on the DRM bridge API.
> + */
> +int dw_mipi_dsi_probe(struct platform_device *pdev,
> +		      const struct dw_mipi_dsi_plat_data *plat_data)
> +{
> +	struct dw_mipi_dsi *dsi;
> +
> +	dsi = __dw_mipi_dsi_probe(pdev, plat_data);
> +	if (IS_ERR(dsi))
> +		return PTR_ERR(dsi);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe);
> +
> +void dw_mipi_dsi_remove(struct platform_device *pdev)
> +{
> +	struct dw_mipi_dsi *dsi = platform_get_drvdata(pdev);
> +
> +	mipi_dsi_host_unregister(&dsi->dsi_host);
> +
> +	__dw_mipi_dsi_remove(dsi);
> +}
> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove);
> +
> +/*
> + * Bind/unbind API, used from platforms based on the component framework.
> + */
> +int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
> +		     const struct dw_mipi_dsi_plat_data *plat_data)
> +{
> +	struct dw_mipi_dsi *dsi;
> +	int ret;
> +
> +	dsi = __dw_mipi_dsi_probe(pdev, plat_data);
> +	if (IS_ERR(dsi))
> +		return PTR_ERR(dsi);
> +
> +	ret = drm_bridge_attach(encoder, &dsi->bridge, NULL);
> +	if (ret) {
> +		dw_mipi_dsi_remove(pdev);
> +		DRM_ERROR("Failed to initialize bridge with drm\n");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
> +
> +void dw_mipi_dsi_unbind(struct device *dev)
> +{
> +	struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
> +
> +	__dw_mipi_dsi_remove(dsi);
> +}
> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
> +
> +MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
> +MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
> +MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
> +MODULE_LICENSE("GPL");
> +MODULE_ALIAS("platform:dw-mipi-dsi");
> diff --git a/include/drm/bridge/dw_mipi_dsi.h b/include/drm/bridge/dw_mipi_dsi.h
> new file mode 100644
> index 0000000..9b30fec
> --- /dev/null
> +++ b/include/drm/bridge/dw_mipi_dsi.h
> @@ -0,0 +1,39 @@
> +/*
> + * Copyright (C) STMicroelectronics SA 2017
> + *
> + * Authors: Philippe Cornu <philippe.cornu@st.com>
> + *          Yannick Fertre <yannick.fertre@st.com>
> + *
> + * License terms:  GNU General Public License (GPL), version 2
> + */
> +
> +#ifndef __DW_MIPI_DSI__
> +#define __DW_MIPI_DSI__
> +
> +struct dw_mipi_dsi_phy_ops {
> +	int (*init)(void *priv_data);
> +	int (*get_lane_mbps)(void *priv_data, struct drm_display_mode *mode,
> +			     unsigned long mode_flags, u32 lanes, u32 format,
> +			     unsigned int *lane_mbps);
> +};
> +
> +struct dw_mipi_dsi_plat_data {
> +	void __iomem *base;
> +	unsigned int max_data_lanes;
> +
> +	enum drm_mode_status (*mode_valid)(void *priv_data,
> +					   const struct drm_display_mode *mode);
> +
> +	const struct dw_mipi_dsi_phy_ops *phy_ops;
> +
> +	void *priv_data;
> +};
> +
> +int dw_mipi_dsi_probe(struct platform_device *pdev,
> +		      const struct dw_mipi_dsi_plat_data *plat_data);
> +void dw_mipi_dsi_remove(struct platform_device *pdev);
> +int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
> +		     const struct dw_mipi_dsi_plat_data *plat_data);
> +void dw_mipi_dsi_unbind(struct device *dev);
> +
> +#endif /* __DW_MIPI_DSI__ */
> 

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v5 4/7] drm/bridge/synopsys: Add MIPI DSI host controller bridge
  2017-07-12  6:05     ` Archit Taneja
@ 2017-07-17  7:54       ` Philippe CORNU
  -1 siblings, 0 replies; 24+ messages in thread
From: Philippe CORNU @ 2017-07-17  7:54 UTC (permalink / raw)
  To: Archit Taneja, Alexandre TORGUE, Thierry Reding, David Airlie,
	Maxime Coquelin, Russell King, Mark Rutland, Rob Herring,
	Arnd Bergmann, Benjamin Gaignard, Yannick FERTRE, Neil Armstrong,
	Eric Anholt, Chris Zhong, Andrzej Hajda, Xinliang Liu,
	zourongrong, Xinwei Kong, Chen Feng, Mark Yao
  Cc: devicetree, dri-devel, Fabien DESSENNE, Ludovic BARRE,
	Mickael REULIER, Vincent ABRIOU, Gabriel FERNANDEZ,
	linux-arm-kernel



On 07/12/2017 08:05 AM, Archit Taneja wrote:
> 
> 
> On 07/03/2017 02:11 PM, Philippe CORNU wrote:
>> Add a Synopsys Designware MIPI DSI host DRM bridge driver, based on the
>> Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
>>
> 
> The patch looks good now. One thing that needs to be updated is to make
> drm_bridge_add() not return anything.

Hi Archit and many thanks for your review.
I have just sent a v6 version adding the drm_bridge_add() small fix.

> 
> The later patches in the series would be dependent on this patch, right?
yes

> Since the ST patches go via drm-misc too, we could either push all these
> together, or I could push the bridge driver to drm-misc-next, and the ST
> patches can be pushed after. Any preference? If not, I'll do the latter.
> 
> Archit
> 
The v6 version has been tested on today drm-misc-next branch (few 
minutes ago). You can push the entire serie as it is maybe the most 
simple solution. Or you can push "up to the synopsys part" and Benjamin 
& I will push the remaining part. In fact, it is up to you, simply tell 
us your preferred approach.

Once again, many thanks,
Philippe


>> Signed-off-by: Philippe CORNU <philippe.cornu@st.com>
>> ---
>>   drivers/gpu/drm/bridge/synopsys/Kconfig       |   6 +
>>   drivers/gpu/drm/bridge/synopsys/Makefile      |   2 +
>>   drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 979 
>> ++++++++++++++++++++++++++
>>   include/drm/bridge/dw_mipi_dsi.h              |  39 +
>>   4 files changed, 1026 insertions(+)
>>   create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>>   create mode 100644 include/drm/bridge/dw_mipi_dsi.h
>>
>> diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig 
>> b/drivers/gpu/drm/bridge/synopsys/Kconfig
>> index 40d2827..f00ee26 100644
>> --- a/drivers/gpu/drm/bridge/synopsys/Kconfig
>> +++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
>> @@ -21,3 +21,9 @@ config DRM_DW_HDMI_I2S_AUDIO
>>       help
>>         Support the I2S Audio interface which is part of the Synopsys
>>         Designware HDMI block.
>> +
>> +config DRM_DW_MIPI_DSI
>> +    tristate
>> +    select DRM_KMS_HELPER
>> +    select DRM_MIPI_DSI
>> +    select DRM_PANEL_BRIDGE
>> diff --git a/drivers/gpu/drm/bridge/synopsys/Makefile 
>> b/drivers/gpu/drm/bridge/synopsys/Makefile
>> index 17aa7a6..5f57d36 100644
>> --- a/drivers/gpu/drm/bridge/synopsys/Makefile
>> +++ b/drivers/gpu/drm/bridge/synopsys/Makefile
>> @@ -3,3 +3,5 @@
>>   obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
>>   obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
>>   obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
>> +
>> +obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw-mipi-dsi.o
>> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
>> b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>> new file mode 100644
>> index 0000000..406000e
>> --- /dev/null
>> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>> @@ -0,0 +1,979 @@
>> +/*
>> + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
>> + * Copyright (C) STMicroelectronics SA 2017
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * Modified by Philippe Cornu <philippe.cornu@st.com>
>> + * This generic Synopsys DesignWare MIPI DSI host driver is based on the
>> + * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/component.h>
>> +#include <linux/iopoll.h>
>> +#include <linux/module.h>
>> +#include <linux/of_device.h>
>> +#include <linux/pm_runtime.h>
>> +#include <linux/reset.h>
>> +#include <drm/drmP.h>
>> +#include <drm/drm_atomic_helper.h>
>> +#include <drm/drm_bridge.h>
>> +#include <drm/drm_crtc.h>
>> +#include <drm/drm_crtc_helper.h>
>> +#include <drm/drm_mipi_dsi.h>
>> +#include <drm/drm_of.h>
>> +#include <drm/bridge/dw_mipi_dsi.h>
>> +#include <video/mipi_display.h>
>> +
>> +#define DSI_VERSION            0x00
>> +#define DSI_PWR_UP            0x04
>> +#define RESET                0
>> +#define POWERUP                BIT(0)
>> +
>> +#define DSI_CLKMGR_CFG            0x08
>> +#define TO_CLK_DIVIDSION(div)        (((div) & 0xff) << 8)
>> +#define TX_ESC_CLK_DIVIDSION(div)    (((div) & 0xff) << 0)
>> +
>> +#define DSI_DPI_VCID            0x0c
>> +#define DPI_VID(vid)            (((vid) & 0x3) << 0)
>> +
>> +#define DSI_DPI_COLOR_CODING        0x10
>> +#define EN18_LOOSELY            BIT(8)
>> +#define DPI_COLOR_CODING_16BIT_1    0x0
>> +#define DPI_COLOR_CODING_16BIT_2    0x1
>> +#define DPI_COLOR_CODING_16BIT_3    0x2
>> +#define DPI_COLOR_CODING_18BIT_1    0x3
>> +#define DPI_COLOR_CODING_18BIT_2    0x4
>> +#define DPI_COLOR_CODING_24BIT        0x5
>> +
>> +#define DSI_DPI_CFG_POL            0x14
>> +#define COLORM_ACTIVE_LOW        BIT(4)
>> +#define SHUTD_ACTIVE_LOW        BIT(3)
>> +#define HSYNC_ACTIVE_LOW        BIT(2)
>> +#define VSYNC_ACTIVE_LOW        BIT(1)
>> +#define DATAEN_ACTIVE_LOW        BIT(0)
>> +
>> +#define DSI_DPI_LP_CMD_TIM        0x18
>> +#define OUTVACT_LPCMD_TIME(p)        (((p) & 0xff) << 16)
>> +#define INVACT_LPCMD_TIME(p)        ((p) & 0xff)
>> +
>> +#define DSI_DBI_CFG            0x20
>> +#define DSI_DBI_CMDSIZE            0x28
>> +
>> +#define DSI_PCKHDL_CFG            0x2c
>> +#define EN_CRC_RX            BIT(4)
>> +#define EN_ECC_RX            BIT(3)
>> +#define EN_BTA                BIT(2)
>> +#define EN_EOTP_RX            BIT(1)
>> +#define EN_EOTP_TX            BIT(0)
>> +
>> +#define DSI_MODE_CFG            0x34
>> +#define ENABLE_VIDEO_MODE        0
>> +#define ENABLE_CMD_MODE            BIT(0)
>> +
>> +#define DSI_VID_MODE_CFG        0x38
>> +#define FRAME_BTA_ACK            BIT(14)
>> +#define ENABLE_LOW_POWER        (0x3f << 8)
>> +#define ENABLE_LOW_POWER_MASK        (0x3f << 8)
>> +#define VID_MODE_TYPE_NON_BURST_SYNC_PULSES    0x0
>> +#define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS    0x1
>> +#define VID_MODE_TYPE_BURST            0x2
>> +#define VID_MODE_TYPE_MASK            0x3
>> +
>> +#define DSI_VID_PKT_SIZE        0x3c
>> +#define VID_PKT_SIZE(p)            (((p) & 0x3fff) << 0)
>> +#define VID_PKT_MAX_SIZE        0x3fff
>> +
>> +#define DSI_VID_HSA_TIME        0x48
>> +#define DSI_VID_HBP_TIME        0x4c
>> +#define DSI_VID_HLINE_TIME        0x50
>> +#define DSI_VID_VSA_LINES        0x54
>> +#define DSI_VID_VBP_LINES        0x58
>> +#define DSI_VID_VFP_LINES        0x5c
>> +#define DSI_VID_VACTIVE_LINES        0x60
>> +#define DSI_CMD_MODE_CFG        0x68
>> +#define MAX_RD_PKT_SIZE_LP        BIT(24)
>> +#define DCS_LW_TX_LP            BIT(19)
>> +#define DCS_SR_0P_TX_LP            BIT(18)
>> +#define DCS_SW_1P_TX_LP            BIT(17)
>> +#define DCS_SW_0P_TX_LP            BIT(16)
>> +#define GEN_LW_TX_LP            BIT(14)
>> +#define GEN_SR_2P_TX_LP            BIT(13)
>> +#define GEN_SR_1P_TX_LP            BIT(12)
>> +#define GEN_SR_0P_TX_LP            BIT(11)
>> +#define GEN_SW_2P_TX_LP            BIT(10)
>> +#define GEN_SW_1P_TX_LP            BIT(9)
>> +#define GEN_SW_0P_TX_LP            BIT(8)
>> +#define EN_ACK_RQST            BIT(1)
>> +#define EN_TEAR_FX            BIT(0)
>> +
>> +#define CMD_MODE_ALL_LP            (MAX_RD_PKT_SIZE_LP | \
>> +                     DCS_LW_TX_LP | \
>> +                     DCS_SR_0P_TX_LP | \
>> +                     DCS_SW_1P_TX_LP | \
>> +                     DCS_SW_0P_TX_LP | \
>> +                     GEN_LW_TX_LP | \
>> +                     GEN_SR_2P_TX_LP | \
>> +                     GEN_SR_1P_TX_LP | \
>> +                     GEN_SR_0P_TX_LP | \
>> +                     GEN_SW_2P_TX_LP | \
>> +                     GEN_SW_1P_TX_LP | \
>> +                     GEN_SW_0P_TX_LP)
>> +
>> +#define DSI_GEN_HDR            0x6c
>> +#define GEN_HDATA(data)            (((data) & 0xffff) << 8)
>> +#define GEN_HDATA_MASK            (0xffff << 8)
>> +#define GEN_HTYPE(type)            (((type) & 0xff) << 0)
>> +#define GEN_HTYPE_MASK            0xff
>> +
>> +#define DSI_GEN_PLD_DATA        0x70
>> +
>> +#define DSI_CMD_PKT_STATUS        0x74
>> +#define GEN_CMD_EMPTY            BIT(0)
>> +#define GEN_CMD_FULL            BIT(1)
>> +#define GEN_PLD_W_EMPTY            BIT(2)
>> +#define GEN_PLD_W_FULL            BIT(3)
>> +#define GEN_PLD_R_EMPTY            BIT(4)
>> +#define GEN_PLD_R_FULL            BIT(5)
>> +#define GEN_RD_CMD_BUSY            BIT(6)
>> +
>> +#define DSI_TO_CNT_CFG            0x78
>> +#define HSTX_TO_CNT(p)            (((p) & 0xffff) << 16)
>> +#define LPRX_TO_CNT(p)            ((p) & 0xffff)
>> +
>> +#define DSI_BTA_TO_CNT            0x8c
>> +#define DSI_LPCLK_CTRL            0x94
>> +#define AUTO_CLKLANE_CTRL        BIT(1)
>> +#define PHY_TXREQUESTCLKHS        BIT(0)
>> +
>> +#define DSI_PHY_TMR_LPCLK_CFG        0x98
>> +#define PHY_CLKHS2LP_TIME(lbcc)        (((lbcc) & 0x3ff) << 16)
>> +#define PHY_CLKLP2HS_TIME(lbcc)        ((lbcc) & 0x3ff)
>> +
>> +#define DSI_PHY_TMR_CFG            0x9c
>> +#define PHY_HS2LP_TIME(lbcc)        (((lbcc) & 0xff) << 24)
>> +#define PHY_LP2HS_TIME(lbcc)        (((lbcc) & 0xff) << 16)
>> +#define MAX_RD_TIME(lbcc)        ((lbcc) & 0x7fff)
>> +
>> +#define DSI_PHY_RSTZ            0xa0
>> +#define PHY_DISFORCEPLL            0
>> +#define PHY_ENFORCEPLL            BIT(3)
>> +#define PHY_DISABLECLK            0
>> +#define PHY_ENABLECLK            BIT(2)
>> +#define PHY_RSTZ            0
>> +#define PHY_UNRSTZ            BIT(1)
>> +#define PHY_SHUTDOWNZ            0
>> +#define PHY_UNSHUTDOWNZ            BIT(0)
>> +
>> +#define DSI_PHY_IF_CFG            0xa4
>> +#define N_LANES(n)            ((((n) - 1) & 0x3) << 0)
>> +#define PHY_STOP_WAIT_TIME(cycle)    (((cycle) & 0xff) << 8)
>> +
>> +#define DSI_PHY_STATUS            0xb0
>> +#define LOCK                BIT(0)
>> +#define STOP_STATE_CLK_LANE        BIT(2)
>> +
>> +#define DSI_PHY_TST_CTRL0        0xb4
>> +#define PHY_TESTCLK            BIT(1)
>> +#define PHY_UNTESTCLK            0
>> +#define PHY_TESTCLR            BIT(0)
>> +#define PHY_UNTESTCLR            0
>> +
>> +#define DSI_PHY_TST_CTRL1        0xb8
>> +#define PHY_TESTEN            BIT(16)
>> +#define PHY_UNTESTEN            0
>> +#define PHY_TESTDOUT(n)            (((n) & 0xff) << 8)
>> +#define PHY_TESTDIN(n)            (((n) & 0xff) << 0)
>> +
>> +#define DSI_INT_ST0            0xbc
>> +#define DSI_INT_ST1            0xc0
>> +#define DSI_INT_MSK0            0xc4
>> +#define DSI_INT_MSK1            0xc8
>> +
>> +#define PHY_STATUS_TIMEOUT_US        10000
>> +#define CMD_PKT_STATUS_TIMEOUT_US    20000
>> +
>> +struct dw_mipi_dsi {
>> +    struct drm_bridge bridge;
>> +    struct mipi_dsi_host dsi_host;
>> +    struct drm_bridge *panel_bridge;
>> +    bool is_panel_bridge;
>> +    struct device *dev;
>> +    void __iomem *base;
>> +
>> +    struct clk *pclk;
>> +
>> +    unsigned int lane_mbps; /* per lane */
>> +    u32 channel;
>> +    u32 lanes;
>> +    u32 format;
>> +    unsigned long mode_flags;
>> +
>> +    const struct dw_mipi_dsi_plat_data *plat_data;
>> +};
>> +
>> +/*
>> + * The controller should generate 2 frames before
>> + * preparing the peripheral.
>> + */
>> +static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode 
>> *mode)
>> +{
>> +    int refresh, two_frames;
>> +
>> +    refresh = drm_mode_vrefresh(mode);
>> +    two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
>> +    msleep(two_frames);
>> +}
>> +
>> +static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host 
>> *host)
>> +{
>> +    return container_of(host, struct dw_mipi_dsi, dsi_host);
>> +}
>> +
>> +static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge 
>> *bridge)
>> +{
>> +    return container_of(bridge, struct dw_mipi_dsi, bridge);
>> +}
>> +
>> +static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
>> +{
>> +    writel(val, dsi->base + reg);
>> +}
>> +
>> +static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
>> +{
>> +    return readl(dsi->base + reg);
>> +}
>> +
>> +static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
>> +                   struct mipi_dsi_device *device)
>> +{
>> +    struct dw_mipi_dsi *dsi = host_to_dsi(host);
>> +    struct drm_bridge *bridge;
>> +    struct drm_panel *panel;
>> +    int ret;
>> +
>> +    if (device->lanes > dsi->plat_data->max_data_lanes) {
>> +        dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
>> +            device->lanes);
>> +        return -EINVAL;
>> +    }
>> +
>> +    dsi->lanes = device->lanes;
>> +    dsi->channel = device->channel;
>> +    dsi->format = device->format;
>> +    dsi->mode_flags = device->mode_flags;
>> +
>> +    ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0,
>> +                      &panel, &bridge);
>> +    if (ret)
>> +        return ret;
>> +
>> +    if (panel) {
>> +        bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DSI);
>> +        if (IS_ERR(bridge))
>> +            return PTR_ERR(bridge);
>> +        dsi->is_panel_bridge = true;
>> +    }
>> +
>> +    dsi->panel_bridge = bridge;
>> +
>> +    return drm_bridge_add(&dsi->bridge);
>> +}
>> +
>> +static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
>> +                   struct mipi_dsi_device *device)
>> +{
>> +    struct dw_mipi_dsi *dsi = host_to_dsi(host);
>> +
>> +    if (dsi->is_panel_bridge)
>> +        drm_panel_bridge_remove(dsi->panel_bridge);
>> +
>> +    drm_bridge_remove(&dsi->bridge);
>> +
>> +    return 0;
>> +}
>> +
>> +static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
>> +                   const struct mipi_dsi_msg *msg)
>> +{
>> +    bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
>> +    u32 val = 0;
>> +
>> +    if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
>> +        val |= EN_ACK_RQST;
>> +    if (lpm)
>> +        val |= CMD_MODE_ALL_LP;
>> +
>> +    dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
>> +    dsi_write(dsi, DSI_CMD_MODE_CFG, val);
>> +}
>> +
>> +static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 
>> hdr_val)
>> +{
>> +    int ret;
>> +    u32 val, mask;
>> +
>> +    ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
>> +                 val, !(val & GEN_CMD_FULL), 1000,
>> +                 CMD_PKT_STATUS_TIMEOUT_US);
>> +    if (ret < 0) {
>> +        dev_err(dsi->dev, "failed to get available command FIFO\n");
>> +        return ret;
>> +    }
>> +
>> +    dsi_write(dsi, DSI_GEN_HDR, hdr_val);
>> +
>> +    mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
>> +    ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
>> +                 val, (val & mask) == mask,
>> +                 1000, CMD_PKT_STATUS_TIMEOUT_US);
>> +    if (ret < 0) {
>> +        dev_err(dsi->dev, "failed to write command FIFO\n");
>> +        return ret;
>> +    }
>> +
>> +    return 0;
>> +}
>> +
>> +static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi *dsi,
>> +                       const struct mipi_dsi_msg *msg)
>> +{
>> +    const u8 *tx_buf = msg->tx_buf;
>> +    u16 data = 0;
>> +    u32 val;
>> +
>> +    if (msg->tx_len > 0)
>> +        data |= tx_buf[0];
>> +    if (msg->tx_len > 1)
>> +        data |= tx_buf[1] << 8;
>> +
>> +    if (msg->tx_len > 2) {
>> +        dev_err(dsi->dev, "too long tx buf length %zu for short 
>> write\n",
>> +            msg->tx_len);
>> +        return -EINVAL;
>> +    }
>> +
>> +    val = GEN_HDATA(data) | GEN_HTYPE(msg->type);
>> +    return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
>> +}
>> +
>> +static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
>> +                      const struct mipi_dsi_msg *msg)
>> +{
>> +    const u8 *tx_buf = msg->tx_buf;
>> +    int len = msg->tx_len, pld_data_bytes = sizeof(u32), ret;
>> +    u32 hdr_val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
>> +    u32 remainder;
>> +    u32 val;
>> +
>> +    if (msg->tx_len < 3) {
>> +        dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
>> +            msg->tx_len);
>> +        return -EINVAL;
>> +    }
>> +
>> +    while (DIV_ROUND_UP(len, pld_data_bytes)) {
>> +        if (len < pld_data_bytes) {
>> +            remainder = 0;
>> +            memcpy(&remainder, tx_buf, len);
>> +            dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
>> +            len = 0;
>> +        } else {
>> +            memcpy(&remainder, tx_buf, pld_data_bytes);
>> +            dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
>> +            tx_buf += pld_data_bytes;
>> +            len -= pld_data_bytes;
>> +        }
>> +
>> +        ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
>> +                     val, !(val & GEN_PLD_W_FULL), 1000,
>> +                     CMD_PKT_STATUS_TIMEOUT_US);
>> +        if (ret < 0) {
>> +            dev_err(dsi->dev,
>> +                "failed to get available write payload FIFO\n");
>> +            return ret;
>> +        }
>> +    }
>> +
>> +    return dw_mipi_dsi_gen_pkt_hdr_write(dsi, hdr_val);
>> +}
>> +
>> +static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
>> +                     const struct mipi_dsi_msg *msg)
>> +{
>> +    struct dw_mipi_dsi *dsi = host_to_dsi(host);
>> +    int ret;
>> +
>> +    /*
>> +     * TODO dw drv improvements
>> +     * use mipi_dsi_create_packet() instead of all following
>> +     * functions and code (no switch cases, no
>> +     * dw_mipi_dsi_dcs_short_write(), only the loop in long_write...)
>> +     * and use packet.header...
>> +     */
>> +    dw_mipi_message_config(dsi, msg);
>> +
>> +    switch (msg->type) {
>> +    case MIPI_DSI_DCS_SHORT_WRITE:
>> +    case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
>> +    case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
>> +        ret = dw_mipi_dsi_dcs_short_write(dsi, msg);
>> +        break;
>> +    case MIPI_DSI_DCS_LONG_WRITE:
>> +        ret = dw_mipi_dsi_dcs_long_write(dsi, msg);
>> +        break;
>> +    default:
>> +        dev_err(dsi->dev, "unsupported message type 0x%02x\n",
>> +            msg->type);
>> +        ret = -EINVAL;
>> +    }
>> +
>> +    return ret;
>> +}
>> +
>> +static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
>> +    .attach = dw_mipi_dsi_host_attach,
>> +    .detach = dw_mipi_dsi_host_detach,
>> +    .transfer = dw_mipi_dsi_host_transfer,
>> +};
>> +
>> +static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
>> +{
>> +    u32 val;
>> +
>> +    /*
>> +     * TODO dw drv improvements
>> +     * enabling low power is panel-dependent, we should use the
>> +     * panel configuration here...
>> +     */
>> +    val = ENABLE_LOW_POWER;
>> +
>> +    if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
>> +        val |= VID_MODE_TYPE_BURST;
>> +    else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
>> +        val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
>> +    else
>> +        val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
>> +
>> +    dsi_write(dsi, DSI_VID_MODE_CFG, val);
>> +}
>> +
>> +static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
>> +                 unsigned long mode_flags)
>> +{
>> +    dsi_write(dsi, DSI_PWR_UP, RESET);
>> +
>> +    if (mode_flags & MIPI_DSI_MODE_VIDEO) {
>> +        dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
>> +        dw_mipi_dsi_video_mode_config(dsi);
>> +        dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
>> +    } else {
>> +        dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
>> +    }
>> +
>> +    dsi_write(dsi, DSI_PWR_UP, POWERUP);
>> +}
>> +
>> +static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
>> +{
>> +    dsi_write(dsi, DSI_PWR_UP, RESET);
>> +    dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
>> +}
>> +
>> +static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
>> +{
>> +    /*
>> +     * The maximum permitted escape clock is 20MHz and it is derived 
>> from
>> +     * lanebyteclk, which is running at "lane_mbps / 8".  Thus we want:
>> +     *
>> +     *     (lane_mbps >> 3) / esc_clk_division < 20
>> +     * which is:
>> +     *     (lane_mbps >> 3) / 20 > esc_clk_division
>> +     */
>> +    u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
>> +
>> +    dsi_write(dsi, DSI_PWR_UP, RESET);
>> +
>> +    /*
>> +     * TODO dw drv improvements
>> +     * timeout clock division should be computed with the
>> +     * high speed transmission counter timeout and byte lane...
>> +     */
>> +    dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
>> +          TX_ESC_CLK_DIVIDSION(esc_clk_division));
>> +}
>> +
>> +static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
>> +                   struct drm_display_mode *mode)
>> +{
>> +    u32 val = 0, color = 0;
>> +
>> +    switch (dsi->format) {
>> +    case MIPI_DSI_FMT_RGB888:
>> +        color = DPI_COLOR_CODING_24BIT;
>> +        break;
>> +    case MIPI_DSI_FMT_RGB666:
>> +        color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
>> +        break;
>> +    case MIPI_DSI_FMT_RGB666_PACKED:
>> +        color = DPI_COLOR_CODING_18BIT_1;
>> +        break;
>> +    case MIPI_DSI_FMT_RGB565:
>> +        color = DPI_COLOR_CODING_16BIT_1;
>> +        break;
>> +    }
>> +
>> +    if (mode->flags & DRM_MODE_FLAG_NVSYNC)
>> +        val |= VSYNC_ACTIVE_LOW;
>> +    if (mode->flags & DRM_MODE_FLAG_NHSYNC)
>> +        val |= HSYNC_ACTIVE_LOW;
>> +
>> +    dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
>> +    dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
>> +    dsi_write(dsi, DSI_DPI_CFG_POL, val);
>> +    /*
>> +     * TODO dw drv improvements
>> +     * largest packet sizes during hfp or during vsa/vpb/vfp
>> +     * should be computed according to byte lane, lane number and only
>> +     * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
>> +     */
>> +    dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
>> +          | INVACT_LPCMD_TIME(4));
>> +}
>> +
>> +static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
>> +{
>> +    dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
>> +}
>> +
>> +static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
>> +                        struct drm_display_mode *mode)
>> +{
>> +    /*
>> +     * TODO dw drv improvements
>> +     * only burst mode is supported here. For non-burst video modes,
>> +     * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
>> +     * DSI_VNPCR.NPSIZE... especially because this driver supports
>> +     * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
>> +     */
>> +    dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
>> +}
>> +
>> +static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
>> +{
>> +    /*
>> +     * TODO dw drv improvements
>> +     * compute high speed transmission counter timeout according
>> +     * to the timeout clock division (TO_CLK_DIVIDSION) and byte lane...
>> +     */
>> +    dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | 
>> LPRX_TO_CNT(1000));
>> +    /*
>> +     * TODO dw drv improvements
>> +     * the Bus-Turn-Around Timeout Counter should be computed
>> +     * according to byte lane...
>> +     */
>> +    dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
>> +    dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
>> +}
>> +
>> +/* Get lane byte clock cycles. */
>> +static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
>> +                       struct drm_display_mode *mode,
>> +                       u32 hcomponent)
>> +{
>> +    u32 frac, lbcc;
>> +
>> +    lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
>> +
>> +    frac = lbcc % mode->clock;
>> +    lbcc = lbcc / mode->clock;
>> +    if (frac)
>> +        lbcc++;
>> +
>> +    return lbcc;
>> +}
>> +
>> +static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
>> +                      struct drm_display_mode *mode)
>> +{
>> +    u32 htotal, hsa, hbp, lbcc;
>> +
>> +    htotal = mode->htotal;
>> +    hsa = mode->hsync_end - mode->hsync_start;
>> +    hbp = mode->htotal - mode->hsync_end;
>> +
>> +    /*
>> +     * TODO dw drv improvements
>> +     * computations below may be improved...
>> +     */
>> +    lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
>> +    dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
>> +
>> +    lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
>> +    dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
>> +
>> +    lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
>> +    dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
>> +}
>> +
>> +static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
>> +                           struct drm_display_mode *mode)
>> +{
>> +    u32 vactive, vsa, vfp, vbp;
>> +
>> +    vactive = mode->vdisplay;
>> +    vsa = mode->vsync_end - mode->vsync_start;
>> +    vfp = mode->vsync_start - mode->vdisplay;
>> +    vbp = mode->vtotal - mode->vsync_end;
>> +
>> +    dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
>> +    dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
>> +    dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
>> +    dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
>> +}
>> +
>> +static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
>> +{
>> +    /*
>> +     * TODO dw drv improvements
>> +     * data & clock lane timers should be computed according to panel
>> +     * blankings and to the automatic clock lane control mode...
>> +     * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
>> +     * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
>> +     */
>> +    dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40)
>> +          | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
>> +
>> +    dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
>> +          | PHY_CLKLP2HS_TIME(0x40));
>> +}
>> +
>> +static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
>> +{
>> +    /*
>> +     * TODO dw drv improvements
>> +     * stop wait time should be the maximum between host dsi
>> +     * and panel stop wait times
>> +     */
>> +    dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
>> +          N_LANES(dsi->lanes));
>> +}
>> +
>> +static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
>> +{
>> +    /* Clear PHY state */
>> +    dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
>> +          | PHY_RSTZ | PHY_SHUTDOWNZ);
>> +    dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
>> +    dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
>> +    dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
>> +}
>> +
>> +static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
>> +{
>> +    u32 val;
>> +    int ret;
>> +
>> +    dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
>> +          PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
>> +
>> +    ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
>> +                 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
>> +    if (ret < 0)
>> +        DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
>> +
>> +    ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
>> +                 val, val & STOP_STATE_CLK_LANE, 1000,
>> +                 PHY_STATUS_TIMEOUT_US);
>> +    if (ret < 0)
>> +        DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
>> +}
>> +
>> +static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
>> +{
>> +    dsi_read(dsi, DSI_INT_ST0);
>> +    dsi_read(dsi, DSI_INT_ST1);
>> +    dsi_write(dsi, DSI_INT_MSK0, 0);
>> +    dsi_write(dsi, DSI_INT_MSK1, 0);
>> +}
>> +
>> +static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
>> +{
>> +    struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
>> +
>> +    /*
>> +     * Switch to command mode before panel-bridge post_disable &
>> +     * panel unprepare.
>> +     * Note: panel-bridge disable & panel disable has been called
>> +     * before by the drm framework.
>> +     */
>> +    dw_mipi_dsi_set_mode(dsi, 0);
>> +
>> +    /*
>> +     * TODO Only way found to call panel-bridge post_disable &
>> +     * panel unprepare before the dsi "final" disable...
>> +     * This needs to be fixed in the drm_bridge framework and the API
>> +     * needs to be updated to manage our own call chains...
>> +     */
>> +    dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge);
>> +
>> +    dw_mipi_dsi_disable(dsi);
>> +    clk_disable_unprepare(dsi->pclk);
>> +    pm_runtime_put(dsi->dev);
>> +}
>> +
>> +void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
>> +                 struct drm_display_mode *mode,
>> +                 struct drm_display_mode *adjusted_mode)
>> +{
>> +    struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
>> +    const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
>> +    void *priv_data = dsi->plat_data->priv_data;
>> +    int ret;
>> +
>> +    clk_prepare_enable(dsi->pclk);
>> +
>> +    ret = phy_ops->get_lane_mbps(priv_data, mode, dsi->mode_flags,
>> +                     dsi->lanes, dsi->format, &dsi->lane_mbps);
>> +    if (ret)
>> +        DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n");
>> +
>> +    pm_runtime_get_sync(dsi->dev);
>> +    dw_mipi_dsi_init(dsi);
>> +    dw_mipi_dsi_dpi_config(dsi, mode);
>> +    dw_mipi_dsi_packet_handler_config(dsi);
>> +    dw_mipi_dsi_video_mode_config(dsi);
>> +    dw_mipi_dsi_video_packet_config(dsi, mode);
>> +    dw_mipi_dsi_command_mode_config(dsi);
>> +    dw_mipi_dsi_line_timer_config(dsi, mode);
>> +    dw_mipi_dsi_vertical_timing_config(dsi, mode);
>> +
>> +    dw_mipi_dsi_dphy_init(dsi);
>> +    dw_mipi_dsi_dphy_timing_config(dsi);
>> +    dw_mipi_dsi_dphy_interface_config(dsi);
>> +
>> +    dw_mipi_dsi_clear_err(dsi);
>> +
>> +    ret = phy_ops->init(priv_data);
>> +    if (ret)
>> +        DRM_DEBUG_DRIVER("Phy init() failed\n");
>> +
>> +    dw_mipi_dsi_dphy_enable(dsi);
>> +
>> +    dw_mipi_dsi_wait_for_two_frames(mode);
>> +
>> +    /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
>> +    dw_mipi_dsi_set_mode(dsi, 0);
>> +}
>> +
>> +static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge)
>> +{
>> +    struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
>> +
>> +    /* Switch to video mode for panel-bridge enable & panel enable */
>> +    dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
>> +}
>> +
>> +static enum drm_mode_status
>> +dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
>> +                  const struct drm_display_mode *mode)
>> +{
>> +    struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
>> +    const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
>> +    enum drm_mode_status mode_status = MODE_OK;
>> +
>> +    if (pdata->mode_valid)
>> +        mode_status = pdata->mode_valid(pdata->priv_data, mode);
>> +
>> +    return mode_status;
>> +}
>> +
>> +static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge)
>> +{
>> +    struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
>> +
>> +    if (!bridge->encoder) {
>> +        DRM_ERROR("Parent encoder object not found\n");
>> +        return -ENODEV;
>> +    }
>> +
>> +    /* Set the encoder type as caller does not know it */
>> +    bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI;
>> +
>> +    /* Attach the panel-bridge to the dsi bridge */
>> +    return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, 
>> bridge);
>> +}
>> +
>> +static struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = {
>> +    .mode_set     = dw_mipi_dsi_bridge_mode_set,
>> +    .enable          = dw_mipi_dsi_bridge_enable,
>> +    .post_disable = dw_mipi_dsi_bridge_post_disable,
>> +    .mode_valid   = dw_mipi_dsi_bridge_mode_valid,
>> +    .attach          = dw_mipi_dsi_bridge_attach,
>> +};
>> +
>> +static struct dw_mipi_dsi *
>> +__dw_mipi_dsi_probe(struct platform_device *pdev,
>> +            const struct dw_mipi_dsi_plat_data *plat_data)
>> +{
>> +    struct device *dev = &pdev->dev;
>> +    struct reset_control *apb_rst;
>> +    struct dw_mipi_dsi *dsi;
>> +    struct resource *res;
>> +    int ret;
>> +
>> +    dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
>> +    if (!dsi)
>> +        return ERR_PTR(-ENOMEM);
>> +
>> +    dsi->dev = dev;
>> +    dsi->plat_data = plat_data;
>> +
>> +    if (!plat_data->phy_ops->init || 
>> !plat_data->phy_ops->get_lane_mbps) {
>> +        DRM_ERROR("Phy not properly configured\n");
>> +        return ERR_PTR(-ENODEV);
>> +    }
>> +
>> +    if (!plat_data->base) {
>> +        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +        if (!res)
>> +            return ERR_PTR(-ENODEV);
>> +
>> +        dsi->base = devm_ioremap_resource(dev, res);
>> +        if (IS_ERR(dsi->base))
>> +            return ERR_PTR(-ENODEV);
>> +
>> +    } else {
>> +        dsi->base = plat_data->base;
>> +    }
>> +
>> +    dsi->pclk = devm_clk_get(dev, "pclk");
>> +    if (IS_ERR(dsi->pclk)) {
>> +        ret = PTR_ERR(dsi->pclk);
>> +        dev_err(dev, "Unable to get pclk: %d\n", ret);
>> +        return ERR_PTR(ret);
>> +    }
>> +
>> +    /*
>> +     * Note that the reset was not defined in the initial device 
>> tree, so
>> +     * we have to be prepared for it not being found.
>> +     */
>> +    apb_rst = devm_reset_control_get(dev, "apb");
>> +    if (IS_ERR(apb_rst)) {
>> +        ret = PTR_ERR(apb_rst);
>> +        if (ret == -ENOENT) {
>> +            apb_rst = NULL;
>> +        } else {
>> +            dev_err(dev, "Unable to get reset control: %d\n", ret);
>> +            return ERR_PTR(ret);
>> +        }
>> +    }
>> +
>> +    if (apb_rst) {
>> +        ret = clk_prepare_enable(dsi->pclk);
>> +        if (ret) {
>> +            dev_err(dev, "%s: Failed to enable pclk\n", __func__);
>> +            return ERR_PTR(ret);
>> +        }
>> +
>> +        reset_control_assert(apb_rst);
>> +        usleep_range(10, 20);
>> +        reset_control_deassert(apb_rst);
>> +
>> +        clk_disable_unprepare(dsi->pclk);
>> +    }
>> +
>> +    pm_runtime_enable(dev);
>> +
>> +    dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
>> +    dsi->dsi_host.dev = dev;
>> +    ret = mipi_dsi_host_register(&dsi->dsi_host);
>> +    if (ret) {
>> +        dev_err(dev, "Failed to register MIPI host: %d\n", ret);
>> +        return ERR_PTR(ret);
>> +    }
>> +
>> +    dsi->bridge.driver_private = dsi;
>> +    dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs;
>> +#ifdef CONFIG_OF
>> +    dsi->bridge.of_node = pdev->dev.of_node;
>> +#endif
>> +
>> +    dev_set_drvdata(dev, dsi);
>> +
>> +    return dsi;
>> +}
>> +
>> +static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
>> +{
>> +    pm_runtime_disable(dsi->dev);
>> +}
>> +
>> +/*
>> + * Probe/remove API, used from platforms based on the DRM bridge API.
>> + */
>> +int dw_mipi_dsi_probe(struct platform_device *pdev,
>> +              const struct dw_mipi_dsi_plat_data *plat_data)
>> +{
>> +    struct dw_mipi_dsi *dsi;
>> +
>> +    dsi = __dw_mipi_dsi_probe(pdev, plat_data);
>> +    if (IS_ERR(dsi))
>> +        return PTR_ERR(dsi);
>> +
>> +    return 0;
>> +}
>> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe);
>> +
>> +void dw_mipi_dsi_remove(struct platform_device *pdev)
>> +{
>> +    struct dw_mipi_dsi *dsi = platform_get_drvdata(pdev);
>> +
>> +    mipi_dsi_host_unregister(&dsi->dsi_host);
>> +
>> +    __dw_mipi_dsi_remove(dsi);
>> +}
>> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove);
>> +
>> +/*
>> + * Bind/unbind API, used from platforms based on the component 
>> framework.
>> + */
>> +int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder 
>> *encoder,
>> +             const struct dw_mipi_dsi_plat_data *plat_data)
>> +{
>> +    struct dw_mipi_dsi *dsi;
>> +    int ret;
>> +
>> +    dsi = __dw_mipi_dsi_probe(pdev, plat_data);
>> +    if (IS_ERR(dsi))
>> +        return PTR_ERR(dsi);
>> +
>> +    ret = drm_bridge_attach(encoder, &dsi->bridge, NULL);
>> +    if (ret) {
>> +        dw_mipi_dsi_remove(pdev);
>> +        DRM_ERROR("Failed to initialize bridge with drm\n");
>> +        return ret;
>> +    }
>> +
>> +    return 0;
>> +}
>> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
>> +
>> +void dw_mipi_dsi_unbind(struct device *dev)
>> +{
>> +    struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
>> +
>> +    __dw_mipi_dsi_remove(dsi);
>> +}
>> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
>> +
>> +MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
>> +MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
>> +MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
>> +MODULE_LICENSE("GPL");
>> +MODULE_ALIAS("platform:dw-mipi-dsi");
>> diff --git a/include/drm/bridge/dw_mipi_dsi.h 
>> b/include/drm/bridge/dw_mipi_dsi.h
>> new file mode 100644
>> index 0000000..9b30fec
>> --- /dev/null
>> +++ b/include/drm/bridge/dw_mipi_dsi.h
>> @@ -0,0 +1,39 @@
>> +/*
>> + * Copyright (C) STMicroelectronics SA 2017
>> + *
>> + * Authors: Philippe Cornu <philippe.cornu@st.com>
>> + *          Yannick Fertre <yannick.fertre@st.com>
>> + *
>> + * License terms:  GNU General Public License (GPL), version 2
>> + */
>> +
>> +#ifndef __DW_MIPI_DSI__
>> +#define __DW_MIPI_DSI__
>> +
>> +struct dw_mipi_dsi_phy_ops {
>> +    int (*init)(void *priv_data);
>> +    int (*get_lane_mbps)(void *priv_data, struct drm_display_mode *mode,
>> +                 unsigned long mode_flags, u32 lanes, u32 format,
>> +                 unsigned int *lane_mbps);
>> +};
>> +
>> +struct dw_mipi_dsi_plat_data {
>> +    void __iomem *base;
>> +    unsigned int max_data_lanes;
>> +
>> +    enum drm_mode_status (*mode_valid)(void *priv_data,
>> +                       const struct drm_display_mode *mode);
>> +
>> +    const struct dw_mipi_dsi_phy_ops *phy_ops;
>> +
>> +    void *priv_data;
>> +};
>> +
>> +int dw_mipi_dsi_probe(struct platform_device *pdev,
>> +              const struct dw_mipi_dsi_plat_data *plat_data);
>> +void dw_mipi_dsi_remove(struct platform_device *pdev);
>> +int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder 
>> *encoder,
>> +             const struct dw_mipi_dsi_plat_data *plat_data);
>> +void dw_mipi_dsi_unbind(struct device *dev);
>> +
>> +#endif /* __DW_MIPI_DSI__ */
>>
> 
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^ permalink raw reply	[flat|nested] 24+ messages in thread
* [PATCH v5 4/7] drm/bridge/synopsys: Add MIPI DSI host controller bridge
@ 2017-07-17  7:54       ` Philippe CORNU
  0 siblings, 0 replies; 24+ messages in thread
From: Philippe CORNU @ 2017-07-17  7:54 UTC (permalink / raw)
  To: linux-arm-kernel



On 07/12/2017 08:05 AM, Archit Taneja wrote:
> 
> 
> On 07/03/2017 02:11 PM, Philippe CORNU wrote:
>> Add a Synopsys Designware MIPI DSI host DRM bridge driver, based on the
>> Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
>>
> 
> The patch looks good now. One thing that needs to be updated is to make
> drm_bridge_add() not return anything.

Hi Archit and many thanks for your review.
I have just sent a v6 version adding the drm_bridge_add() small fix.

> 
> The later patches in the series would be dependent on this patch, right?
yes

> Since the ST patches go via drm-misc too, we could either push all these
> together, or I could push the bridge driver to drm-misc-next, and the ST
> patches can be pushed after. Any preference? If not, I'll do the latter.
> 
> Archit
> 
The v6 version has been tested on today drm-misc-next branch (few 
minutes ago). You can push the entire serie as it is maybe the most 
simple solution. Or you can push "up to the synopsys part" and Benjamin 
& I will push the remaining part. In fact, it is up to you, simply tell 
us your preferred approach.

Once again, many thanks,
Philippe


>> Signed-off-by: Philippe CORNU <philippe.cornu@st.com>
>> ---
>>   drivers/gpu/drm/bridge/synopsys/Kconfig       |   6 +
>>   drivers/gpu/drm/bridge/synopsys/Makefile      |   2 +
>>   drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 979 
>> ++++++++++++++++++++++++++
>>   include/drm/bridge/dw_mipi_dsi.h              |  39 +
>>   4 files changed, 1026 insertions(+)
>>   create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>>   create mode 100644 include/drm/bridge/dw_mipi_dsi.h
>>
>> diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig 
>> b/drivers/gpu/drm/bridge/synopsys/Kconfig
>> index 40d2827..f00ee26 100644
>> --- a/drivers/gpu/drm/bridge/synopsys/Kconfig
>> +++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
>> @@ -21,3 +21,9 @@ config DRM_DW_HDMI_I2S_AUDIO
>>       help
>>         Support the I2S Audio interface which is part of the Synopsys
>>         Designware HDMI block.
>> +
>> +config DRM_DW_MIPI_DSI
>> +    tristate
>> +    select DRM_KMS_HELPER
>> +    select DRM_MIPI_DSI
>> +    select DRM_PANEL_BRIDGE
>> diff --git a/drivers/gpu/drm/bridge/synopsys/Makefile 
>> b/drivers/gpu/drm/bridge/synopsys/Makefile
>> index 17aa7a6..5f57d36 100644
>> --- a/drivers/gpu/drm/bridge/synopsys/Makefile
>> +++ b/drivers/gpu/drm/bridge/synopsys/Makefile
>> @@ -3,3 +3,5 @@
>>   obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
>>   obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
>>   obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
>> +
>> +obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw-mipi-dsi.o
>> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
>> b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>> new file mode 100644
>> index 0000000..406000e
>> --- /dev/null
>> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>> @@ -0,0 +1,979 @@
>> +/*
>> + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
>> + * Copyright (C) STMicroelectronics SA 2017
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * Modified by Philippe Cornu <philippe.cornu@st.com>
>> + * This generic Synopsys DesignWare MIPI DSI host driver is based on the
>> + * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/component.h>
>> +#include <linux/iopoll.h>
>> +#include <linux/module.h>
>> +#include <linux/of_device.h>
>> +#include <linux/pm_runtime.h>
>> +#include <linux/reset.h>
>> +#include <drm/drmP.h>
>> +#include <drm/drm_atomic_helper.h>
>> +#include <drm/drm_bridge.h>
>> +#include <drm/drm_crtc.h>
>> +#include <drm/drm_crtc_helper.h>
>> +#include <drm/drm_mipi_dsi.h>
>> +#include <drm/drm_of.h>
>> +#include <drm/bridge/dw_mipi_dsi.h>
>> +#include <video/mipi_display.h>
>> +
>> +#define DSI_VERSION            0x00
>> +#define DSI_PWR_UP            0x04
>> +#define RESET                0
>> +#define POWERUP                BIT(0)
>> +
>> +#define DSI_CLKMGR_CFG            0x08
>> +#define TO_CLK_DIVIDSION(div)        (((div) & 0xff) << 8)
>> +#define TX_ESC_CLK_DIVIDSION(div)    (((div) & 0xff) << 0)
>> +
>> +#define DSI_DPI_VCID            0x0c
>> +#define DPI_VID(vid)            (((vid) & 0x3) << 0)
>> +
>> +#define DSI_DPI_COLOR_CODING        0x10
>> +#define EN18_LOOSELY            BIT(8)
>> +#define DPI_COLOR_CODING_16BIT_1    0x0
>> +#define DPI_COLOR_CODING_16BIT_2    0x1
>> +#define DPI_COLOR_CODING_16BIT_3    0x2
>> +#define DPI_COLOR_CODING_18BIT_1    0x3
>> +#define DPI_COLOR_CODING_18BIT_2    0x4
>> +#define DPI_COLOR_CODING_24BIT        0x5
>> +
>> +#define DSI_DPI_CFG_POL            0x14
>> +#define COLORM_ACTIVE_LOW        BIT(4)
>> +#define SHUTD_ACTIVE_LOW        BIT(3)
>> +#define HSYNC_ACTIVE_LOW        BIT(2)
>> +#define VSYNC_ACTIVE_LOW        BIT(1)
>> +#define DATAEN_ACTIVE_LOW        BIT(0)
>> +
>> +#define DSI_DPI_LP_CMD_TIM        0x18
>> +#define OUTVACT_LPCMD_TIME(p)        (((p) & 0xff) << 16)
>> +#define INVACT_LPCMD_TIME(p)        ((p) & 0xff)
>> +
>> +#define DSI_DBI_CFG            0x20
>> +#define DSI_DBI_CMDSIZE            0x28
>> +
>> +#define DSI_PCKHDL_CFG            0x2c
>> +#define EN_CRC_RX            BIT(4)
>> +#define EN_ECC_RX            BIT(3)
>> +#define EN_BTA                BIT(2)
>> +#define EN_EOTP_RX            BIT(1)
>> +#define EN_EOTP_TX            BIT(0)
>> +
>> +#define DSI_MODE_CFG            0x34
>> +#define ENABLE_VIDEO_MODE        0
>> +#define ENABLE_CMD_MODE            BIT(0)
>> +
>> +#define DSI_VID_MODE_CFG        0x38
>> +#define FRAME_BTA_ACK            BIT(14)
>> +#define ENABLE_LOW_POWER        (0x3f << 8)
>> +#define ENABLE_LOW_POWER_MASK        (0x3f << 8)
>> +#define VID_MODE_TYPE_NON_BURST_SYNC_PULSES    0x0
>> +#define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS    0x1
>> +#define VID_MODE_TYPE_BURST            0x2
>> +#define VID_MODE_TYPE_MASK            0x3
>> +
>> +#define DSI_VID_PKT_SIZE        0x3c
>> +#define VID_PKT_SIZE(p)            (((p) & 0x3fff) << 0)
>> +#define VID_PKT_MAX_SIZE        0x3fff
>> +
>> +#define DSI_VID_HSA_TIME        0x48
>> +#define DSI_VID_HBP_TIME        0x4c
>> +#define DSI_VID_HLINE_TIME        0x50
>> +#define DSI_VID_VSA_LINES        0x54
>> +#define DSI_VID_VBP_LINES        0x58
>> +#define DSI_VID_VFP_LINES        0x5c
>> +#define DSI_VID_VACTIVE_LINES        0x60
>> +#define DSI_CMD_MODE_CFG        0x68
>> +#define MAX_RD_PKT_SIZE_LP        BIT(24)
>> +#define DCS_LW_TX_LP            BIT(19)
>> +#define DCS_SR_0P_TX_LP            BIT(18)
>> +#define DCS_SW_1P_TX_LP            BIT(17)
>> +#define DCS_SW_0P_TX_LP            BIT(16)
>> +#define GEN_LW_TX_LP            BIT(14)
>> +#define GEN_SR_2P_TX_LP            BIT(13)
>> +#define GEN_SR_1P_TX_LP            BIT(12)
>> +#define GEN_SR_0P_TX_LP            BIT(11)
>> +#define GEN_SW_2P_TX_LP            BIT(10)
>> +#define GEN_SW_1P_TX_LP            BIT(9)
>> +#define GEN_SW_0P_TX_LP            BIT(8)
>> +#define EN_ACK_RQST            BIT(1)
>> +#define EN_TEAR_FX            BIT(0)
>> +
>> +#define CMD_MODE_ALL_LP            (MAX_RD_PKT_SIZE_LP | \
>> +                     DCS_LW_TX_LP | \
>> +                     DCS_SR_0P_TX_LP | \
>> +                     DCS_SW_1P_TX_LP | \
>> +                     DCS_SW_0P_TX_LP | \
>> +                     GEN_LW_TX_LP | \
>> +                     GEN_SR_2P_TX_LP | \
>> +                     GEN_SR_1P_TX_LP | \
>> +                     GEN_SR_0P_TX_LP | \
>> +                     GEN_SW_2P_TX_LP | \
>> +                     GEN_SW_1P_TX_LP | \
>> +                     GEN_SW_0P_TX_LP)
>> +
>> +#define DSI_GEN_HDR            0x6c
>> +#define GEN_HDATA(data)            (((data) & 0xffff) << 8)
>> +#define GEN_HDATA_MASK            (0xffff << 8)
>> +#define GEN_HTYPE(type)            (((type) & 0xff) << 0)
>> +#define GEN_HTYPE_MASK            0xff
>> +
>> +#define DSI_GEN_PLD_DATA        0x70
>> +
>> +#define DSI_CMD_PKT_STATUS        0x74
>> +#define GEN_CMD_EMPTY            BIT(0)
>> +#define GEN_CMD_FULL            BIT(1)
>> +#define GEN_PLD_W_EMPTY            BIT(2)
>> +#define GEN_PLD_W_FULL            BIT(3)
>> +#define GEN_PLD_R_EMPTY            BIT(4)
>> +#define GEN_PLD_R_FULL            BIT(5)
>> +#define GEN_RD_CMD_BUSY            BIT(6)
>> +
>> +#define DSI_TO_CNT_CFG            0x78
>> +#define HSTX_TO_CNT(p)            (((p) & 0xffff) << 16)
>> +#define LPRX_TO_CNT(p)            ((p) & 0xffff)
>> +
>> +#define DSI_BTA_TO_CNT            0x8c
>> +#define DSI_LPCLK_CTRL            0x94
>> +#define AUTO_CLKLANE_CTRL        BIT(1)
>> +#define PHY_TXREQUESTCLKHS        BIT(0)
>> +
>> +#define DSI_PHY_TMR_LPCLK_CFG        0x98
>> +#define PHY_CLKHS2LP_TIME(lbcc)        (((lbcc) & 0x3ff) << 16)
>> +#define PHY_CLKLP2HS_TIME(lbcc)        ((lbcc) & 0x3ff)
>> +
>> +#define DSI_PHY_TMR_CFG            0x9c
>> +#define PHY_HS2LP_TIME(lbcc)        (((lbcc) & 0xff) << 24)
>> +#define PHY_LP2HS_TIME(lbcc)        (((lbcc) & 0xff) << 16)
>> +#define MAX_RD_TIME(lbcc)        ((lbcc) & 0x7fff)
>> +
>> +#define DSI_PHY_RSTZ            0xa0
>> +#define PHY_DISFORCEPLL            0
>> +#define PHY_ENFORCEPLL            BIT(3)
>> +#define PHY_DISABLECLK            0
>> +#define PHY_ENABLECLK            BIT(2)
>> +#define PHY_RSTZ            0
>> +#define PHY_UNRSTZ            BIT(1)
>> +#define PHY_SHUTDOWNZ            0
>> +#define PHY_UNSHUTDOWNZ            BIT(0)
>> +
>> +#define DSI_PHY_IF_CFG            0xa4
>> +#define N_LANES(n)            ((((n) - 1) & 0x3) << 0)
>> +#define PHY_STOP_WAIT_TIME(cycle)    (((cycle) & 0xff) << 8)
>> +
>> +#define DSI_PHY_STATUS            0xb0
>> +#define LOCK                BIT(0)
>> +#define STOP_STATE_CLK_LANE        BIT(2)
>> +
>> +#define DSI_PHY_TST_CTRL0        0xb4
>> +#define PHY_TESTCLK            BIT(1)
>> +#define PHY_UNTESTCLK            0
>> +#define PHY_TESTCLR            BIT(0)
>> +#define PHY_UNTESTCLR            0
>> +
>> +#define DSI_PHY_TST_CTRL1        0xb8
>> +#define PHY_TESTEN            BIT(16)
>> +#define PHY_UNTESTEN            0
>> +#define PHY_TESTDOUT(n)            (((n) & 0xff) << 8)
>> +#define PHY_TESTDIN(n)            (((n) & 0xff) << 0)
>> +
>> +#define DSI_INT_ST0            0xbc
>> +#define DSI_INT_ST1            0xc0
>> +#define DSI_INT_MSK0            0xc4
>> +#define DSI_INT_MSK1            0xc8
>> +
>> +#define PHY_STATUS_TIMEOUT_US        10000
>> +#define CMD_PKT_STATUS_TIMEOUT_US    20000
>> +
>> +struct dw_mipi_dsi {
>> +    struct drm_bridge bridge;
>> +    struct mipi_dsi_host dsi_host;
>> +    struct drm_bridge *panel_bridge;
>> +    bool is_panel_bridge;
>> +    struct device *dev;
>> +    void __iomem *base;
>> +
>> +    struct clk *pclk;
>> +
>> +    unsigned int lane_mbps; /* per lane */
>> +    u32 channel;
>> +    u32 lanes;
>> +    u32 format;
>> +    unsigned long mode_flags;
>> +
>> +    const struct dw_mipi_dsi_plat_data *plat_data;
>> +};
>> +
>> +/*
>> + * The controller should generate 2 frames before
>> + * preparing the peripheral.
>> + */
>> +static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode 
>> *mode)
>> +{
>> +    int refresh, two_frames;
>> +
>> +    refresh = drm_mode_vrefresh(mode);
>> +    two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
>> +    msleep(two_frames);
>> +}
>> +
>> +static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host 
>> *host)
>> +{
>> +    return container_of(host, struct dw_mipi_dsi, dsi_host);
>> +}
>> +
>> +static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge 
>> *bridge)
>> +{
>> +    return container_of(bridge, struct dw_mipi_dsi, bridge);
>> +}
>> +
>> +static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
>> +{
>> +    writel(val, dsi->base + reg);
>> +}
>> +
>> +static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
>> +{
>> +    return readl(dsi->base + reg);
>> +}
>> +
>> +static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
>> +                   struct mipi_dsi_device *device)
>> +{
>> +    struct dw_mipi_dsi *dsi = host_to_dsi(host);
>> +    struct drm_bridge *bridge;
>> +    struct drm_panel *panel;
>> +    int ret;
>> +
>> +    if (device->lanes > dsi->plat_data->max_data_lanes) {
>> +        dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
>> +            device->lanes);
>> +        return -EINVAL;
>> +    }
>> +
>> +    dsi->lanes = device->lanes;
>> +    dsi->channel = device->channel;
>> +    dsi->format = device->format;
>> +    dsi->mode_flags = device->mode_flags;
>> +
>> +    ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0,
>> +                      &panel, &bridge);
>> +    if (ret)
>> +        return ret;
>> +
>> +    if (panel) {
>> +        bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DSI);
>> +        if (IS_ERR(bridge))
>> +            return PTR_ERR(bridge);
>> +        dsi->is_panel_bridge = true;
>> +    }
>> +
>> +    dsi->panel_bridge = bridge;
>> +
>> +    return drm_bridge_add(&dsi->bridge);
>> +}
>> +
>> +static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
>> +                   struct mipi_dsi_device *device)
>> +{
>> +    struct dw_mipi_dsi *dsi = host_to_dsi(host);
>> +
>> +    if (dsi->is_panel_bridge)
>> +        drm_panel_bridge_remove(dsi->panel_bridge);
>> +
>> +    drm_bridge_remove(&dsi->bridge);
>> +
>> +    return 0;
>> +}
>> +
>> +static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
>> +                   const struct mipi_dsi_msg *msg)
>> +{
>> +    bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
>> +    u32 val = 0;
>> +
>> +    if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
>> +        val |= EN_ACK_RQST;
>> +    if (lpm)
>> +        val |= CMD_MODE_ALL_LP;
>> +
>> +    dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
>> +    dsi_write(dsi, DSI_CMD_MODE_CFG, val);
>> +}
>> +
>> +static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 
>> hdr_val)
>> +{
>> +    int ret;
>> +    u32 val, mask;
>> +
>> +    ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
>> +                 val, !(val & GEN_CMD_FULL), 1000,
>> +                 CMD_PKT_STATUS_TIMEOUT_US);
>> +    if (ret < 0) {
>> +        dev_err(dsi->dev, "failed to get available command FIFO\n");
>> +        return ret;
>> +    }
>> +
>> +    dsi_write(dsi, DSI_GEN_HDR, hdr_val);
>> +
>> +    mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
>> +    ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
>> +                 val, (val & mask) == mask,
>> +                 1000, CMD_PKT_STATUS_TIMEOUT_US);
>> +    if (ret < 0) {
>> +        dev_err(dsi->dev, "failed to write command FIFO\n");
>> +        return ret;
>> +    }
>> +
>> +    return 0;
>> +}
>> +
>> +static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi *dsi,
>> +                       const struct mipi_dsi_msg *msg)
>> +{
>> +    const u8 *tx_buf = msg->tx_buf;
>> +    u16 data = 0;
>> +    u32 val;
>> +
>> +    if (msg->tx_len > 0)
>> +        data |= tx_buf[0];
>> +    if (msg->tx_len > 1)
>> +        data |= tx_buf[1] << 8;
>> +
>> +    if (msg->tx_len > 2) {
>> +        dev_err(dsi->dev, "too long tx buf length %zu for short 
>> write\n",
>> +            msg->tx_len);
>> +        return -EINVAL;
>> +    }
>> +
>> +    val = GEN_HDATA(data) | GEN_HTYPE(msg->type);
>> +    return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
>> +}
>> +
>> +static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
>> +                      const struct mipi_dsi_msg *msg)
>> +{
>> +    const u8 *tx_buf = msg->tx_buf;
>> +    int len = msg->tx_len, pld_data_bytes = sizeof(u32), ret;
>> +    u32 hdr_val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
>> +    u32 remainder;
>> +    u32 val;
>> +
>> +    if (msg->tx_len < 3) {
>> +        dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
>> +            msg->tx_len);
>> +        return -EINVAL;
>> +    }
>> +
>> +    while (DIV_ROUND_UP(len, pld_data_bytes)) {
>> +        if (len < pld_data_bytes) {
>> +            remainder = 0;
>> +            memcpy(&remainder, tx_buf, len);
>> +            dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
>> +            len = 0;
>> +        } else {
>> +            memcpy(&remainder, tx_buf, pld_data_bytes);
>> +            dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
>> +            tx_buf += pld_data_bytes;
>> +            len -= pld_data_bytes;
>> +        }
>> +
>> +        ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
>> +                     val, !(val & GEN_PLD_W_FULL), 1000,
>> +                     CMD_PKT_STATUS_TIMEOUT_US);
>> +        if (ret < 0) {
>> +            dev_err(dsi->dev,
>> +                "failed to get available write payload FIFO\n");
>> +            return ret;
>> +        }
>> +    }
>> +
>> +    return dw_mipi_dsi_gen_pkt_hdr_write(dsi, hdr_val);
>> +}
>> +
>> +static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
>> +                     const struct mipi_dsi_msg *msg)
>> +{
>> +    struct dw_mipi_dsi *dsi = host_to_dsi(host);
>> +    int ret;
>> +
>> +    /*
>> +     * TODO dw drv improvements
>> +     * use mipi_dsi_create_packet() instead of all following
>> +     * functions and code (no switch cases, no
>> +     * dw_mipi_dsi_dcs_short_write(), only the loop in long_write...)
>> +     * and use packet.header...
>> +     */
>> +    dw_mipi_message_config(dsi, msg);
>> +
>> +    switch (msg->type) {
>> +    case MIPI_DSI_DCS_SHORT_WRITE:
>> +    case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
>> +    case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
>> +        ret = dw_mipi_dsi_dcs_short_write(dsi, msg);
>> +        break;
>> +    case MIPI_DSI_DCS_LONG_WRITE:
>> +        ret = dw_mipi_dsi_dcs_long_write(dsi, msg);
>> +        break;
>> +    default:
>> +        dev_err(dsi->dev, "unsupported message type 0x%02x\n",
>> +            msg->type);
>> +        ret = -EINVAL;
>> +    }
>> +
>> +    return ret;
>> +}
>> +
>> +static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
>> +    .attach = dw_mipi_dsi_host_attach,
>> +    .detach = dw_mipi_dsi_host_detach,
>> +    .transfer = dw_mipi_dsi_host_transfer,
>> +};
>> +
>> +static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
>> +{
>> +    u32 val;
>> +
>> +    /*
>> +     * TODO dw drv improvements
>> +     * enabling low power is panel-dependent, we should use the
>> +     * panel configuration here...
>> +     */
>> +    val = ENABLE_LOW_POWER;
>> +
>> +    if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
>> +        val |= VID_MODE_TYPE_BURST;
>> +    else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
>> +        val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
>> +    else
>> +        val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
>> +
>> +    dsi_write(dsi, DSI_VID_MODE_CFG, val);
>> +}
>> +
>> +static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
>> +                 unsigned long mode_flags)
>> +{
>> +    dsi_write(dsi, DSI_PWR_UP, RESET);
>> +
>> +    if (mode_flags & MIPI_DSI_MODE_VIDEO) {
>> +        dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
>> +        dw_mipi_dsi_video_mode_config(dsi);
>> +        dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
>> +    } else {
>> +        dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
>> +    }
>> +
>> +    dsi_write(dsi, DSI_PWR_UP, POWERUP);
>> +}
>> +
>> +static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
>> +{
>> +    dsi_write(dsi, DSI_PWR_UP, RESET);
>> +    dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
>> +}
>> +
>> +static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
>> +{
>> +    /*
>> +     * The maximum permitted escape clock is 20MHz and it is derived 
>> from
>> +     * lanebyteclk, which is running at "lane_mbps / 8".  Thus we want:
>> +     *
>> +     *     (lane_mbps >> 3) / esc_clk_division < 20
>> +     * which is:
>> +     *     (lane_mbps >> 3) / 20 > esc_clk_division
>> +     */
>> +    u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
>> +
>> +    dsi_write(dsi, DSI_PWR_UP, RESET);
>> +
>> +    /*
>> +     * TODO dw drv improvements
>> +     * timeout clock division should be computed with the
>> +     * high speed transmission counter timeout and byte lane...
>> +     */
>> +    dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
>> +          TX_ESC_CLK_DIVIDSION(esc_clk_division));
>> +}
>> +
>> +static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
>> +                   struct drm_display_mode *mode)
>> +{
>> +    u32 val = 0, color = 0;
>> +
>> +    switch (dsi->format) {
>> +    case MIPI_DSI_FMT_RGB888:
>> +        color = DPI_COLOR_CODING_24BIT;
>> +        break;
>> +    case MIPI_DSI_FMT_RGB666:
>> +        color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
>> +        break;
>> +    case MIPI_DSI_FMT_RGB666_PACKED:
>> +        color = DPI_COLOR_CODING_18BIT_1;
>> +        break;
>> +    case MIPI_DSI_FMT_RGB565:
>> +        color = DPI_COLOR_CODING_16BIT_1;
>> +        break;
>> +    }
>> +
>> +    if (mode->flags & DRM_MODE_FLAG_NVSYNC)
>> +        val |= VSYNC_ACTIVE_LOW;
>> +    if (mode->flags & DRM_MODE_FLAG_NHSYNC)
>> +        val |= HSYNC_ACTIVE_LOW;
>> +
>> +    dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
>> +    dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
>> +    dsi_write(dsi, DSI_DPI_CFG_POL, val);
>> +    /*
>> +     * TODO dw drv improvements
>> +     * largest packet sizes during hfp or during vsa/vpb/vfp
>> +     * should be computed according to byte lane, lane number and only
>> +     * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
>> +     */
>> +    dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
>> +          | INVACT_LPCMD_TIME(4));
>> +}
>> +
>> +static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
>> +{
>> +    dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
>> +}
>> +
>> +static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
>> +                        struct drm_display_mode *mode)
>> +{
>> +    /*
>> +     * TODO dw drv improvements
>> +     * only burst mode is supported here. For non-burst video modes,
>> +     * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
>> +     * DSI_VNPCR.NPSIZE... especially because this driver supports
>> +     * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
>> +     */
>> +    dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
>> +}
>> +
>> +static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
>> +{
>> +    /*
>> +     * TODO dw drv improvements
>> +     * compute high speed transmission counter timeout according
>> +     * to the timeout clock division (TO_CLK_DIVIDSION) and byte lane...
>> +     */
>> +    dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | 
>> LPRX_TO_CNT(1000));
>> +    /*
>> +     * TODO dw drv improvements
>> +     * the Bus-Turn-Around Timeout Counter should be computed
>> +     * according to byte lane...
>> +     */
>> +    dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
>> +    dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
>> +}
>> +
>> +/* Get lane byte clock cycles. */
>> +static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
>> +                       struct drm_display_mode *mode,
>> +                       u32 hcomponent)
>> +{
>> +    u32 frac, lbcc;
>> +
>> +    lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
>> +
>> +    frac = lbcc % mode->clock;
>> +    lbcc = lbcc / mode->clock;
>> +    if (frac)
>> +        lbcc++;
>> +
>> +    return lbcc;
>> +}
>> +
>> +static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
>> +                      struct drm_display_mode *mode)
>> +{
>> +    u32 htotal, hsa, hbp, lbcc;
>> +
>> +    htotal = mode->htotal;
>> +    hsa = mode->hsync_end - mode->hsync_start;
>> +    hbp = mode->htotal - mode->hsync_end;
>> +
>> +    /*
>> +     * TODO dw drv improvements
>> +     * computations below may be improved...
>> +     */
>> +    lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
>> +    dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
>> +
>> +    lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
>> +    dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
>> +
>> +    lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
>> +    dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
>> +}
>> +
>> +static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
>> +                           struct drm_display_mode *mode)
>> +{
>> +    u32 vactive, vsa, vfp, vbp;
>> +
>> +    vactive = mode->vdisplay;
>> +    vsa = mode->vsync_end - mode->vsync_start;
>> +    vfp = mode->vsync_start - mode->vdisplay;
>> +    vbp = mode->vtotal - mode->vsync_end;
>> +
>> +    dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
>> +    dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
>> +    dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
>> +    dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
>> +}
>> +
>> +static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
>> +{
>> +    /*
>> +     * TODO dw drv improvements
>> +     * data & clock lane timers should be computed according to panel
>> +     * blankings and to the automatic clock lane control mode...
>> +     * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
>> +     * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
>> +     */
>> +    dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40)
>> +          | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
>> +
>> +    dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
>> +          | PHY_CLKLP2HS_TIME(0x40));
>> +}
>> +
>> +static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
>> +{
>> +    /*
>> +     * TODO dw drv improvements
>> +     * stop wait time should be the maximum between host dsi
>> +     * and panel stop wait times
>> +     */
>> +    dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
>> +          N_LANES(dsi->lanes));
>> +}
>> +
>> +static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
>> +{
>> +    /* Clear PHY state */
>> +    dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
>> +          | PHY_RSTZ | PHY_SHUTDOWNZ);
>> +    dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
>> +    dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
>> +    dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
>> +}
>> +
>> +static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
>> +{
>> +    u32 val;
>> +    int ret;
>> +
>> +    dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
>> +          PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
>> +
>> +    ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
>> +                 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
>> +    if (ret < 0)
>> +        DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
>> +
>> +    ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
>> +                 val, val & STOP_STATE_CLK_LANE, 1000,
>> +                 PHY_STATUS_TIMEOUT_US);
>> +    if (ret < 0)
>> +        DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
>> +}
>> +
>> +static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
>> +{
>> +    dsi_read(dsi, DSI_INT_ST0);
>> +    dsi_read(dsi, DSI_INT_ST1);
>> +    dsi_write(dsi, DSI_INT_MSK0, 0);
>> +    dsi_write(dsi, DSI_INT_MSK1, 0);
>> +}
>> +
>> +static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
>> +{
>> +    struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
>> +
>> +    /*
>> +     * Switch to command mode before panel-bridge post_disable &
>> +     * panel unprepare.
>> +     * Note: panel-bridge disable & panel disable has been called
>> +     * before by the drm framework.
>> +     */
>> +    dw_mipi_dsi_set_mode(dsi, 0);
>> +
>> +    /*
>> +     * TODO Only way found to call panel-bridge post_disable &
>> +     * panel unprepare before the dsi "final" disable...
>> +     * This needs to be fixed in the drm_bridge framework and the API
>> +     * needs to be updated to manage our own call chains...
>> +     */
>> +    dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge);
>> +
>> +    dw_mipi_dsi_disable(dsi);
>> +    clk_disable_unprepare(dsi->pclk);
>> +    pm_runtime_put(dsi->dev);
>> +}
>> +
>> +void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
>> +                 struct drm_display_mode *mode,
>> +                 struct drm_display_mode *adjusted_mode)
>> +{
>> +    struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
>> +    const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
>> +    void *priv_data = dsi->plat_data->priv_data;
>> +    int ret;
>> +
>> +    clk_prepare_enable(dsi->pclk);
>> +
>> +    ret = phy_ops->get_lane_mbps(priv_data, mode, dsi->mode_flags,
>> +                     dsi->lanes, dsi->format, &dsi->lane_mbps);
>> +    if (ret)
>> +        DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n");
>> +
>> +    pm_runtime_get_sync(dsi->dev);
>> +    dw_mipi_dsi_init(dsi);
>> +    dw_mipi_dsi_dpi_config(dsi, mode);
>> +    dw_mipi_dsi_packet_handler_config(dsi);
>> +    dw_mipi_dsi_video_mode_config(dsi);
>> +    dw_mipi_dsi_video_packet_config(dsi, mode);
>> +    dw_mipi_dsi_command_mode_config(dsi);
>> +    dw_mipi_dsi_line_timer_config(dsi, mode);
>> +    dw_mipi_dsi_vertical_timing_config(dsi, mode);
>> +
>> +    dw_mipi_dsi_dphy_init(dsi);
>> +    dw_mipi_dsi_dphy_timing_config(dsi);
>> +    dw_mipi_dsi_dphy_interface_config(dsi);
>> +
>> +    dw_mipi_dsi_clear_err(dsi);
>> +
>> +    ret = phy_ops->init(priv_data);
>> +    if (ret)
>> +        DRM_DEBUG_DRIVER("Phy init() failed\n");
>> +
>> +    dw_mipi_dsi_dphy_enable(dsi);
>> +
>> +    dw_mipi_dsi_wait_for_two_frames(mode);
>> +
>> +    /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
>> +    dw_mipi_dsi_set_mode(dsi, 0);
>> +}
>> +
>> +static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge)
>> +{
>> +    struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
>> +
>> +    /* Switch to video mode for panel-bridge enable & panel enable */
>> +    dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
>> +}
>> +
>> +static enum drm_mode_status
>> +dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
>> +                  const struct drm_display_mode *mode)
>> +{
>> +    struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
>> +    const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
>> +    enum drm_mode_status mode_status = MODE_OK;
>> +
>> +    if (pdata->mode_valid)
>> +        mode_status = pdata->mode_valid(pdata->priv_data, mode);
>> +
>> +    return mode_status;
>> +}
>> +
>> +static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge)
>> +{
>> +    struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
>> +
>> +    if (!bridge->encoder) {
>> +        DRM_ERROR("Parent encoder object not found\n");
>> +        return -ENODEV;
>> +    }
>> +
>> +    /* Set the encoder type as caller does not know it */
>> +    bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI;
>> +
>> +    /* Attach the panel-bridge to the dsi bridge */
>> +    return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, 
>> bridge);
>> +}
>> +
>> +static struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = {
>> +    .mode_set     = dw_mipi_dsi_bridge_mode_set,
>> +    .enable          = dw_mipi_dsi_bridge_enable,
>> +    .post_disable = dw_mipi_dsi_bridge_post_disable,
>> +    .mode_valid   = dw_mipi_dsi_bridge_mode_valid,
>> +    .attach          = dw_mipi_dsi_bridge_attach,
>> +};
>> +
>> +static struct dw_mipi_dsi *
>> +__dw_mipi_dsi_probe(struct platform_device *pdev,
>> +            const struct dw_mipi_dsi_plat_data *plat_data)
>> +{
>> +    struct device *dev = &pdev->dev;
>> +    struct reset_control *apb_rst;
>> +    struct dw_mipi_dsi *dsi;
>> +    struct resource *res;
>> +    int ret;
>> +
>> +    dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
>> +    if (!dsi)
>> +        return ERR_PTR(-ENOMEM);
>> +
>> +    dsi->dev = dev;
>> +    dsi->plat_data = plat_data;
>> +
>> +    if (!plat_data->phy_ops->init || 
>> !plat_data->phy_ops->get_lane_mbps) {
>> +        DRM_ERROR("Phy not properly configured\n");
>> +        return ERR_PTR(-ENODEV);
>> +    }
>> +
>> +    if (!plat_data->base) {
>> +        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +        if (!res)
>> +            return ERR_PTR(-ENODEV);
>> +
>> +        dsi->base = devm_ioremap_resource(dev, res);
>> +        if (IS_ERR(dsi->base))
>> +            return ERR_PTR(-ENODEV);
>> +
>> +    } else {
>> +        dsi->base = plat_data->base;
>> +    }
>> +
>> +    dsi->pclk = devm_clk_get(dev, "pclk");
>> +    if (IS_ERR(dsi->pclk)) {
>> +        ret = PTR_ERR(dsi->pclk);
>> +        dev_err(dev, "Unable to get pclk: %d\n", ret);
>> +        return ERR_PTR(ret);
>> +    }
>> +
>> +    /*
>> +     * Note that the reset was not defined in the initial device 
>> tree, so
>> +     * we have to be prepared for it not being found.
>> +     */
>> +    apb_rst = devm_reset_control_get(dev, "apb");
>> +    if (IS_ERR(apb_rst)) {
>> +        ret = PTR_ERR(apb_rst);
>> +        if (ret == -ENOENT) {
>> +            apb_rst = NULL;
>> +        } else {
>> +            dev_err(dev, "Unable to get reset control: %d\n", ret);
>> +            return ERR_PTR(ret);
>> +        }
>> +    }
>> +
>> +    if (apb_rst) {
>> +        ret = clk_prepare_enable(dsi->pclk);
>> +        if (ret) {
>> +            dev_err(dev, "%s: Failed to enable pclk\n", __func__);
>> +            return ERR_PTR(ret);
>> +        }
>> +
>> +        reset_control_assert(apb_rst);
>> +        usleep_range(10, 20);
>> +        reset_control_deassert(apb_rst);
>> +
>> +        clk_disable_unprepare(dsi->pclk);
>> +    }
>> +
>> +    pm_runtime_enable(dev);
>> +
>> +    dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
>> +    dsi->dsi_host.dev = dev;
>> +    ret = mipi_dsi_host_register(&dsi->dsi_host);
>> +    if (ret) {
>> +        dev_err(dev, "Failed to register MIPI host: %d\n", ret);
>> +        return ERR_PTR(ret);
>> +    }
>> +
>> +    dsi->bridge.driver_private = dsi;
>> +    dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs;
>> +#ifdef CONFIG_OF
>> +    dsi->bridge.of_node = pdev->dev.of_node;
>> +#endif
>> +
>> +    dev_set_drvdata(dev, dsi);
>> +
>> +    return dsi;
>> +}
>> +
>> +static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
>> +{
>> +    pm_runtime_disable(dsi->dev);
>> +}
>> +
>> +/*
>> + * Probe/remove API, used from platforms based on the DRM bridge API.
>> + */
>> +int dw_mipi_dsi_probe(struct platform_device *pdev,
>> +              const struct dw_mipi_dsi_plat_data *plat_data)
>> +{
>> +    struct dw_mipi_dsi *dsi;
>> +
>> +    dsi = __dw_mipi_dsi_probe(pdev, plat_data);
>> +    if (IS_ERR(dsi))
>> +        return PTR_ERR(dsi);
>> +
>> +    return 0;
>> +}
>> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe);
>> +
>> +void dw_mipi_dsi_remove(struct platform_device *pdev)
>> +{
>> +    struct dw_mipi_dsi *dsi = platform_get_drvdata(pdev);
>> +
>> +    mipi_dsi_host_unregister(&dsi->dsi_host);
>> +
>> +    __dw_mipi_dsi_remove(dsi);
>> +}
>> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove);
>> +
>> +/*
>> + * Bind/unbind API, used from platforms based on the component 
>> framework.
>> + */
>> +int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder 
>> *encoder,
>> +             const struct dw_mipi_dsi_plat_data *plat_data)
>> +{
>> +    struct dw_mipi_dsi *dsi;
>> +    int ret;
>> +
>> +    dsi = __dw_mipi_dsi_probe(pdev, plat_data);
>> +    if (IS_ERR(dsi))
>> +        return PTR_ERR(dsi);
>> +
>> +    ret = drm_bridge_attach(encoder, &dsi->bridge, NULL);
>> +    if (ret) {
>> +        dw_mipi_dsi_remove(pdev);
>> +        DRM_ERROR("Failed to initialize bridge with drm\n");
>> +        return ret;
>> +    }
>> +
>> +    return 0;
>> +}
>> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
>> +
>> +void dw_mipi_dsi_unbind(struct device *dev)
>> +{
>> +    struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
>> +
>> +    __dw_mipi_dsi_remove(dsi);
>> +}
>> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
>> +
>> +MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
>> +MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
>> +MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
>> +MODULE_LICENSE("GPL");
>> +MODULE_ALIAS("platform:dw-mipi-dsi");
>> diff --git a/include/drm/bridge/dw_mipi_dsi.h 
>> b/include/drm/bridge/dw_mipi_dsi.h
>> new file mode 100644
>> index 0000000..9b30fec
>> --- /dev/null
>> +++ b/include/drm/bridge/dw_mipi_dsi.h
>> @@ -0,0 +1,39 @@
>> +/*
>> + * Copyright (C) STMicroelectronics SA 2017
>> + *
>> + * Authors: Philippe Cornu <philippe.cornu@st.com>
>> + *          Yannick Fertre <yannick.fertre@st.com>
>> + *
>> + * License terms:  GNU General Public License (GPL), version 2
>> + */
>> +
>> +#ifndef __DW_MIPI_DSI__
>> +#define __DW_MIPI_DSI__
>> +
>> +struct dw_mipi_dsi_phy_ops {
>> +    int (*init)(void *priv_data);
>> +    int (*get_lane_mbps)(void *priv_data, struct drm_display_mode *mode,
>> +                 unsigned long mode_flags, u32 lanes, u32 format,
>> +                 unsigned int *lane_mbps);
>> +};
>> +
>> +struct dw_mipi_dsi_plat_data {
>> +    void __iomem *base;
>> +    unsigned int max_data_lanes;
>> +
>> +    enum drm_mode_status (*mode_valid)(void *priv_data,
>> +                       const struct drm_display_mode *mode);
>> +
>> +    const struct dw_mipi_dsi_phy_ops *phy_ops;
>> +
>> +    void *priv_data;
>> +};
>> +
>> +int dw_mipi_dsi_probe(struct platform_device *pdev,
>> +              const struct dw_mipi_dsi_plat_data *plat_data);
>> +void dw_mipi_dsi_remove(struct platform_device *pdev);
>> +int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder 
>> *encoder,
>> +             const struct dw_mipi_dsi_plat_data *plat_data);
>> +void dw_mipi_dsi_unbind(struct device *dev);
>> +
>> +#endif /* __DW_MIPI_DSI__ */
>>
> 

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v5 4/7] drm/bridge/synopsys: Add MIPI DSI host controller bridge
  2017-07-17  7:54       ` Philippe CORNU
@ 2017-07-17  8:06         ` Archit Taneja
  -1 siblings, 0 replies; 24+ messages in thread
From: Archit Taneja @ 2017-07-17  8:06 UTC (permalink / raw)
  To: Philippe CORNU, Alexandre TORGUE, Rob Herring, Arnd Bergmann,
	Eric Anholt, Andrzej Hajda
  Cc: Mark Rutland, Neil Armstrong, dri-devel, Thierry Reding,
	Chris Zhong, Mickael REULIER, Russell King, Fabien DESSENNE,
	Xinwei Kong, linux-arm-kernel, devicetree, Chen Feng,
	Vincent ABRIOU, Ludovic BARRE, Yannick FERTRE, Maxime Coquelin,
	zourongrong, Gabriel FERNANDEZ



On 07/17/2017 01:24 PM, Philippe CORNU wrote:
> 
> 
> On 07/12/2017 08:05 AM, Archit Taneja wrote:
>>
>>
>> On 07/03/2017 02:11 PM, Philippe CORNU wrote:
>>> Add a Synopsys Designware MIPI DSI host DRM bridge driver, based on the
>>> Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
>>>
>>
>> The patch looks good now. One thing that needs to be updated is to make
>> drm_bridge_add() not return anything.
> 
> Hi Archit and many thanks for your review.
> I have just sent a v6 version adding the drm_bridge_add() small fix.
> 
>>
>> The later patches in the series would be dependent on this patch, right?
> yes
> 
>> Since the ST patches go via drm-misc too, we could either push all these
>> together, or I could push the bridge driver to drm-misc-next, and the ST
>> patches can be pushed after. Any preference? If not, I'll do the latter.
>>
>> Archit
>>
> The v6 version has been tested on today drm-misc-next branch (few
> minutes ago). You can push the entire serie as it is maybe the most
> simple solution. Or you can push "up to the synopsys part" and Benjamin
> & I will push the remaining part. In fact, it is up to you, simply tell
> us your preferred approach.

Thanks. I'll push patches 1-4 after some build testing. You can push the rest
afterwards.

Thanks,
Archit

> 
> Once again, many thanks,
> Philippe
> 
> 
>>> Signed-off-by: Philippe CORNU <philippe.cornu@st.com>
>>> ---
>>>    drivers/gpu/drm/bridge/synopsys/Kconfig       |   6 +
>>>    drivers/gpu/drm/bridge/synopsys/Makefile      |   2 +
>>>    drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 979
>>> ++++++++++++++++++++++++++
>>>    include/drm/bridge/dw_mipi_dsi.h              |  39 +
>>>    4 files changed, 1026 insertions(+)
>>>    create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>>>    create mode 100644 include/drm/bridge/dw_mipi_dsi.h
>>>
>>> diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig
>>> b/drivers/gpu/drm/bridge/synopsys/Kconfig
>>> index 40d2827..f00ee26 100644
>>> --- a/drivers/gpu/drm/bridge/synopsys/Kconfig
>>> +++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
>>> @@ -21,3 +21,9 @@ config DRM_DW_HDMI_I2S_AUDIO
>>>        help
>>>          Support the I2S Audio interface which is part of the Synopsys
>>>          Designware HDMI block.
>>> +
>>> +config DRM_DW_MIPI_DSI
>>> +    tristate
>>> +    select DRM_KMS_HELPER
>>> +    select DRM_MIPI_DSI
>>> +    select DRM_PANEL_BRIDGE
>>> diff --git a/drivers/gpu/drm/bridge/synopsys/Makefile
>>> b/drivers/gpu/drm/bridge/synopsys/Makefile
>>> index 17aa7a6..5f57d36 100644
>>> --- a/drivers/gpu/drm/bridge/synopsys/Makefile
>>> +++ b/drivers/gpu/drm/bridge/synopsys/Makefile
>>> @@ -3,3 +3,5 @@
>>>    obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
>>>    obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
>>>    obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
>>> +
>>> +obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw-mipi-dsi.o
>>> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>>> b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>>> new file mode 100644
>>> index 0000000..406000e
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>>> @@ -0,0 +1,979 @@
>>> +/*
>>> + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
>>> + * Copyright (C) STMicroelectronics SA 2017
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License as published by
>>> + * the Free Software Foundation; either version 2 of the License, or
>>> + * (at your option) any later version.
>>> + *
>>> + * Modified by Philippe Cornu <philippe.cornu@st.com>
>>> + * This generic Synopsys DesignWare MIPI DSI host driver is based on the
>>> + * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
>>> + */
>>> +
>>> +#include <linux/clk.h>
>>> +#include <linux/component.h>
>>> +#include <linux/iopoll.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of_device.h>
>>> +#include <linux/pm_runtime.h>
>>> +#include <linux/reset.h>
>>> +#include <drm/drmP.h>
>>> +#include <drm/drm_atomic_helper.h>
>>> +#include <drm/drm_bridge.h>
>>> +#include <drm/drm_crtc.h>
>>> +#include <drm/drm_crtc_helper.h>
>>> +#include <drm/drm_mipi_dsi.h>
>>> +#include <drm/drm_of.h>
>>> +#include <drm/bridge/dw_mipi_dsi.h>
>>> +#include <video/mipi_display.h>
>>> +
>>> +#define DSI_VERSION            0x00
>>> +#define DSI_PWR_UP            0x04
>>> +#define RESET                0
>>> +#define POWERUP                BIT(0)
>>> +
>>> +#define DSI_CLKMGR_CFG            0x08
>>> +#define TO_CLK_DIVIDSION(div)        (((div) & 0xff) << 8)
>>> +#define TX_ESC_CLK_DIVIDSION(div)    (((div) & 0xff) << 0)
>>> +
>>> +#define DSI_DPI_VCID            0x0c
>>> +#define DPI_VID(vid)            (((vid) & 0x3) << 0)
>>> +
>>> +#define DSI_DPI_COLOR_CODING        0x10
>>> +#define EN18_LOOSELY            BIT(8)
>>> +#define DPI_COLOR_CODING_16BIT_1    0x0
>>> +#define DPI_COLOR_CODING_16BIT_2    0x1
>>> +#define DPI_COLOR_CODING_16BIT_3    0x2
>>> +#define DPI_COLOR_CODING_18BIT_1    0x3
>>> +#define DPI_COLOR_CODING_18BIT_2    0x4
>>> +#define DPI_COLOR_CODING_24BIT        0x5
>>> +
>>> +#define DSI_DPI_CFG_POL            0x14
>>> +#define COLORM_ACTIVE_LOW        BIT(4)
>>> +#define SHUTD_ACTIVE_LOW        BIT(3)
>>> +#define HSYNC_ACTIVE_LOW        BIT(2)
>>> +#define VSYNC_ACTIVE_LOW        BIT(1)
>>> +#define DATAEN_ACTIVE_LOW        BIT(0)
>>> +
>>> +#define DSI_DPI_LP_CMD_TIM        0x18
>>> +#define OUTVACT_LPCMD_TIME(p)        (((p) & 0xff) << 16)
>>> +#define INVACT_LPCMD_TIME(p)        ((p) & 0xff)
>>> +
>>> +#define DSI_DBI_CFG            0x20
>>> +#define DSI_DBI_CMDSIZE            0x28
>>> +
>>> +#define DSI_PCKHDL_CFG            0x2c
>>> +#define EN_CRC_RX            BIT(4)
>>> +#define EN_ECC_RX            BIT(3)
>>> +#define EN_BTA                BIT(2)
>>> +#define EN_EOTP_RX            BIT(1)
>>> +#define EN_EOTP_TX            BIT(0)
>>> +
>>> +#define DSI_MODE_CFG            0x34
>>> +#define ENABLE_VIDEO_MODE        0
>>> +#define ENABLE_CMD_MODE            BIT(0)
>>> +
>>> +#define DSI_VID_MODE_CFG        0x38
>>> +#define FRAME_BTA_ACK            BIT(14)
>>> +#define ENABLE_LOW_POWER        (0x3f << 8)
>>> +#define ENABLE_LOW_POWER_MASK        (0x3f << 8)
>>> +#define VID_MODE_TYPE_NON_BURST_SYNC_PULSES    0x0
>>> +#define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS    0x1
>>> +#define VID_MODE_TYPE_BURST            0x2
>>> +#define VID_MODE_TYPE_MASK            0x3
>>> +
>>> +#define DSI_VID_PKT_SIZE        0x3c
>>> +#define VID_PKT_SIZE(p)            (((p) & 0x3fff) << 0)
>>> +#define VID_PKT_MAX_SIZE        0x3fff
>>> +
>>> +#define DSI_VID_HSA_TIME        0x48
>>> +#define DSI_VID_HBP_TIME        0x4c
>>> +#define DSI_VID_HLINE_TIME        0x50
>>> +#define DSI_VID_VSA_LINES        0x54
>>> +#define DSI_VID_VBP_LINES        0x58
>>> +#define DSI_VID_VFP_LINES        0x5c
>>> +#define DSI_VID_VACTIVE_LINES        0x60
>>> +#define DSI_CMD_MODE_CFG        0x68
>>> +#define MAX_RD_PKT_SIZE_LP        BIT(24)
>>> +#define DCS_LW_TX_LP            BIT(19)
>>> +#define DCS_SR_0P_TX_LP            BIT(18)
>>> +#define DCS_SW_1P_TX_LP            BIT(17)
>>> +#define DCS_SW_0P_TX_LP            BIT(16)
>>> +#define GEN_LW_TX_LP            BIT(14)
>>> +#define GEN_SR_2P_TX_LP            BIT(13)
>>> +#define GEN_SR_1P_TX_LP            BIT(12)
>>> +#define GEN_SR_0P_TX_LP            BIT(11)
>>> +#define GEN_SW_2P_TX_LP            BIT(10)
>>> +#define GEN_SW_1P_TX_LP            BIT(9)
>>> +#define GEN_SW_0P_TX_LP            BIT(8)
>>> +#define EN_ACK_RQST            BIT(1)
>>> +#define EN_TEAR_FX            BIT(0)
>>> +
>>> +#define CMD_MODE_ALL_LP            (MAX_RD_PKT_SIZE_LP | \
>>> +                     DCS_LW_TX_LP | \
>>> +                     DCS_SR_0P_TX_LP | \
>>> +                     DCS_SW_1P_TX_LP | \
>>> +                     DCS_SW_0P_TX_LP | \
>>> +                     GEN_LW_TX_LP | \
>>> +                     GEN_SR_2P_TX_LP | \
>>> +                     GEN_SR_1P_TX_LP | \
>>> +                     GEN_SR_0P_TX_LP | \
>>> +                     GEN_SW_2P_TX_LP | \
>>> +                     GEN_SW_1P_TX_LP | \
>>> +                     GEN_SW_0P_TX_LP)
>>> +
>>> +#define DSI_GEN_HDR            0x6c
>>> +#define GEN_HDATA(data)            (((data) & 0xffff) << 8)
>>> +#define GEN_HDATA_MASK            (0xffff << 8)
>>> +#define GEN_HTYPE(type)            (((type) & 0xff) << 0)
>>> +#define GEN_HTYPE_MASK            0xff
>>> +
>>> +#define DSI_GEN_PLD_DATA        0x70
>>> +
>>> +#define DSI_CMD_PKT_STATUS        0x74
>>> +#define GEN_CMD_EMPTY            BIT(0)
>>> +#define GEN_CMD_FULL            BIT(1)
>>> +#define GEN_PLD_W_EMPTY            BIT(2)
>>> +#define GEN_PLD_W_FULL            BIT(3)
>>> +#define GEN_PLD_R_EMPTY            BIT(4)
>>> +#define GEN_PLD_R_FULL            BIT(5)
>>> +#define GEN_RD_CMD_BUSY            BIT(6)
>>> +
>>> +#define DSI_TO_CNT_CFG            0x78
>>> +#define HSTX_TO_CNT(p)            (((p) & 0xffff) << 16)
>>> +#define LPRX_TO_CNT(p)            ((p) & 0xffff)
>>> +
>>> +#define DSI_BTA_TO_CNT            0x8c
>>> +#define DSI_LPCLK_CTRL            0x94
>>> +#define AUTO_CLKLANE_CTRL        BIT(1)
>>> +#define PHY_TXREQUESTCLKHS        BIT(0)
>>> +
>>> +#define DSI_PHY_TMR_LPCLK_CFG        0x98
>>> +#define PHY_CLKHS2LP_TIME(lbcc)        (((lbcc) & 0x3ff) << 16)
>>> +#define PHY_CLKLP2HS_TIME(lbcc)        ((lbcc) & 0x3ff)
>>> +
>>> +#define DSI_PHY_TMR_CFG            0x9c
>>> +#define PHY_HS2LP_TIME(lbcc)        (((lbcc) & 0xff) << 24)
>>> +#define PHY_LP2HS_TIME(lbcc)        (((lbcc) & 0xff) << 16)
>>> +#define MAX_RD_TIME(lbcc)        ((lbcc) & 0x7fff)
>>> +
>>> +#define DSI_PHY_RSTZ            0xa0
>>> +#define PHY_DISFORCEPLL            0
>>> +#define PHY_ENFORCEPLL            BIT(3)
>>> +#define PHY_DISABLECLK            0
>>> +#define PHY_ENABLECLK            BIT(2)
>>> +#define PHY_RSTZ            0
>>> +#define PHY_UNRSTZ            BIT(1)
>>> +#define PHY_SHUTDOWNZ            0
>>> +#define PHY_UNSHUTDOWNZ            BIT(0)
>>> +
>>> +#define DSI_PHY_IF_CFG            0xa4
>>> +#define N_LANES(n)            ((((n) - 1) & 0x3) << 0)
>>> +#define PHY_STOP_WAIT_TIME(cycle)    (((cycle) & 0xff) << 8)
>>> +
>>> +#define DSI_PHY_STATUS            0xb0
>>> +#define LOCK                BIT(0)
>>> +#define STOP_STATE_CLK_LANE        BIT(2)
>>> +
>>> +#define DSI_PHY_TST_CTRL0        0xb4
>>> +#define PHY_TESTCLK            BIT(1)
>>> +#define PHY_UNTESTCLK            0
>>> +#define PHY_TESTCLR            BIT(0)
>>> +#define PHY_UNTESTCLR            0
>>> +
>>> +#define DSI_PHY_TST_CTRL1        0xb8
>>> +#define PHY_TESTEN            BIT(16)
>>> +#define PHY_UNTESTEN            0
>>> +#define PHY_TESTDOUT(n)            (((n) & 0xff) << 8)
>>> +#define PHY_TESTDIN(n)            (((n) & 0xff) << 0)
>>> +
>>> +#define DSI_INT_ST0            0xbc
>>> +#define DSI_INT_ST1            0xc0
>>> +#define DSI_INT_MSK0            0xc4
>>> +#define DSI_INT_MSK1            0xc8
>>> +
>>> +#define PHY_STATUS_TIMEOUT_US        10000
>>> +#define CMD_PKT_STATUS_TIMEOUT_US    20000
>>> +
>>> +struct dw_mipi_dsi {
>>> +    struct drm_bridge bridge;
>>> +    struct mipi_dsi_host dsi_host;
>>> +    struct drm_bridge *panel_bridge;
>>> +    bool is_panel_bridge;
>>> +    struct device *dev;
>>> +    void __iomem *base;
>>> +
>>> +    struct clk *pclk;
>>> +
>>> +    unsigned int lane_mbps; /* per lane */
>>> +    u32 channel;
>>> +    u32 lanes;
>>> +    u32 format;
>>> +    unsigned long mode_flags;
>>> +
>>> +    const struct dw_mipi_dsi_plat_data *plat_data;
>>> +};
>>> +
>>> +/*
>>> + * The controller should generate 2 frames before
>>> + * preparing the peripheral.
>>> + */
>>> +static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode
>>> *mode)
>>> +{
>>> +    int refresh, two_frames;
>>> +
>>> +    refresh = drm_mode_vrefresh(mode);
>>> +    two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
>>> +    msleep(two_frames);
>>> +}
>>> +
>>> +static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host
>>> *host)
>>> +{
>>> +    return container_of(host, struct dw_mipi_dsi, dsi_host);
>>> +}
>>> +
>>> +static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge
>>> *bridge)
>>> +{
>>> +    return container_of(bridge, struct dw_mipi_dsi, bridge);
>>> +}
>>> +
>>> +static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
>>> +{
>>> +    writel(val, dsi->base + reg);
>>> +}
>>> +
>>> +static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
>>> +{
>>> +    return readl(dsi->base + reg);
>>> +}
>>> +
>>> +static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
>>> +                   struct mipi_dsi_device *device)
>>> +{
>>> +    struct dw_mipi_dsi *dsi = host_to_dsi(host);
>>> +    struct drm_bridge *bridge;
>>> +    struct drm_panel *panel;
>>> +    int ret;
>>> +
>>> +    if (device->lanes > dsi->plat_data->max_data_lanes) {
>>> +        dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
>>> +            device->lanes);
>>> +        return -EINVAL;
>>> +    }
>>> +
>>> +    dsi->lanes = device->lanes;
>>> +    dsi->channel = device->channel;
>>> +    dsi->format = device->format;
>>> +    dsi->mode_flags = device->mode_flags;
>>> +
>>> +    ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0,
>>> +                      &panel, &bridge);
>>> +    if (ret)
>>> +        return ret;
>>> +
>>> +    if (panel) {
>>> +        bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DSI);
>>> +        if (IS_ERR(bridge))
>>> +            return PTR_ERR(bridge);
>>> +        dsi->is_panel_bridge = true;
>>> +    }
>>> +
>>> +    dsi->panel_bridge = bridge;
>>> +
>>> +    return drm_bridge_add(&dsi->bridge);
>>> +}
>>> +
>>> +static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
>>> +                   struct mipi_dsi_device *device)
>>> +{
>>> +    struct dw_mipi_dsi *dsi = host_to_dsi(host);
>>> +
>>> +    if (dsi->is_panel_bridge)
>>> +        drm_panel_bridge_remove(dsi->panel_bridge);
>>> +
>>> +    drm_bridge_remove(&dsi->bridge);
>>> +
>>> +    return 0;
>>> +}
>>> +
>>> +static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
>>> +                   const struct mipi_dsi_msg *msg)
>>> +{
>>> +    bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
>>> +    u32 val = 0;
>>> +
>>> +    if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
>>> +        val |= EN_ACK_RQST;
>>> +    if (lpm)
>>> +        val |= CMD_MODE_ALL_LP;
>>> +
>>> +    dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
>>> +    dsi_write(dsi, DSI_CMD_MODE_CFG, val);
>>> +}
>>> +
>>> +static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32
>>> hdr_val)
>>> +{
>>> +    int ret;
>>> +    u32 val, mask;
>>> +
>>> +    ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
>>> +                 val, !(val & GEN_CMD_FULL), 1000,
>>> +                 CMD_PKT_STATUS_TIMEOUT_US);
>>> +    if (ret < 0) {
>>> +        dev_err(dsi->dev, "failed to get available command FIFO\n");
>>> +        return ret;
>>> +    }
>>> +
>>> +    dsi_write(dsi, DSI_GEN_HDR, hdr_val);
>>> +
>>> +    mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
>>> +    ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
>>> +                 val, (val & mask) == mask,
>>> +                 1000, CMD_PKT_STATUS_TIMEOUT_US);
>>> +    if (ret < 0) {
>>> +        dev_err(dsi->dev, "failed to write command FIFO\n");
>>> +        return ret;
>>> +    }
>>> +
>>> +    return 0;
>>> +}
>>> +
>>> +static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi *dsi,
>>> +                       const struct mipi_dsi_msg *msg)
>>> +{
>>> +    const u8 *tx_buf = msg->tx_buf;
>>> +    u16 data = 0;
>>> +    u32 val;
>>> +
>>> +    if (msg->tx_len > 0)
>>> +        data |= tx_buf[0];
>>> +    if (msg->tx_len > 1)
>>> +        data |= tx_buf[1] << 8;
>>> +
>>> +    if (msg->tx_len > 2) {
>>> +        dev_err(dsi->dev, "too long tx buf length %zu for short
>>> write\n",
>>> +            msg->tx_len);
>>> +        return -EINVAL;
>>> +    }
>>> +
>>> +    val = GEN_HDATA(data) | GEN_HTYPE(msg->type);
>>> +    return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
>>> +}
>>> +
>>> +static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
>>> +                      const struct mipi_dsi_msg *msg)
>>> +{
>>> +    const u8 *tx_buf = msg->tx_buf;
>>> +    int len = msg->tx_len, pld_data_bytes = sizeof(u32), ret;
>>> +    u32 hdr_val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
>>> +    u32 remainder;
>>> +    u32 val;
>>> +
>>> +    if (msg->tx_len < 3) {
>>> +        dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
>>> +            msg->tx_len);
>>> +        return -EINVAL;
>>> +    }
>>> +
>>> +    while (DIV_ROUND_UP(len, pld_data_bytes)) {
>>> +        if (len < pld_data_bytes) {
>>> +            remainder = 0;
>>> +            memcpy(&remainder, tx_buf, len);
>>> +            dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
>>> +            len = 0;
>>> +        } else {
>>> +            memcpy(&remainder, tx_buf, pld_data_bytes);
>>> +            dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
>>> +            tx_buf += pld_data_bytes;
>>> +            len -= pld_data_bytes;
>>> +        }
>>> +
>>> +        ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
>>> +                     val, !(val & GEN_PLD_W_FULL), 1000,
>>> +                     CMD_PKT_STATUS_TIMEOUT_US);
>>> +        if (ret < 0) {
>>> +            dev_err(dsi->dev,
>>> +                "failed to get available write payload FIFO\n");
>>> +            return ret;
>>> +        }
>>> +    }
>>> +
>>> +    return dw_mipi_dsi_gen_pkt_hdr_write(dsi, hdr_val);
>>> +}
>>> +
>>> +static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
>>> +                     const struct mipi_dsi_msg *msg)
>>> +{
>>> +    struct dw_mipi_dsi *dsi = host_to_dsi(host);
>>> +    int ret;
>>> +
>>> +    /*
>>> +     * TODO dw drv improvements
>>> +     * use mipi_dsi_create_packet() instead of all following
>>> +     * functions and code (no switch cases, no
>>> +     * dw_mipi_dsi_dcs_short_write(), only the loop in long_write...)
>>> +     * and use packet.header...
>>> +     */
>>> +    dw_mipi_message_config(dsi, msg);
>>> +
>>> +    switch (msg->type) {
>>> +    case MIPI_DSI_DCS_SHORT_WRITE:
>>> +    case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
>>> +    case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
>>> +        ret = dw_mipi_dsi_dcs_short_write(dsi, msg);
>>> +        break;
>>> +    case MIPI_DSI_DCS_LONG_WRITE:
>>> +        ret = dw_mipi_dsi_dcs_long_write(dsi, msg);
>>> +        break;
>>> +    default:
>>> +        dev_err(dsi->dev, "unsupported message type 0x%02x\n",
>>> +            msg->type);
>>> +        ret = -EINVAL;
>>> +    }
>>> +
>>> +    return ret;
>>> +}
>>> +
>>> +static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
>>> +    .attach = dw_mipi_dsi_host_attach,
>>> +    .detach = dw_mipi_dsi_host_detach,
>>> +    .transfer = dw_mipi_dsi_host_transfer,
>>> +};
>>> +
>>> +static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
>>> +{
>>> +    u32 val;
>>> +
>>> +    /*
>>> +     * TODO dw drv improvements
>>> +     * enabling low power is panel-dependent, we should use the
>>> +     * panel configuration here...
>>> +     */
>>> +    val = ENABLE_LOW_POWER;
>>> +
>>> +    if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
>>> +        val |= VID_MODE_TYPE_BURST;
>>> +    else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
>>> +        val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
>>> +    else
>>> +        val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
>>> +
>>> +    dsi_write(dsi, DSI_VID_MODE_CFG, val);
>>> +}
>>> +
>>> +static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
>>> +                 unsigned long mode_flags)
>>> +{
>>> +    dsi_write(dsi, DSI_PWR_UP, RESET);
>>> +
>>> +    if (mode_flags & MIPI_DSI_MODE_VIDEO) {
>>> +        dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
>>> +        dw_mipi_dsi_video_mode_config(dsi);
>>> +        dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
>>> +    } else {
>>> +        dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
>>> +    }
>>> +
>>> +    dsi_write(dsi, DSI_PWR_UP, POWERUP);
>>> +}
>>> +
>>> +static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
>>> +{
>>> +    dsi_write(dsi, DSI_PWR_UP, RESET);
>>> +    dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
>>> +}
>>> +
>>> +static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
>>> +{
>>> +    /*
>>> +     * The maximum permitted escape clock is 20MHz and it is derived
>>> from
>>> +     * lanebyteclk, which is running at "lane_mbps / 8".  Thus we want:
>>> +     *
>>> +     *     (lane_mbps >> 3) / esc_clk_division < 20
>>> +     * which is:
>>> +     *     (lane_mbps >> 3) / 20 > esc_clk_division
>>> +     */
>>> +    u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
>>> +
>>> +    dsi_write(dsi, DSI_PWR_UP, RESET);
>>> +
>>> +    /*
>>> +     * TODO dw drv improvements
>>> +     * timeout clock division should be computed with the
>>> +     * high speed transmission counter timeout and byte lane...
>>> +     */
>>> +    dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
>>> +          TX_ESC_CLK_DIVIDSION(esc_clk_division));
>>> +}
>>> +
>>> +static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
>>> +                   struct drm_display_mode *mode)
>>> +{
>>> +    u32 val = 0, color = 0;
>>> +
>>> +    switch (dsi->format) {
>>> +    case MIPI_DSI_FMT_RGB888:
>>> +        color = DPI_COLOR_CODING_24BIT;
>>> +        break;
>>> +    case MIPI_DSI_FMT_RGB666:
>>> +        color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
>>> +        break;
>>> +    case MIPI_DSI_FMT_RGB666_PACKED:
>>> +        color = DPI_COLOR_CODING_18BIT_1;
>>> +        break;
>>> +    case MIPI_DSI_FMT_RGB565:
>>> +        color = DPI_COLOR_CODING_16BIT_1;
>>> +        break;
>>> +    }
>>> +
>>> +    if (mode->flags & DRM_MODE_FLAG_NVSYNC)
>>> +        val |= VSYNC_ACTIVE_LOW;
>>> +    if (mode->flags & DRM_MODE_FLAG_NHSYNC)
>>> +        val |= HSYNC_ACTIVE_LOW;
>>> +
>>> +    dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
>>> +    dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
>>> +    dsi_write(dsi, DSI_DPI_CFG_POL, val);
>>> +    /*
>>> +     * TODO dw drv improvements
>>> +     * largest packet sizes during hfp or during vsa/vpb/vfp
>>> +     * should be computed according to byte lane, lane number and only
>>> +     * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
>>> +     */
>>> +    dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
>>> +          | INVACT_LPCMD_TIME(4));
>>> +}
>>> +
>>> +static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
>>> +{
>>> +    dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
>>> +}
>>> +
>>> +static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
>>> +                        struct drm_display_mode *mode)
>>> +{
>>> +    /*
>>> +     * TODO dw drv improvements
>>> +     * only burst mode is supported here. For non-burst video modes,
>>> +     * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
>>> +     * DSI_VNPCR.NPSIZE... especially because this driver supports
>>> +     * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
>>> +     */
>>> +    dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
>>> +}
>>> +
>>> +static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
>>> +{
>>> +    /*
>>> +     * TODO dw drv improvements
>>> +     * compute high speed transmission counter timeout according
>>> +     * to the timeout clock division (TO_CLK_DIVIDSION) and byte lane...
>>> +     */
>>> +    dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) |
>>> LPRX_TO_CNT(1000));
>>> +    /*
>>> +     * TODO dw drv improvements
>>> +     * the Bus-Turn-Around Timeout Counter should be computed
>>> +     * according to byte lane...
>>> +     */
>>> +    dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
>>> +    dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
>>> +}
>>> +
>>> +/* Get lane byte clock cycles. */
>>> +static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
>>> +                       struct drm_display_mode *mode,
>>> +                       u32 hcomponent)
>>> +{
>>> +    u32 frac, lbcc;
>>> +
>>> +    lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
>>> +
>>> +    frac = lbcc % mode->clock;
>>> +    lbcc = lbcc / mode->clock;
>>> +    if (frac)
>>> +        lbcc++;
>>> +
>>> +    return lbcc;
>>> +}
>>> +
>>> +static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
>>> +                      struct drm_display_mode *mode)
>>> +{
>>> +    u32 htotal, hsa, hbp, lbcc;
>>> +
>>> +    htotal = mode->htotal;
>>> +    hsa = mode->hsync_end - mode->hsync_start;
>>> +    hbp = mode->htotal - mode->hsync_end;
>>> +
>>> +    /*
>>> +     * TODO dw drv improvements
>>> +     * computations below may be improved...
>>> +     */
>>> +    lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
>>> +    dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
>>> +
>>> +    lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
>>> +    dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
>>> +
>>> +    lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
>>> +    dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
>>> +}
>>> +
>>> +static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
>>> +                           struct drm_display_mode *mode)
>>> +{
>>> +    u32 vactive, vsa, vfp, vbp;
>>> +
>>> +    vactive = mode->vdisplay;
>>> +    vsa = mode->vsync_end - mode->vsync_start;
>>> +    vfp = mode->vsync_start - mode->vdisplay;
>>> +    vbp = mode->vtotal - mode->vsync_end;
>>> +
>>> +    dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
>>> +    dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
>>> +    dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
>>> +    dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
>>> +}
>>> +
>>> +static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
>>> +{
>>> +    /*
>>> +     * TODO dw drv improvements
>>> +     * data & clock lane timers should be computed according to panel
>>> +     * blankings and to the automatic clock lane control mode...
>>> +     * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
>>> +     * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
>>> +     */
>>> +    dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40)
>>> +          | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
>>> +
>>> +    dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
>>> +          | PHY_CLKLP2HS_TIME(0x40));
>>> +}
>>> +
>>> +static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
>>> +{
>>> +    /*
>>> +     * TODO dw drv improvements
>>> +     * stop wait time should be the maximum between host dsi
>>> +     * and panel stop wait times
>>> +     */
>>> +    dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
>>> +          N_LANES(dsi->lanes));
>>> +}
>>> +
>>> +static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
>>> +{
>>> +    /* Clear PHY state */
>>> +    dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
>>> +          | PHY_RSTZ | PHY_SHUTDOWNZ);
>>> +    dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
>>> +    dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
>>> +    dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
>>> +}
>>> +
>>> +static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
>>> +{
>>> +    u32 val;
>>> +    int ret;
>>> +
>>> +    dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
>>> +          PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
>>> +
>>> +    ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
>>> +                 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
>>> +    if (ret < 0)
>>> +        DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
>>> +
>>> +    ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
>>> +                 val, val & STOP_STATE_CLK_LANE, 1000,
>>> +                 PHY_STATUS_TIMEOUT_US);
>>> +    if (ret < 0)
>>> +        DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
>>> +}
>>> +
>>> +static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
>>> +{
>>> +    dsi_read(dsi, DSI_INT_ST0);
>>> +    dsi_read(dsi, DSI_INT_ST1);
>>> +    dsi_write(dsi, DSI_INT_MSK0, 0);
>>> +    dsi_write(dsi, DSI_INT_MSK1, 0);
>>> +}
>>> +
>>> +static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
>>> +{
>>> +    struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
>>> +
>>> +    /*
>>> +     * Switch to command mode before panel-bridge post_disable &
>>> +     * panel unprepare.
>>> +     * Note: panel-bridge disable & panel disable has been called
>>> +     * before by the drm framework.
>>> +     */
>>> +    dw_mipi_dsi_set_mode(dsi, 0);
>>> +
>>> +    /*
>>> +     * TODO Only way found to call panel-bridge post_disable &
>>> +     * panel unprepare before the dsi "final" disable...
>>> +     * This needs to be fixed in the drm_bridge framework and the API
>>> +     * needs to be updated to manage our own call chains...
>>> +     */
>>> +    dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge);
>>> +
>>> +    dw_mipi_dsi_disable(dsi);
>>> +    clk_disable_unprepare(dsi->pclk);
>>> +    pm_runtime_put(dsi->dev);
>>> +}
>>> +
>>> +void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
>>> +                 struct drm_display_mode *mode,
>>> +                 struct drm_display_mode *adjusted_mode)
>>> +{
>>> +    struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
>>> +    const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
>>> +    void *priv_data = dsi->plat_data->priv_data;
>>> +    int ret;
>>> +
>>> +    clk_prepare_enable(dsi->pclk);
>>> +
>>> +    ret = phy_ops->get_lane_mbps(priv_data, mode, dsi->mode_flags,
>>> +                     dsi->lanes, dsi->format, &dsi->lane_mbps);
>>> +    if (ret)
>>> +        DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n");
>>> +
>>> +    pm_runtime_get_sync(dsi->dev);
>>> +    dw_mipi_dsi_init(dsi);
>>> +    dw_mipi_dsi_dpi_config(dsi, mode);
>>> +    dw_mipi_dsi_packet_handler_config(dsi);
>>> +    dw_mipi_dsi_video_mode_config(dsi);
>>> +    dw_mipi_dsi_video_packet_config(dsi, mode);
>>> +    dw_mipi_dsi_command_mode_config(dsi);
>>> +    dw_mipi_dsi_line_timer_config(dsi, mode);
>>> +    dw_mipi_dsi_vertical_timing_config(dsi, mode);
>>> +
>>> +    dw_mipi_dsi_dphy_init(dsi);
>>> +    dw_mipi_dsi_dphy_timing_config(dsi);
>>> +    dw_mipi_dsi_dphy_interface_config(dsi);
>>> +
>>> +    dw_mipi_dsi_clear_err(dsi);
>>> +
>>> +    ret = phy_ops->init(priv_data);
>>> +    if (ret)
>>> +        DRM_DEBUG_DRIVER("Phy init() failed\n");
>>> +
>>> +    dw_mipi_dsi_dphy_enable(dsi);
>>> +
>>> +    dw_mipi_dsi_wait_for_two_frames(mode);
>>> +
>>> +    /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
>>> +    dw_mipi_dsi_set_mode(dsi, 0);
>>> +}
>>> +
>>> +static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge)
>>> +{
>>> +    struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
>>> +
>>> +    /* Switch to video mode for panel-bridge enable & panel enable */
>>> +    dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
>>> +}
>>> +
>>> +static enum drm_mode_status
>>> +dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
>>> +                  const struct drm_display_mode *mode)
>>> +{
>>> +    struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
>>> +    const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
>>> +    enum drm_mode_status mode_status = MODE_OK;
>>> +
>>> +    if (pdata->mode_valid)
>>> +        mode_status = pdata->mode_valid(pdata->priv_data, mode);
>>> +
>>> +    return mode_status;
>>> +}
>>> +
>>> +static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge)
>>> +{
>>> +    struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
>>> +
>>> +    if (!bridge->encoder) {
>>> +        DRM_ERROR("Parent encoder object not found\n");
>>> +        return -ENODEV;
>>> +    }
>>> +
>>> +    /* Set the encoder type as caller does not know it */
>>> +    bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI;
>>> +
>>> +    /* Attach the panel-bridge to the dsi bridge */
>>> +    return drm_bridge_attach(bridge->encoder, dsi->panel_bridge,
>>> bridge);
>>> +}
>>> +
>>> +static struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = {
>>> +    .mode_set     = dw_mipi_dsi_bridge_mode_set,
>>> +    .enable          = dw_mipi_dsi_bridge_enable,
>>> +    .post_disable = dw_mipi_dsi_bridge_post_disable,
>>> +    .mode_valid   = dw_mipi_dsi_bridge_mode_valid,
>>> +    .attach          = dw_mipi_dsi_bridge_attach,
>>> +};
>>> +
>>> +static struct dw_mipi_dsi *
>>> +__dw_mipi_dsi_probe(struct platform_device *pdev,
>>> +            const struct dw_mipi_dsi_plat_data *plat_data)
>>> +{
>>> +    struct device *dev = &pdev->dev;
>>> +    struct reset_control *apb_rst;
>>> +    struct dw_mipi_dsi *dsi;
>>> +    struct resource *res;
>>> +    int ret;
>>> +
>>> +    dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
>>> +    if (!dsi)
>>> +        return ERR_PTR(-ENOMEM);
>>> +
>>> +    dsi->dev = dev;
>>> +    dsi->plat_data = plat_data;
>>> +
>>> +    if (!plat_data->phy_ops->init ||
>>> !plat_data->phy_ops->get_lane_mbps) {
>>> +        DRM_ERROR("Phy not properly configured\n");
>>> +        return ERR_PTR(-ENODEV);
>>> +    }
>>> +
>>> +    if (!plat_data->base) {
>>> +        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> +        if (!res)
>>> +            return ERR_PTR(-ENODEV);
>>> +
>>> +        dsi->base = devm_ioremap_resource(dev, res);
>>> +        if (IS_ERR(dsi->base))
>>> +            return ERR_PTR(-ENODEV);
>>> +
>>> +    } else {
>>> +        dsi->base = plat_data->base;
>>> +    }
>>> +
>>> +    dsi->pclk = devm_clk_get(dev, "pclk");
>>> +    if (IS_ERR(dsi->pclk)) {
>>> +        ret = PTR_ERR(dsi->pclk);
>>> +        dev_err(dev, "Unable to get pclk: %d\n", ret);
>>> +        return ERR_PTR(ret);
>>> +    }
>>> +
>>> +    /*
>>> +     * Note that the reset was not defined in the initial device
>>> tree, so
>>> +     * we have to be prepared for it not being found.
>>> +     */
>>> +    apb_rst = devm_reset_control_get(dev, "apb");
>>> +    if (IS_ERR(apb_rst)) {
>>> +        ret = PTR_ERR(apb_rst);
>>> +        if (ret == -ENOENT) {
>>> +            apb_rst = NULL;
>>> +        } else {
>>> +            dev_err(dev, "Unable to get reset control: %d\n", ret);
>>> +            return ERR_PTR(ret);
>>> +        }
>>> +    }
>>> +
>>> +    if (apb_rst) {
>>> +        ret = clk_prepare_enable(dsi->pclk);
>>> +        if (ret) {
>>> +            dev_err(dev, "%s: Failed to enable pclk\n", __func__);
>>> +            return ERR_PTR(ret);
>>> +        }
>>> +
>>> +        reset_control_assert(apb_rst);
>>> +        usleep_range(10, 20);
>>> +        reset_control_deassert(apb_rst);
>>> +
>>> +        clk_disable_unprepare(dsi->pclk);
>>> +    }
>>> +
>>> +    pm_runtime_enable(dev);
>>> +
>>> +    dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
>>> +    dsi->dsi_host.dev = dev;
>>> +    ret = mipi_dsi_host_register(&dsi->dsi_host);
>>> +    if (ret) {
>>> +        dev_err(dev, "Failed to register MIPI host: %d\n", ret);
>>> +        return ERR_PTR(ret);
>>> +    }
>>> +
>>> +    dsi->bridge.driver_private = dsi;
>>> +    dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs;
>>> +#ifdef CONFIG_OF
>>> +    dsi->bridge.of_node = pdev->dev.of_node;
>>> +#endif
>>> +
>>> +    dev_set_drvdata(dev, dsi);
>>> +
>>> +    return dsi;
>>> +}
>>> +
>>> +static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
>>> +{
>>> +    pm_runtime_disable(dsi->dev);
>>> +}
>>> +
>>> +/*
>>> + * Probe/remove API, used from platforms based on the DRM bridge API.
>>> + */
>>> +int dw_mipi_dsi_probe(struct platform_device *pdev,
>>> +              const struct dw_mipi_dsi_plat_data *plat_data)
>>> +{
>>> +    struct dw_mipi_dsi *dsi;
>>> +
>>> +    dsi = __dw_mipi_dsi_probe(pdev, plat_data);
>>> +    if (IS_ERR(dsi))
>>> +        return PTR_ERR(dsi);
>>> +
>>> +    return 0;
>>> +}
>>> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe);
>>> +
>>> +void dw_mipi_dsi_remove(struct platform_device *pdev)
>>> +{
>>> +    struct dw_mipi_dsi *dsi = platform_get_drvdata(pdev);
>>> +
>>> +    mipi_dsi_host_unregister(&dsi->dsi_host);
>>> +
>>> +    __dw_mipi_dsi_remove(dsi);
>>> +}
>>> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove);
>>> +
>>> +/*
>>> + * Bind/unbind API, used from platforms based on the component
>>> framework.
>>> + */
>>> +int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder
>>> *encoder,
>>> +             const struct dw_mipi_dsi_plat_data *plat_data)
>>> +{
>>> +    struct dw_mipi_dsi *dsi;
>>> +    int ret;
>>> +
>>> +    dsi = __dw_mipi_dsi_probe(pdev, plat_data);
>>> +    if (IS_ERR(dsi))
>>> +        return PTR_ERR(dsi);
>>> +
>>> +    ret = drm_bridge_attach(encoder, &dsi->bridge, NULL);
>>> +    if (ret) {
>>> +        dw_mipi_dsi_remove(pdev);
>>> +        DRM_ERROR("Failed to initialize bridge with drm\n");
>>> +        return ret;
>>> +    }
>>> +
>>> +    return 0;
>>> +}
>>> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
>>> +
>>> +void dw_mipi_dsi_unbind(struct device *dev)
>>> +{
>>> +    struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
>>> +
>>> +    __dw_mipi_dsi_remove(dsi);
>>> +}
>>> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
>>> +
>>> +MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
>>> +MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
>>> +MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
>>> +MODULE_LICENSE("GPL");
>>> +MODULE_ALIAS("platform:dw-mipi-dsi");
>>> diff --git a/include/drm/bridge/dw_mipi_dsi.h
>>> b/include/drm/bridge/dw_mipi_dsi.h
>>> new file mode 100644
>>> index 0000000..9b30fec
>>> --- /dev/null
>>> +++ b/include/drm/bridge/dw_mipi_dsi.h
>>> @@ -0,0 +1,39 @@
>>> +/*
>>> + * Copyright (C) STMicroelectronics SA 2017
>>> + *
>>> + * Authors: Philippe Cornu <philippe.cornu@st.com>
>>> + *          Yannick Fertre <yannick.fertre@st.com>
>>> + *
>>> + * License terms:  GNU General Public License (GPL), version 2
>>> + */
>>> +
>>> +#ifndef __DW_MIPI_DSI__
>>> +#define __DW_MIPI_DSI__
>>> +
>>> +struct dw_mipi_dsi_phy_ops {
>>> +    int (*init)(void *priv_data);
>>> +    int (*get_lane_mbps)(void *priv_data, struct drm_display_mode *mode,
>>> +                 unsigned long mode_flags, u32 lanes, u32 format,
>>> +                 unsigned int *lane_mbps);
>>> +};
>>> +
>>> +struct dw_mipi_dsi_plat_data {
>>> +    void __iomem *base;
>>> +    unsigned int max_data_lanes;
>>> +
>>> +    enum drm_mode_status (*mode_valid)(void *priv_data,
>>> +                       const struct drm_display_mode *mode);
>>> +
>>> +    const struct dw_mipi_dsi_phy_ops *phy_ops;
>>> +
>>> +    void *priv_data;
>>> +};
>>> +
>>> +int dw_mipi_dsi_probe(struct platform_device *pdev,
>>> +              const struct dw_mipi_dsi_plat_data *plat_data);
>>> +void dw_mipi_dsi_remove(struct platform_device *pdev);
>>> +int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder
>>> *encoder,
>>> +             const struct dw_mipi_dsi_plat_data *plat_data);
>>> +void dw_mipi_dsi_unbind(struct device *dev);
>>> +
>>> +#endif /* __DW_MIPI_DSI__ */
>>>

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
_______________________________________________
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^ permalink raw reply	[flat|nested] 24+ messages in thread
* [PATCH v5 4/7] drm/bridge/synopsys: Add MIPI DSI host controller bridge
@ 2017-07-17  8:06         ` Archit Taneja
  0 siblings, 0 replies; 24+ messages in thread
From: Archit Taneja @ 2017-07-17  8:06 UTC (permalink / raw)
  To: linux-arm-kernel



On 07/17/2017 01:24 PM, Philippe CORNU wrote:
> 
> 
> On 07/12/2017 08:05 AM, Archit Taneja wrote:
>>
>>
>> On 07/03/2017 02:11 PM, Philippe CORNU wrote:
>>> Add a Synopsys Designware MIPI DSI host DRM bridge driver, based on the
>>> Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
>>>
>>
>> The patch looks good now. One thing that needs to be updated is to make
>> drm_bridge_add() not return anything.
> 
> Hi Archit and many thanks for your review.
> I have just sent a v6 version adding the drm_bridge_add() small fix.
> 
>>
>> The later patches in the series would be dependent on this patch, right?
> yes
> 
>> Since the ST patches go via drm-misc too, we could either push all these
>> together, or I could push the bridge driver to drm-misc-next, and the ST
>> patches can be pushed after. Any preference? If not, I'll do the latter.
>>
>> Archit
>>
> The v6 version has been tested on today drm-misc-next branch (few
> minutes ago). You can push the entire serie as it is maybe the most
> simple solution. Or you can push "up to the synopsys part" and Benjamin
> & I will push the remaining part. In fact, it is up to you, simply tell
> us your preferred approach.

Thanks. I'll push patches 1-4 after some build testing. You can push the rest
afterwards.

Thanks,
Archit

> 
> Once again, many thanks,
> Philippe
> 
> 
>>> Signed-off-by: Philippe CORNU <philippe.cornu@st.com>
>>> ---
>>>    drivers/gpu/drm/bridge/synopsys/Kconfig       |   6 +
>>>    drivers/gpu/drm/bridge/synopsys/Makefile      |   2 +
>>>    drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 979
>>> ++++++++++++++++++++++++++
>>>    include/drm/bridge/dw_mipi_dsi.h              |  39 +
>>>    4 files changed, 1026 insertions(+)
>>>    create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>>>    create mode 100644 include/drm/bridge/dw_mipi_dsi.h
>>>
>>> diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig
>>> b/drivers/gpu/drm/bridge/synopsys/Kconfig
>>> index 40d2827..f00ee26 100644
>>> --- a/drivers/gpu/drm/bridge/synopsys/Kconfig
>>> +++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
>>> @@ -21,3 +21,9 @@ config DRM_DW_HDMI_I2S_AUDIO
>>>        help
>>>          Support the I2S Audio interface which is part of the Synopsys
>>>          Designware HDMI block.
>>> +
>>> +config DRM_DW_MIPI_DSI
>>> +    tristate
>>> +    select DRM_KMS_HELPER
>>> +    select DRM_MIPI_DSI
>>> +    select DRM_PANEL_BRIDGE
>>> diff --git a/drivers/gpu/drm/bridge/synopsys/Makefile
>>> b/drivers/gpu/drm/bridge/synopsys/Makefile
>>> index 17aa7a6..5f57d36 100644
>>> --- a/drivers/gpu/drm/bridge/synopsys/Makefile
>>> +++ b/drivers/gpu/drm/bridge/synopsys/Makefile
>>> @@ -3,3 +3,5 @@
>>>    obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
>>>    obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
>>>    obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
>>> +
>>> +obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw-mipi-dsi.o
>>> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>>> b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>>> new file mode 100644
>>> index 0000000..406000e
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>>> @@ -0,0 +1,979 @@
>>> +/*
>>> + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
>>> + * Copyright (C) STMicroelectronics SA 2017
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License as published by
>>> + * the Free Software Foundation; either version 2 of the License, or
>>> + * (at your option) any later version.
>>> + *
>>> + * Modified by Philippe Cornu <philippe.cornu@st.com>
>>> + * This generic Synopsys DesignWare MIPI DSI host driver is based on the
>>> + * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
>>> + */
>>> +
>>> +#include <linux/clk.h>
>>> +#include <linux/component.h>
>>> +#include <linux/iopoll.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of_device.h>
>>> +#include <linux/pm_runtime.h>
>>> +#include <linux/reset.h>
>>> +#include <drm/drmP.h>
>>> +#include <drm/drm_atomic_helper.h>
>>> +#include <drm/drm_bridge.h>
>>> +#include <drm/drm_crtc.h>
>>> +#include <drm/drm_crtc_helper.h>
>>> +#include <drm/drm_mipi_dsi.h>
>>> +#include <drm/drm_of.h>
>>> +#include <drm/bridge/dw_mipi_dsi.h>
>>> +#include <video/mipi_display.h>
>>> +
>>> +#define DSI_VERSION            0x00
>>> +#define DSI_PWR_UP            0x04
>>> +#define RESET                0
>>> +#define POWERUP                BIT(0)
>>> +
>>> +#define DSI_CLKMGR_CFG            0x08
>>> +#define TO_CLK_DIVIDSION(div)        (((div) & 0xff) << 8)
>>> +#define TX_ESC_CLK_DIVIDSION(div)    (((div) & 0xff) << 0)
>>> +
>>> +#define DSI_DPI_VCID            0x0c
>>> +#define DPI_VID(vid)            (((vid) & 0x3) << 0)
>>> +
>>> +#define DSI_DPI_COLOR_CODING        0x10
>>> +#define EN18_LOOSELY            BIT(8)
>>> +#define DPI_COLOR_CODING_16BIT_1    0x0
>>> +#define DPI_COLOR_CODING_16BIT_2    0x1
>>> +#define DPI_COLOR_CODING_16BIT_3    0x2
>>> +#define DPI_COLOR_CODING_18BIT_1    0x3
>>> +#define DPI_COLOR_CODING_18BIT_2    0x4
>>> +#define DPI_COLOR_CODING_24BIT        0x5
>>> +
>>> +#define DSI_DPI_CFG_POL            0x14
>>> +#define COLORM_ACTIVE_LOW        BIT(4)
>>> +#define SHUTD_ACTIVE_LOW        BIT(3)
>>> +#define HSYNC_ACTIVE_LOW        BIT(2)
>>> +#define VSYNC_ACTIVE_LOW        BIT(1)
>>> +#define DATAEN_ACTIVE_LOW        BIT(0)
>>> +
>>> +#define DSI_DPI_LP_CMD_TIM        0x18
>>> +#define OUTVACT_LPCMD_TIME(p)        (((p) & 0xff) << 16)
>>> +#define INVACT_LPCMD_TIME(p)        ((p) & 0xff)
>>> +
>>> +#define DSI_DBI_CFG            0x20
>>> +#define DSI_DBI_CMDSIZE            0x28
>>> +
>>> +#define DSI_PCKHDL_CFG            0x2c
>>> +#define EN_CRC_RX            BIT(4)
>>> +#define EN_ECC_RX            BIT(3)
>>> +#define EN_BTA                BIT(2)
>>> +#define EN_EOTP_RX            BIT(1)
>>> +#define EN_EOTP_TX            BIT(0)
>>> +
>>> +#define DSI_MODE_CFG            0x34
>>> +#define ENABLE_VIDEO_MODE        0
>>> +#define ENABLE_CMD_MODE            BIT(0)
>>> +
>>> +#define DSI_VID_MODE_CFG        0x38
>>> +#define FRAME_BTA_ACK            BIT(14)
>>> +#define ENABLE_LOW_POWER        (0x3f << 8)
>>> +#define ENABLE_LOW_POWER_MASK        (0x3f << 8)
>>> +#define VID_MODE_TYPE_NON_BURST_SYNC_PULSES    0x0
>>> +#define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS    0x1
>>> +#define VID_MODE_TYPE_BURST            0x2
>>> +#define VID_MODE_TYPE_MASK            0x3
>>> +
>>> +#define DSI_VID_PKT_SIZE        0x3c
>>> +#define VID_PKT_SIZE(p)            (((p) & 0x3fff) << 0)
>>> +#define VID_PKT_MAX_SIZE        0x3fff
>>> +
>>> +#define DSI_VID_HSA_TIME        0x48
>>> +#define DSI_VID_HBP_TIME        0x4c
>>> +#define DSI_VID_HLINE_TIME        0x50
>>> +#define DSI_VID_VSA_LINES        0x54
>>> +#define DSI_VID_VBP_LINES        0x58
>>> +#define DSI_VID_VFP_LINES        0x5c
>>> +#define DSI_VID_VACTIVE_LINES        0x60
>>> +#define DSI_CMD_MODE_CFG        0x68
>>> +#define MAX_RD_PKT_SIZE_LP        BIT(24)
>>> +#define DCS_LW_TX_LP            BIT(19)
>>> +#define DCS_SR_0P_TX_LP            BIT(18)
>>> +#define DCS_SW_1P_TX_LP            BIT(17)
>>> +#define DCS_SW_0P_TX_LP            BIT(16)
>>> +#define GEN_LW_TX_LP            BIT(14)
>>> +#define GEN_SR_2P_TX_LP            BIT(13)
>>> +#define GEN_SR_1P_TX_LP            BIT(12)
>>> +#define GEN_SR_0P_TX_LP            BIT(11)
>>> +#define GEN_SW_2P_TX_LP            BIT(10)
>>> +#define GEN_SW_1P_TX_LP            BIT(9)
>>> +#define GEN_SW_0P_TX_LP            BIT(8)
>>> +#define EN_ACK_RQST            BIT(1)
>>> +#define EN_TEAR_FX            BIT(0)
>>> +
>>> +#define CMD_MODE_ALL_LP            (MAX_RD_PKT_SIZE_LP | \
>>> +                     DCS_LW_TX_LP | \
>>> +                     DCS_SR_0P_TX_LP | \
>>> +                     DCS_SW_1P_TX_LP | \
>>> +                     DCS_SW_0P_TX_LP | \
>>> +                     GEN_LW_TX_LP | \
>>> +                     GEN_SR_2P_TX_LP | \
>>> +                     GEN_SR_1P_TX_LP | \
>>> +                     GEN_SR_0P_TX_LP | \
>>> +                     GEN_SW_2P_TX_LP | \
>>> +                     GEN_SW_1P_TX_LP | \
>>> +                     GEN_SW_0P_TX_LP)
>>> +
>>> +#define DSI_GEN_HDR            0x6c
>>> +#define GEN_HDATA(data)            (((data) & 0xffff) << 8)
>>> +#define GEN_HDATA_MASK            (0xffff << 8)
>>> +#define GEN_HTYPE(type)            (((type) & 0xff) << 0)
>>> +#define GEN_HTYPE_MASK            0xff
>>> +
>>> +#define DSI_GEN_PLD_DATA        0x70
>>> +
>>> +#define DSI_CMD_PKT_STATUS        0x74
>>> +#define GEN_CMD_EMPTY            BIT(0)
>>> +#define GEN_CMD_FULL            BIT(1)
>>> +#define GEN_PLD_W_EMPTY            BIT(2)
>>> +#define GEN_PLD_W_FULL            BIT(3)
>>> +#define GEN_PLD_R_EMPTY            BIT(4)
>>> +#define GEN_PLD_R_FULL            BIT(5)
>>> +#define GEN_RD_CMD_BUSY            BIT(6)
>>> +
>>> +#define DSI_TO_CNT_CFG            0x78
>>> +#define HSTX_TO_CNT(p)            (((p) & 0xffff) << 16)
>>> +#define LPRX_TO_CNT(p)            ((p) & 0xffff)
>>> +
>>> +#define DSI_BTA_TO_CNT            0x8c
>>> +#define DSI_LPCLK_CTRL            0x94
>>> +#define AUTO_CLKLANE_CTRL        BIT(1)
>>> +#define PHY_TXREQUESTCLKHS        BIT(0)
>>> +
>>> +#define DSI_PHY_TMR_LPCLK_CFG        0x98
>>> +#define PHY_CLKHS2LP_TIME(lbcc)        (((lbcc) & 0x3ff) << 16)
>>> +#define PHY_CLKLP2HS_TIME(lbcc)        ((lbcc) & 0x3ff)
>>> +
>>> +#define DSI_PHY_TMR_CFG            0x9c
>>> +#define PHY_HS2LP_TIME(lbcc)        (((lbcc) & 0xff) << 24)
>>> +#define PHY_LP2HS_TIME(lbcc)        (((lbcc) & 0xff) << 16)
>>> +#define MAX_RD_TIME(lbcc)        ((lbcc) & 0x7fff)
>>> +
>>> +#define DSI_PHY_RSTZ            0xa0
>>> +#define PHY_DISFORCEPLL            0
>>> +#define PHY_ENFORCEPLL            BIT(3)
>>> +#define PHY_DISABLECLK            0
>>> +#define PHY_ENABLECLK            BIT(2)
>>> +#define PHY_RSTZ            0
>>> +#define PHY_UNRSTZ            BIT(1)
>>> +#define PHY_SHUTDOWNZ            0
>>> +#define PHY_UNSHUTDOWNZ            BIT(0)
>>> +
>>> +#define DSI_PHY_IF_CFG            0xa4
>>> +#define N_LANES(n)            ((((n) - 1) & 0x3) << 0)
>>> +#define PHY_STOP_WAIT_TIME(cycle)    (((cycle) & 0xff) << 8)
>>> +
>>> +#define DSI_PHY_STATUS            0xb0
>>> +#define LOCK                BIT(0)
>>> +#define STOP_STATE_CLK_LANE        BIT(2)
>>> +
>>> +#define DSI_PHY_TST_CTRL0        0xb4
>>> +#define PHY_TESTCLK            BIT(1)
>>> +#define PHY_UNTESTCLK            0
>>> +#define PHY_TESTCLR            BIT(0)
>>> +#define PHY_UNTESTCLR            0
>>> +
>>> +#define DSI_PHY_TST_CTRL1        0xb8
>>> +#define PHY_TESTEN            BIT(16)
>>> +#define PHY_UNTESTEN            0
>>> +#define PHY_TESTDOUT(n)            (((n) & 0xff) << 8)
>>> +#define PHY_TESTDIN(n)            (((n) & 0xff) << 0)
>>> +
>>> +#define DSI_INT_ST0            0xbc
>>> +#define DSI_INT_ST1            0xc0
>>> +#define DSI_INT_MSK0            0xc4
>>> +#define DSI_INT_MSK1            0xc8
>>> +
>>> +#define PHY_STATUS_TIMEOUT_US        10000
>>> +#define CMD_PKT_STATUS_TIMEOUT_US    20000
>>> +
>>> +struct dw_mipi_dsi {
>>> +    struct drm_bridge bridge;
>>> +    struct mipi_dsi_host dsi_host;
>>> +    struct drm_bridge *panel_bridge;
>>> +    bool is_panel_bridge;
>>> +    struct device *dev;
>>> +    void __iomem *base;
>>> +
>>> +    struct clk *pclk;
>>> +
>>> +    unsigned int lane_mbps; /* per lane */
>>> +    u32 channel;
>>> +    u32 lanes;
>>> +    u32 format;
>>> +    unsigned long mode_flags;
>>> +
>>> +    const struct dw_mipi_dsi_plat_data *plat_data;
>>> +};
>>> +
>>> +/*
>>> + * The controller should generate 2 frames before
>>> + * preparing the peripheral.
>>> + */
>>> +static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode
>>> *mode)
>>> +{
>>> +    int refresh, two_frames;
>>> +
>>> +    refresh = drm_mode_vrefresh(mode);
>>> +    two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
>>> +    msleep(two_frames);
>>> +}
>>> +
>>> +static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host
>>> *host)
>>> +{
>>> +    return container_of(host, struct dw_mipi_dsi, dsi_host);
>>> +}
>>> +
>>> +static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge
>>> *bridge)
>>> +{
>>> +    return container_of(bridge, struct dw_mipi_dsi, bridge);
>>> +}
>>> +
>>> +static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
>>> +{
>>> +    writel(val, dsi->base + reg);
>>> +}
>>> +
>>> +static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
>>> +{
>>> +    return readl(dsi->base + reg);
>>> +}
>>> +
>>> +static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
>>> +                   struct mipi_dsi_device *device)
>>> +{
>>> +    struct dw_mipi_dsi *dsi = host_to_dsi(host);
>>> +    struct drm_bridge *bridge;
>>> +    struct drm_panel *panel;
>>> +    int ret;
>>> +
>>> +    if (device->lanes > dsi->plat_data->max_data_lanes) {
>>> +        dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
>>> +            device->lanes);
>>> +        return -EINVAL;
>>> +    }
>>> +
>>> +    dsi->lanes = device->lanes;
>>> +    dsi->channel = device->channel;
>>> +    dsi->format = device->format;
>>> +    dsi->mode_flags = device->mode_flags;
>>> +
>>> +    ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0,
>>> +                      &panel, &bridge);
>>> +    if (ret)
>>> +        return ret;
>>> +
>>> +    if (panel) {
>>> +        bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DSI);
>>> +        if (IS_ERR(bridge))
>>> +            return PTR_ERR(bridge);
>>> +        dsi->is_panel_bridge = true;
>>> +    }
>>> +
>>> +    dsi->panel_bridge = bridge;
>>> +
>>> +    return drm_bridge_add(&dsi->bridge);
>>> +}
>>> +
>>> +static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
>>> +                   struct mipi_dsi_device *device)
>>> +{
>>> +    struct dw_mipi_dsi *dsi = host_to_dsi(host);
>>> +
>>> +    if (dsi->is_panel_bridge)
>>> +        drm_panel_bridge_remove(dsi->panel_bridge);
>>> +
>>> +    drm_bridge_remove(&dsi->bridge);
>>> +
>>> +    return 0;
>>> +}
>>> +
>>> +static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
>>> +                   const struct mipi_dsi_msg *msg)
>>> +{
>>> +    bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
>>> +    u32 val = 0;
>>> +
>>> +    if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
>>> +        val |= EN_ACK_RQST;
>>> +    if (lpm)
>>> +        val |= CMD_MODE_ALL_LP;
>>> +
>>> +    dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
>>> +    dsi_write(dsi, DSI_CMD_MODE_CFG, val);
>>> +}
>>> +
>>> +static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32
>>> hdr_val)
>>> +{
>>> +    int ret;
>>> +    u32 val, mask;
>>> +
>>> +    ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
>>> +                 val, !(val & GEN_CMD_FULL), 1000,
>>> +                 CMD_PKT_STATUS_TIMEOUT_US);
>>> +    if (ret < 0) {
>>> +        dev_err(dsi->dev, "failed to get available command FIFO\n");
>>> +        return ret;
>>> +    }
>>> +
>>> +    dsi_write(dsi, DSI_GEN_HDR, hdr_val);
>>> +
>>> +    mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
>>> +    ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
>>> +                 val, (val & mask) == mask,
>>> +                 1000, CMD_PKT_STATUS_TIMEOUT_US);
>>> +    if (ret < 0) {
>>> +        dev_err(dsi->dev, "failed to write command FIFO\n");
>>> +        return ret;
>>> +    }
>>> +
>>> +    return 0;
>>> +}
>>> +
>>> +static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi *dsi,
>>> +                       const struct mipi_dsi_msg *msg)
>>> +{
>>> +    const u8 *tx_buf = msg->tx_buf;
>>> +    u16 data = 0;
>>> +    u32 val;
>>> +
>>> +    if (msg->tx_len > 0)
>>> +        data |= tx_buf[0];
>>> +    if (msg->tx_len > 1)
>>> +        data |= tx_buf[1] << 8;
>>> +
>>> +    if (msg->tx_len > 2) {
>>> +        dev_err(dsi->dev, "too long tx buf length %zu for short
>>> write\n",
>>> +            msg->tx_len);
>>> +        return -EINVAL;
>>> +    }
>>> +
>>> +    val = GEN_HDATA(data) | GEN_HTYPE(msg->type);
>>> +    return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
>>> +}
>>> +
>>> +static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
>>> +                      const struct mipi_dsi_msg *msg)
>>> +{
>>> +    const u8 *tx_buf = msg->tx_buf;
>>> +    int len = msg->tx_len, pld_data_bytes = sizeof(u32), ret;
>>> +    u32 hdr_val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
>>> +    u32 remainder;
>>> +    u32 val;
>>> +
>>> +    if (msg->tx_len < 3) {
>>> +        dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
>>> +            msg->tx_len);
>>> +        return -EINVAL;
>>> +    }
>>> +
>>> +    while (DIV_ROUND_UP(len, pld_data_bytes)) {
>>> +        if (len < pld_data_bytes) {
>>> +            remainder = 0;
>>> +            memcpy(&remainder, tx_buf, len);
>>> +            dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
>>> +            len = 0;
>>> +        } else {
>>> +            memcpy(&remainder, tx_buf, pld_data_bytes);
>>> +            dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
>>> +            tx_buf += pld_data_bytes;
>>> +            len -= pld_data_bytes;
>>> +        }
>>> +
>>> +        ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
>>> +                     val, !(val & GEN_PLD_W_FULL), 1000,
>>> +                     CMD_PKT_STATUS_TIMEOUT_US);
>>> +        if (ret < 0) {
>>> +            dev_err(dsi->dev,
>>> +                "failed to get available write payload FIFO\n");
>>> +            return ret;
>>> +        }
>>> +    }
>>> +
>>> +    return dw_mipi_dsi_gen_pkt_hdr_write(dsi, hdr_val);
>>> +}
>>> +
>>> +static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
>>> +                     const struct mipi_dsi_msg *msg)
>>> +{
>>> +    struct dw_mipi_dsi *dsi = host_to_dsi(host);
>>> +    int ret;
>>> +
>>> +    /*
>>> +     * TODO dw drv improvements
>>> +     * use mipi_dsi_create_packet() instead of all following
>>> +     * functions and code (no switch cases, no
>>> +     * dw_mipi_dsi_dcs_short_write(), only the loop in long_write...)
>>> +     * and use packet.header...
>>> +     */
>>> +    dw_mipi_message_config(dsi, msg);
>>> +
>>> +    switch (msg->type) {
>>> +    case MIPI_DSI_DCS_SHORT_WRITE:
>>> +    case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
>>> +    case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
>>> +        ret = dw_mipi_dsi_dcs_short_write(dsi, msg);
>>> +        break;
>>> +    case MIPI_DSI_DCS_LONG_WRITE:
>>> +        ret = dw_mipi_dsi_dcs_long_write(dsi, msg);
>>> +        break;
>>> +    default:
>>> +        dev_err(dsi->dev, "unsupported message type 0x%02x\n",
>>> +            msg->type);
>>> +        ret = -EINVAL;
>>> +    }
>>> +
>>> +    return ret;
>>> +}
>>> +
>>> +static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
>>> +    .attach = dw_mipi_dsi_host_attach,
>>> +    .detach = dw_mipi_dsi_host_detach,
>>> +    .transfer = dw_mipi_dsi_host_transfer,
>>> +};
>>> +
>>> +static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
>>> +{
>>> +    u32 val;
>>> +
>>> +    /*
>>> +     * TODO dw drv improvements
>>> +     * enabling low power is panel-dependent, we should use the
>>> +     * panel configuration here...
>>> +     */
>>> +    val = ENABLE_LOW_POWER;
>>> +
>>> +    if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
>>> +        val |= VID_MODE_TYPE_BURST;
>>> +    else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
>>> +        val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
>>> +    else
>>> +        val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
>>> +
>>> +    dsi_write(dsi, DSI_VID_MODE_CFG, val);
>>> +}
>>> +
>>> +static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
>>> +                 unsigned long mode_flags)
>>> +{
>>> +    dsi_write(dsi, DSI_PWR_UP, RESET);
>>> +
>>> +    if (mode_flags & MIPI_DSI_MODE_VIDEO) {
>>> +        dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
>>> +        dw_mipi_dsi_video_mode_config(dsi);
>>> +        dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
>>> +    } else {
>>> +        dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
>>> +    }
>>> +
>>> +    dsi_write(dsi, DSI_PWR_UP, POWERUP);
>>> +}
>>> +
>>> +static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
>>> +{
>>> +    dsi_write(dsi, DSI_PWR_UP, RESET);
>>> +    dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
>>> +}
>>> +
>>> +static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
>>> +{
>>> +    /*
>>> +     * The maximum permitted escape clock is 20MHz and it is derived
>>> from
>>> +     * lanebyteclk, which is running at "lane_mbps / 8".  Thus we want:
>>> +     *
>>> +     *     (lane_mbps >> 3) / esc_clk_division < 20
>>> +     * which is:
>>> +     *     (lane_mbps >> 3) / 20 > esc_clk_division
>>> +     */
>>> +    u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
>>> +
>>> +    dsi_write(dsi, DSI_PWR_UP, RESET);
>>> +
>>> +    /*
>>> +     * TODO dw drv improvements
>>> +     * timeout clock division should be computed with the
>>> +     * high speed transmission counter timeout and byte lane...
>>> +     */
>>> +    dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
>>> +          TX_ESC_CLK_DIVIDSION(esc_clk_division));
>>> +}
>>> +
>>> +static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
>>> +                   struct drm_display_mode *mode)
>>> +{
>>> +    u32 val = 0, color = 0;
>>> +
>>> +    switch (dsi->format) {
>>> +    case MIPI_DSI_FMT_RGB888:
>>> +        color = DPI_COLOR_CODING_24BIT;
>>> +        break;
>>> +    case MIPI_DSI_FMT_RGB666:
>>> +        color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
>>> +        break;
>>> +    case MIPI_DSI_FMT_RGB666_PACKED:
>>> +        color = DPI_COLOR_CODING_18BIT_1;
>>> +        break;
>>> +    case MIPI_DSI_FMT_RGB565:
>>> +        color = DPI_COLOR_CODING_16BIT_1;
>>> +        break;
>>> +    }
>>> +
>>> +    if (mode->flags & DRM_MODE_FLAG_NVSYNC)
>>> +        val |= VSYNC_ACTIVE_LOW;
>>> +    if (mode->flags & DRM_MODE_FLAG_NHSYNC)
>>> +        val |= HSYNC_ACTIVE_LOW;
>>> +
>>> +    dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
>>> +    dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
>>> +    dsi_write(dsi, DSI_DPI_CFG_POL, val);
>>> +    /*
>>> +     * TODO dw drv improvements
>>> +     * largest packet sizes during hfp or during vsa/vpb/vfp
>>> +     * should be computed according to byte lane, lane number and only
>>> +     * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
>>> +     */
>>> +    dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
>>> +          | INVACT_LPCMD_TIME(4));
>>> +}
>>> +
>>> +static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
>>> +{
>>> +    dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
>>> +}
>>> +
>>> +static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
>>> +                        struct drm_display_mode *mode)
>>> +{
>>> +    /*
>>> +     * TODO dw drv improvements
>>> +     * only burst mode is supported here. For non-burst video modes,
>>> +     * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
>>> +     * DSI_VNPCR.NPSIZE... especially because this driver supports
>>> +     * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
>>> +     */
>>> +    dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
>>> +}
>>> +
>>> +static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
>>> +{
>>> +    /*
>>> +     * TODO dw drv improvements
>>> +     * compute high speed transmission counter timeout according
>>> +     * to the timeout clock division (TO_CLK_DIVIDSION) and byte lane...
>>> +     */
>>> +    dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) |
>>> LPRX_TO_CNT(1000));
>>> +    /*
>>> +     * TODO dw drv improvements
>>> +     * the Bus-Turn-Around Timeout Counter should be computed
>>> +     * according to byte lane...
>>> +     */
>>> +    dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
>>> +    dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
>>> +}
>>> +
>>> +/* Get lane byte clock cycles. */
>>> +static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
>>> +                       struct drm_display_mode *mode,
>>> +                       u32 hcomponent)
>>> +{
>>> +    u32 frac, lbcc;
>>> +
>>> +    lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
>>> +
>>> +    frac = lbcc % mode->clock;
>>> +    lbcc = lbcc / mode->clock;
>>> +    if (frac)
>>> +        lbcc++;
>>> +
>>> +    return lbcc;
>>> +}
>>> +
>>> +static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
>>> +                      struct drm_display_mode *mode)
>>> +{
>>> +    u32 htotal, hsa, hbp, lbcc;
>>> +
>>> +    htotal = mode->htotal;
>>> +    hsa = mode->hsync_end - mode->hsync_start;
>>> +    hbp = mode->htotal - mode->hsync_end;
>>> +
>>> +    /*
>>> +     * TODO dw drv improvements
>>> +     * computations below may be improved...
>>> +     */
>>> +    lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
>>> +    dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
>>> +
>>> +    lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
>>> +    dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
>>> +
>>> +    lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
>>> +    dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
>>> +}
>>> +
>>> +static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
>>> +                           struct drm_display_mode *mode)
>>> +{
>>> +    u32 vactive, vsa, vfp, vbp;
>>> +
>>> +    vactive = mode->vdisplay;
>>> +    vsa = mode->vsync_end - mode->vsync_start;
>>> +    vfp = mode->vsync_start - mode->vdisplay;
>>> +    vbp = mode->vtotal - mode->vsync_end;
>>> +
>>> +    dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
>>> +    dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
>>> +    dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
>>> +    dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
>>> +}
>>> +
>>> +static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
>>> +{
>>> +    /*
>>> +     * TODO dw drv improvements
>>> +     * data & clock lane timers should be computed according to panel
>>> +     * blankings and to the automatic clock lane control mode...
>>> +     * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
>>> +     * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
>>> +     */
>>> +    dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40)
>>> +          | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
>>> +
>>> +    dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
>>> +          | PHY_CLKLP2HS_TIME(0x40));
>>> +}
>>> +
>>> +static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
>>> +{
>>> +    /*
>>> +     * TODO dw drv improvements
>>> +     * stop wait time should be the maximum between host dsi
>>> +     * and panel stop wait times
>>> +     */
>>> +    dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
>>> +          N_LANES(dsi->lanes));
>>> +}
>>> +
>>> +static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
>>> +{
>>> +    /* Clear PHY state */
>>> +    dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
>>> +          | PHY_RSTZ | PHY_SHUTDOWNZ);
>>> +    dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
>>> +    dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
>>> +    dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
>>> +}
>>> +
>>> +static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
>>> +{
>>> +    u32 val;
>>> +    int ret;
>>> +
>>> +    dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
>>> +          PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
>>> +
>>> +    ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
>>> +                 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
>>> +    if (ret < 0)
>>> +        DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
>>> +
>>> +    ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
>>> +                 val, val & STOP_STATE_CLK_LANE, 1000,
>>> +                 PHY_STATUS_TIMEOUT_US);
>>> +    if (ret < 0)
>>> +        DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
>>> +}
>>> +
>>> +static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
>>> +{
>>> +    dsi_read(dsi, DSI_INT_ST0);
>>> +    dsi_read(dsi, DSI_INT_ST1);
>>> +    dsi_write(dsi, DSI_INT_MSK0, 0);
>>> +    dsi_write(dsi, DSI_INT_MSK1, 0);
>>> +}
>>> +
>>> +static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
>>> +{
>>> +    struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
>>> +
>>> +    /*
>>> +     * Switch to command mode before panel-bridge post_disable &
>>> +     * panel unprepare.
>>> +     * Note: panel-bridge disable & panel disable has been called
>>> +     * before by the drm framework.
>>> +     */
>>> +    dw_mipi_dsi_set_mode(dsi, 0);
>>> +
>>> +    /*
>>> +     * TODO Only way found to call panel-bridge post_disable &
>>> +     * panel unprepare before the dsi "final" disable...
>>> +     * This needs to be fixed in the drm_bridge framework and the API
>>> +     * needs to be updated to manage our own call chains...
>>> +     */
>>> +    dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge);
>>> +
>>> +    dw_mipi_dsi_disable(dsi);
>>> +    clk_disable_unprepare(dsi->pclk);
>>> +    pm_runtime_put(dsi->dev);
>>> +}
>>> +
>>> +void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
>>> +                 struct drm_display_mode *mode,
>>> +                 struct drm_display_mode *adjusted_mode)
>>> +{
>>> +    struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
>>> +    const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
>>> +    void *priv_data = dsi->plat_data->priv_data;
>>> +    int ret;
>>> +
>>> +    clk_prepare_enable(dsi->pclk);
>>> +
>>> +    ret = phy_ops->get_lane_mbps(priv_data, mode, dsi->mode_flags,
>>> +                     dsi->lanes, dsi->format, &dsi->lane_mbps);
>>> +    if (ret)
>>> +        DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n");
>>> +
>>> +    pm_runtime_get_sync(dsi->dev);
>>> +    dw_mipi_dsi_init(dsi);
>>> +    dw_mipi_dsi_dpi_config(dsi, mode);
>>> +    dw_mipi_dsi_packet_handler_config(dsi);
>>> +    dw_mipi_dsi_video_mode_config(dsi);
>>> +    dw_mipi_dsi_video_packet_config(dsi, mode);
>>> +    dw_mipi_dsi_command_mode_config(dsi);
>>> +    dw_mipi_dsi_line_timer_config(dsi, mode);
>>> +    dw_mipi_dsi_vertical_timing_config(dsi, mode);
>>> +
>>> +    dw_mipi_dsi_dphy_init(dsi);
>>> +    dw_mipi_dsi_dphy_timing_config(dsi);
>>> +    dw_mipi_dsi_dphy_interface_config(dsi);
>>> +
>>> +    dw_mipi_dsi_clear_err(dsi);
>>> +
>>> +    ret = phy_ops->init(priv_data);
>>> +    if (ret)
>>> +        DRM_DEBUG_DRIVER("Phy init() failed\n");
>>> +
>>> +    dw_mipi_dsi_dphy_enable(dsi);
>>> +
>>> +    dw_mipi_dsi_wait_for_two_frames(mode);
>>> +
>>> +    /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
>>> +    dw_mipi_dsi_set_mode(dsi, 0);
>>> +}
>>> +
>>> +static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge)
>>> +{
>>> +    struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
>>> +
>>> +    /* Switch to video mode for panel-bridge enable & panel enable */
>>> +    dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
>>> +}
>>> +
>>> +static enum drm_mode_status
>>> +dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
>>> +                  const struct drm_display_mode *mode)
>>> +{
>>> +    struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
>>> +    const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
>>> +    enum drm_mode_status mode_status = MODE_OK;
>>> +
>>> +    if (pdata->mode_valid)
>>> +        mode_status = pdata->mode_valid(pdata->priv_data, mode);
>>> +
>>> +    return mode_status;
>>> +}
>>> +
>>> +static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge)
>>> +{
>>> +    struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
>>> +
>>> +    if (!bridge->encoder) {
>>> +        DRM_ERROR("Parent encoder object not found\n");
>>> +        return -ENODEV;
>>> +    }
>>> +
>>> +    /* Set the encoder type as caller does not know it */
>>> +    bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI;
>>> +
>>> +    /* Attach the panel-bridge to the dsi bridge */
>>> +    return drm_bridge_attach(bridge->encoder, dsi->panel_bridge,
>>> bridge);
>>> +}
>>> +
>>> +static struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = {
>>> +    .mode_set     = dw_mipi_dsi_bridge_mode_set,
>>> +    .enable          = dw_mipi_dsi_bridge_enable,
>>> +    .post_disable = dw_mipi_dsi_bridge_post_disable,
>>> +    .mode_valid   = dw_mipi_dsi_bridge_mode_valid,
>>> +    .attach          = dw_mipi_dsi_bridge_attach,
>>> +};
>>> +
>>> +static struct dw_mipi_dsi *
>>> +__dw_mipi_dsi_probe(struct platform_device *pdev,
>>> +            const struct dw_mipi_dsi_plat_data *plat_data)
>>> +{
>>> +    struct device *dev = &pdev->dev;
>>> +    struct reset_control *apb_rst;
>>> +    struct dw_mipi_dsi *dsi;
>>> +    struct resource *res;
>>> +    int ret;
>>> +
>>> +    dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
>>> +    if (!dsi)
>>> +        return ERR_PTR(-ENOMEM);
>>> +
>>> +    dsi->dev = dev;
>>> +    dsi->plat_data = plat_data;
>>> +
>>> +    if (!plat_data->phy_ops->init ||
>>> !plat_data->phy_ops->get_lane_mbps) {
>>> +        DRM_ERROR("Phy not properly configured\n");
>>> +        return ERR_PTR(-ENODEV);
>>> +    }
>>> +
>>> +    if (!plat_data->base) {
>>> +        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> +        if (!res)
>>> +            return ERR_PTR(-ENODEV);
>>> +
>>> +        dsi->base = devm_ioremap_resource(dev, res);
>>> +        if (IS_ERR(dsi->base))
>>> +            return ERR_PTR(-ENODEV);
>>> +
>>> +    } else {
>>> +        dsi->base = plat_data->base;
>>> +    }
>>> +
>>> +    dsi->pclk = devm_clk_get(dev, "pclk");
>>> +    if (IS_ERR(dsi->pclk)) {
>>> +        ret = PTR_ERR(dsi->pclk);
>>> +        dev_err(dev, "Unable to get pclk: %d\n", ret);
>>> +        return ERR_PTR(ret);
>>> +    }
>>> +
>>> +    /*
>>> +     * Note that the reset was not defined in the initial device
>>> tree, so
>>> +     * we have to be prepared for it not being found.
>>> +     */
>>> +    apb_rst = devm_reset_control_get(dev, "apb");
>>> +    if (IS_ERR(apb_rst)) {
>>> +        ret = PTR_ERR(apb_rst);
>>> +        if (ret == -ENOENT) {
>>> +            apb_rst = NULL;
>>> +        } else {
>>> +            dev_err(dev, "Unable to get reset control: %d\n", ret);
>>> +            return ERR_PTR(ret);
>>> +        }
>>> +    }
>>> +
>>> +    if (apb_rst) {
>>> +        ret = clk_prepare_enable(dsi->pclk);
>>> +        if (ret) {
>>> +            dev_err(dev, "%s: Failed to enable pclk\n", __func__);
>>> +            return ERR_PTR(ret);
>>> +        }
>>> +
>>> +        reset_control_assert(apb_rst);
>>> +        usleep_range(10, 20);
>>> +        reset_control_deassert(apb_rst);
>>> +
>>> +        clk_disable_unprepare(dsi->pclk);
>>> +    }
>>> +
>>> +    pm_runtime_enable(dev);
>>> +
>>> +    dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
>>> +    dsi->dsi_host.dev = dev;
>>> +    ret = mipi_dsi_host_register(&dsi->dsi_host);
>>> +    if (ret) {
>>> +        dev_err(dev, "Failed to register MIPI host: %d\n", ret);
>>> +        return ERR_PTR(ret);
>>> +    }
>>> +
>>> +    dsi->bridge.driver_private = dsi;
>>> +    dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs;
>>> +#ifdef CONFIG_OF
>>> +    dsi->bridge.of_node = pdev->dev.of_node;
>>> +#endif
>>> +
>>> +    dev_set_drvdata(dev, dsi);
>>> +
>>> +    return dsi;
>>> +}
>>> +
>>> +static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
>>> +{
>>> +    pm_runtime_disable(dsi->dev);
>>> +}
>>> +
>>> +/*
>>> + * Probe/remove API, used from platforms based on the DRM bridge API.
>>> + */
>>> +int dw_mipi_dsi_probe(struct platform_device *pdev,
>>> +              const struct dw_mipi_dsi_plat_data *plat_data)
>>> +{
>>> +    struct dw_mipi_dsi *dsi;
>>> +
>>> +    dsi = __dw_mipi_dsi_probe(pdev, plat_data);
>>> +    if (IS_ERR(dsi))
>>> +        return PTR_ERR(dsi);
>>> +
>>> +    return 0;
>>> +}
>>> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe);
>>> +
>>> +void dw_mipi_dsi_remove(struct platform_device *pdev)
>>> +{
>>> +    struct dw_mipi_dsi *dsi = platform_get_drvdata(pdev);
>>> +
>>> +    mipi_dsi_host_unregister(&dsi->dsi_host);
>>> +
>>> +    __dw_mipi_dsi_remove(dsi);
>>> +}
>>> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove);
>>> +
>>> +/*
>>> + * Bind/unbind API, used from platforms based on the component
>>> framework.
>>> + */
>>> +int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder
>>> *encoder,
>>> +             const struct dw_mipi_dsi_plat_data *plat_data)
>>> +{
>>> +    struct dw_mipi_dsi *dsi;
>>> +    int ret;
>>> +
>>> +    dsi = __dw_mipi_dsi_probe(pdev, plat_data);
>>> +    if (IS_ERR(dsi))
>>> +        return PTR_ERR(dsi);
>>> +
>>> +    ret = drm_bridge_attach(encoder, &dsi->bridge, NULL);
>>> +    if (ret) {
>>> +        dw_mipi_dsi_remove(pdev);
>>> +        DRM_ERROR("Failed to initialize bridge with drm\n");
>>> +        return ret;
>>> +    }
>>> +
>>> +    return 0;
>>> +}
>>> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
>>> +
>>> +void dw_mipi_dsi_unbind(struct device *dev)
>>> +{
>>> +    struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
>>> +
>>> +    __dw_mipi_dsi_remove(dsi);
>>> +}
>>> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
>>> +
>>> +MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
>>> +MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
>>> +MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
>>> +MODULE_LICENSE("GPL");
>>> +MODULE_ALIAS("platform:dw-mipi-dsi");
>>> diff --git a/include/drm/bridge/dw_mipi_dsi.h
>>> b/include/drm/bridge/dw_mipi_dsi.h
>>> new file mode 100644
>>> index 0000000..9b30fec
>>> --- /dev/null
>>> +++ b/include/drm/bridge/dw_mipi_dsi.h
>>> @@ -0,0 +1,39 @@
>>> +/*
>>> + * Copyright (C) STMicroelectronics SA 2017
>>> + *
>>> + * Authors: Philippe Cornu <philippe.cornu@st.com>
>>> + *          Yannick Fertre <yannick.fertre@st.com>
>>> + *
>>> + * License terms:  GNU General Public License (GPL), version 2
>>> + */
>>> +
>>> +#ifndef __DW_MIPI_DSI__
>>> +#define __DW_MIPI_DSI__
>>> +
>>> +struct dw_mipi_dsi_phy_ops {
>>> +    int (*init)(void *priv_data);
>>> +    int (*get_lane_mbps)(void *priv_data, struct drm_display_mode *mode,
>>> +                 unsigned long mode_flags, u32 lanes, u32 format,
>>> +                 unsigned int *lane_mbps);
>>> +};
>>> +
>>> +struct dw_mipi_dsi_plat_data {
>>> +    void __iomem *base;
>>> +    unsigned int max_data_lanes;
>>> +
>>> +    enum drm_mode_status (*mode_valid)(void *priv_data,
>>> +                       const struct drm_display_mode *mode);
>>> +
>>> +    const struct dw_mipi_dsi_phy_ops *phy_ops;
>>> +
>>> +    void *priv_data;
>>> +};
>>> +
>>> +int dw_mipi_dsi_probe(struct platform_device *pdev,
>>> +              const struct dw_mipi_dsi_plat_data *plat_data);
>>> +void dw_mipi_dsi_remove(struct platform_device *pdev);
>>> +int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder
>>> *encoder,
>>> +             const struct dw_mipi_dsi_plat_data *plat_data);
>>> +void dw_mipi_dsi_unbind(struct device *dev);
>>> +
>>> +#endif /* __DW_MIPI_DSI__ */
>>>

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

^ permalink raw reply	[flat|nested] 24+ messages in thread
end of thread, other threads:[~2017-07-17  8:06 UTC | newest]

Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-07-03  8:41 [PATCH v5 0/7] STM32 DSI HOST Philippe CORNU
2017-07-03  8:41 ` Philippe CORNU
2017-07-03  8:41 ` [PATCH v5 1/7] drm/stm: ltdc: Fix leak of px clk enable in some error paths Philippe CORNU
2017-07-03  8:41   ` Philippe CORNU
2017-07-03  8:41 ` [PATCH v5 2/7] drm/stm: ltdc: Add panel-bridge support Philippe CORNU
2017-07-03  8:41   ` Philippe CORNU
2017-07-03  8:41 ` [PATCH v5 3/7] dt-bindings: display: Add Synopsys DW MIPI DSI host controller Philippe CORNU
2017-07-03  8:41   ` Philippe CORNU
     [not found]   ` <1499071287-10414-4-git-send-email-philippe.cornu-qxv4g6HH51o@public.gmane.org>
2017-07-07 15:53     ` Rob Herring
2017-07-07 15:53       ` Rob Herring
2017-07-03  8:41 ` [PATCH v5 4/7] drm/bridge/synopsys: Add MIPI DSI host controller bridge Philippe CORNU
2017-07-03  8:41   ` Philippe CORNU
2017-07-12  6:05   ` Archit Taneja
2017-07-12  6:05     ` Archit Taneja
2017-07-17  7:54     ` Philippe CORNU
2017-07-17  7:54       ` Philippe CORNU
2017-07-17  8:06       ` Archit Taneja
2017-07-17  8:06         ` Archit Taneja
2017-07-03  8:41 ` [PATCH v5 5/7] dt-bindings: display: stm32: remove st-display-subsystem parent node requirement Philippe CORNU
2017-07-03  8:41   ` Philippe CORNU
2017-07-03  8:41 ` [PATCH v5 6/7] dt-bindings: display: stm32: Add DSI controller Philippe CORNU
2017-07-03  8:41   ` Philippe CORNU
2017-07-03  8:41 ` [PATCH v5 7/7] drm/stm: Add STM32 DSI controller driver Philippe CORNU
2017-07-03  8:41   ` Philippe CORNU

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