[PATCH v2] mtd: spi-nor: Add support for ESMT F25L32QA and F25L64QA

[PATCH v2] mtd: spi-nor: Add support for ESMT F25L32QA and F25L64QA

[L. D. Pinney]

Add Support for the ESMT F25L32QA and F25L64QA
These are 4MB and 8MB SPI-NOR Chips from Elite Semiconductor Memory Technology

Signed-off-by: L. D. Pinney <ldpinney@gmail.com>
---
 drivers/mtd/spi-nor/spi-nor.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 70e52ffc2203..205efab4746c 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -960,6 +960,8 @@ static const struct flash_info spi_nor_ids[] = {
 
 	/* ESMT */
 	{ "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
+	{ "f25l32qa", INFO(0x8c4116, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
+	{ "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) },
 
 	/* Everspin */
 	{ "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },

Re: [PATCH v2] mtd: spi-nor: Add support for ESMT F25L32QA and F25L64QA

[Cyrille Pitchen]

Le 14/02/2017 à 23:27, L. D. Pinney a écrit :
> Add Support for the ESMT F25L32QA and F25L64QA
> These are 4MB and 8MB SPI-NOR Chips from Elite Semiconductor Memory Technology

checkpatch displays a warning for this line:
WARNING: Possible unwrapped commit description (prefer a maximum 75
chars per line)

So I moved "Technology" on the next line.

Please verify your patch with checkpatch next time ;)

> 
> Signed-off-by: L. D. Pinney <ldpinney@gmail.com>

Applied to spi-nor/next after rewording the commit message as explained
above.

Thanks!
> ---
>  drivers/mtd/spi-nor/spi-nor.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index 70e52ffc2203..205efab4746c 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -960,6 +960,8 @@ static const struct flash_info spi_nor_ids[] = {
>  
>  	/* ESMT */
>  	{ "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
> +	{ "f25l32qa", INFO(0x8c4116, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
> +	{ "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) },
>  
>  	/* Everspin */
>  	{ "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
> 
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