From: Kukjin Kim <kgene@kernel.org> To: "'Nicolas Pitre'" <nicolas.pitre@linaro.org>, "'Krzysztof Kozlowski'" <k.kozlowski@samsung.com> Cc: "'Russell King'" <linux@arm.linux.org.uk>, "'Will Deacon'" <will.deacon@arm.com>, "'David A. Long'" <dave.long@linaro.org>, "'Mark Rutland'" <mark.rutland@arm.com>, "'Vinayak Kale'" <vkale@apm.com>, "'Laura Abbott'" <lauraa@codeaurora.org>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, "'Kyungmin Park'" <kyungmin.park@samsung.com>, "'Marek Szyprowski'" <m.szyprowski@samsung.com>, "'Bartlomiej Zolnierkiewicz'" <b.zolnierkie@samsung.com>, "'Tomasz Figa'" <tomasz.figa@gmail.com>, "'Mark Brown'" <broonie@kernel.org> Subject: RE: [PATCH v2] ARM: cacheflush: Fix v7_exit_coherency_flush exynos build breakage on ARMv6 Date: Thu, 25 Sep 2014 14:58:31 +0900 [thread overview] Message-ID: <018f01cfd885$bc677320$35365960$@kernel.org> (raw) In-Reply-To: <alpine.LFD.2.11.1409240954220.8647@knanqh.ubzr> Nicolas Pitre wrote: > > On Wed, 24 Sep 2014, Krzysztof Kozlowski wrote: > > > This fixes build breakage of platsmp.c if ARMv6 was chosen for compile > > time options (e.g. by building allmodconfig): > > > > $ make allmodconfig > > $ make > > CC arch/arm/mach-exynos/platsmp.o > > /tmp/ccdQM0Eg.s: Assembler messages: > > /tmp/ccdQM0Eg.s:432: Error: selected processor does not support ARM mode `isb ' > > /tmp/ccdQM0Eg.s:437: Error: selected processor does not support ARM mode `isb ' > > /tmp/ccdQM0Eg.s:438: Error: selected processor does not support ARM mode `dsb ' > > make[1]: *** [arch/arm/mach-exynos/platsmp.o] Error 1 > > > > The error was introduced in commit "ARM: EXYNOS: Move code from > > hotplug.c to platsmp.c". Previously code using > > v7_exit_coherency_flush() macro was built with '-march=armv7-a' flag but > > this flag dissapeared during the movement. > > > > Fix this by annotating the v7_exit_coherency_flush() asm code with > > armv7-a architecture. > > > > Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> > > Reported-by: Mark Brown <broonie@kernel.org> > > Link: http://www.spinics.net/lists/linux-samsung-soc/msg36790.html > > Acked-by: Nicolas Pitre <nico@linaro.org> > Acked-by: Kukjin Kim <kgene.kim@samsung.com> For building allmodconfig, this patch fixes the problem. Hi Russell, Can you please take this? - Kukjin > > > > > --- > > > > Changes since v1: > > 1. Use armv7-a arch annotation instead replacing isb/dsb with macros. > > Suggsted by Nicolas Pitre. > > --- > > arch/arm/include/asm/cacheflush.h | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h > > index 79ecb4f34ffb..10e78d00a0bb 100644 > > --- a/arch/arm/include/asm/cacheflush.h > > +++ b/arch/arm/include/asm/cacheflush.h > > @@ -466,6 +466,7 @@ static inline void __sync_cache_range_r(volatile void *p, size_t size) > > */ > > #define v7_exit_coherency_flush(level) \ > > asm volatile( \ > > + ".arch armv7-a \n\t" \ > > "stmfd sp!, {fp, ip} \n\t" \ > > "mrc p15, 0, r0, c1, c0, 0 @ get SCTLR \n\t" \ > > "bic r0, r0, #"__stringify(CR_C)" \n\t" \ > > -- > > 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: kgene@kernel.org (Kukjin Kim) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2] ARM: cacheflush: Fix v7_exit_coherency_flush exynos build breakage on ARMv6 Date: Thu, 25 Sep 2014 14:58:31 +0900 [thread overview] Message-ID: <018f01cfd885$bc677320$35365960$@kernel.org> (raw) In-Reply-To: <alpine.LFD.2.11.1409240954220.8647@knanqh.ubzr> Nicolas Pitre wrote: > > On Wed, 24 Sep 2014, Krzysztof Kozlowski wrote: > > > This fixes build breakage of platsmp.c if ARMv6 was chosen for compile > > time options (e.g. by building allmodconfig): > > > > $ make allmodconfig > > $ make > > CC arch/arm/mach-exynos/platsmp.o > > /tmp/ccdQM0Eg.s: Assembler messages: > > /tmp/ccdQM0Eg.s:432: Error: selected processor does not support ARM mode `isb ' > > /tmp/ccdQM0Eg.s:437: Error: selected processor does not support ARM mode `isb ' > > /tmp/ccdQM0Eg.s:438: Error: selected processor does not support ARM mode `dsb ' > > make[1]: *** [arch/arm/mach-exynos/platsmp.o] Error 1 > > > > The error was introduced in commit "ARM: EXYNOS: Move code from > > hotplug.c to platsmp.c". Previously code using > > v7_exit_coherency_flush() macro was built with '-march=armv7-a' flag but > > this flag dissapeared during the movement. > > > > Fix this by annotating the v7_exit_coherency_flush() asm code with > > armv7-a architecture. > > > > Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> > > Reported-by: Mark Brown <broonie@kernel.org> > > Link: http://www.spinics.net/lists/linux-samsung-soc/msg36790.html > > Acked-by: Nicolas Pitre <nico@linaro.org> > Acked-by: Kukjin Kim <kgene.kim@samsung.com> For building allmodconfig, this patch fixes the problem. Hi Russell, Can you please take this? - Kukjin > > > > > --- > > > > Changes since v1: > > 1. Use armv7-a arch annotation instead replacing isb/dsb with macros. > > Suggsted by Nicolas Pitre. > > --- > > arch/arm/include/asm/cacheflush.h | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h > > index 79ecb4f34ffb..10e78d00a0bb 100644 > > --- a/arch/arm/include/asm/cacheflush.h > > +++ b/arch/arm/include/asm/cacheflush.h > > @@ -466,6 +466,7 @@ static inline void __sync_cache_range_r(volatile void *p, size_t size) > > */ > > #define v7_exit_coherency_flush(level) \ > > asm volatile( \ > > + ".arch armv7-a \n\t" \ > > "stmfd sp!, {fp, ip} \n\t" \ > > "mrc p15, 0, r0, c1, c0, 0 @ get SCTLR \n\t" \ > > "bic r0, r0, #"__stringify(CR_C)" \n\t" \ > > -- > > 1.9.1
next prev parent reply other threads:[~2014-09-25 5:58 UTC|newest] Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-09-24 8:27 [PATCH v2] ARM: cacheflush: Fix v7_exit_coherency_flush exynos build breakage on ARMv6 Krzysztof Kozlowski 2014-09-24 8:27 ` Krzysztof Kozlowski 2014-09-24 13:54 ` Nicolas Pitre 2014-09-24 13:54 ` Nicolas Pitre 2014-09-25 5:58 ` Kukjin Kim [this message] 2014-09-25 5:58 ` Kukjin Kim
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to='018f01cfd885$bc677320$35365960$@kernel.org' \ --to=kgene@kernel.org \ --cc=b.zolnierkie@samsung.com \ --cc=broonie@kernel.org \ --cc=dave.long@linaro.org \ --cc=k.kozlowski@samsung.com \ --cc=kyungmin.park@samsung.com \ --cc=lauraa@codeaurora.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux@arm.linux.org.uk \ --cc=m.szyprowski@samsung.com \ --cc=mark.rutland@arm.com \ --cc=nicolas.pitre@linaro.org \ --cc=tomasz.figa@gmail.com \ --cc=vkale@apm.com \ --cc=will.deacon@arm.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.