[U-Boot] [PATCH v1 0/6] Update stm32x7 serial driver

[U-Boot] [PATCH v1 0/6] Update stm32x7 serial driver

[patrice.chotard at st.com]

From: Patrice Chotard <patrice.chotard@st.com>

This series update the serial_stm32x7 driver used by both STM32F7 and STM32H7 SoCs :
	_ clean the code by using BIT and GENMASK macro
	_ remove useless CLK and OF_CONTROL flags
	_ add fifo support for H7
	_ introduce STM32F4 support

Currently, STM32F4 uses a dedicated serial driver drivers/serial/serial_stm32.c.
whereas STM32F7 and STM32H7 uses drivers/serial/serial/serial_stm32x7.c .
There is no reason to have 2 separate serial driver for STM32 SoCs family.

It's the first step to prepare STM32F4 conversion to driver model and 
device tree support. Hence this conversion will be done, serial_stm32x7.c 
driver will support alls SoCs (ie F4/F7 and H7) it will be then renamed with 
the generic name serial_stm32.c

Patrice Chotard (6):
  serial: stm32x7: cleanup code
  serial: stm32x7: remove stm32f7-usart and stm32h7-usart compatible
  serial: stm32x7: prepare the ground to STM32F4 support
  serial: stm32x7: add fifo support for STM32H7
  serial: stm32x7: add STM32F4 support
  serial: stm32x7: remove useless CONFIG_CLK and OF_CONTROL flag

 arch/arm/dts/stm32h743.dtsi     |  4 +-
 drivers/serial/Kconfig          |  4 +-
 drivers/serial/serial_stm32x7.c | 84 ++++++++++++++++++++++-------------------
 drivers/serial/serial_stm32x7.h | 71 +++++++++++++++++++++++-----------
 4 files changed, 99 insertions(+), 64 deletions(-)

-- 
1.9.1

[U-Boot] [PATCH v1 1/6] serial: stm32x7: cleanup code

[patrice.chotard at st.com]

From: Patrice Chotard <patrice.chotard@st.com>

Use BIT() macro and GENMASK() macro

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
---
 drivers/serial/serial_stm32x7.h | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h
index 9fe37af..6d36b74 100644
--- a/drivers/serial/serial_stm32x7.h
+++ b/drivers/serial/serial_stm32x7.h
@@ -28,18 +28,18 @@ struct stm32x7_serial_platdata {
 	unsigned long int clock_rate;
 };
 
-#define USART_CR1_OVER8			(1 << 15)
-#define USART_CR1_TE			(1 << 3)
-#define USART_CR1_RE			(1 << 2)
-#define USART_CR1_UE			(1 << 0)
+#define USART_CR1_OVER8			BIT(15)
+#define USART_CR1_TE			BIT(3)
+#define USART_CR1_RE			BIT(2)
+#define USART_CR1_UE			BIT(0)
 
-#define USART_CR3_OVRDIS		(1 << 12)
+#define USART_CR3_OVRDIS		BIT(12)
 
-#define USART_SR_FLAG_RXNE		(1 << 5)
-#define USART_SR_FLAG_TXE		(1 << 7)
+#define USART_SR_FLAG_RXNE		BIT(5)
+#define USART_SR_FLAG_TXE		BIT(7)
 
-#define USART_BRR_F_MASK		0xFF
+#define USART_BRR_F_MASK		GENMASK(7, 0)
 #define USART_BRR_M_SHIFT		4
-#define USART_BRR_M_MASK		0xFFF0
+#define USART_BRR_M_MASK		GENMASK(15, 4)
 
 #endif
-- 
1.9.1

[U-Boot] [PATCH v1 2/6] serial: stm32x7: remove stm32f7-usart and stm32h7-usart compatible

[patrice.chotard at st.com]

From: Patrice Chotard <patrice.chotard@st.com>

This patch remove the extra compatibility string "st,stm32h7-usart"
and "st,stm32f7-usart" to avoid confusion, save some time & space.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
---
 arch/arm/dts/stm32h743.dtsi     | 4 ++--
 drivers/serial/serial_stm32x7.c | 2 --
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi
index 16e9308..a413866 100644
--- a/arch/arm/dts/stm32h743.dtsi
+++ b/arch/arm/dts/stm32h743.dtsi
@@ -76,7 +76,7 @@
 		};
 
 		usart1: serial at 40011000 {
-			compatible = "st,stm32h7-usart", "st,stm32h7-uart";
+			compatible = "st,stm32h7-uart";
 			reg = <0x40011000 0x400>;
 			interrupts = <37>;
 			status = "disabled";
@@ -84,7 +84,7 @@
 		};
 
 		usart2: serial at 40004400 {
-			compatible = "st,stm32h7-usart", "st,stm32h7-uart";
+			compatible = "st,stm32h7-uart";
 			reg = <0x40004400 0x400>;
 			interrupts = <38>;
 			status = "disabled";
diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c
index 2f4eafa..bafcc36 100644
--- a/drivers/serial/serial_stm32x7.c
+++ b/drivers/serial/serial_stm32x7.c
@@ -110,9 +110,7 @@ static int stm32_serial_probe(struct udevice *dev)
 
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 static const struct udevice_id stm32_serial_id[] = {
-	{.compatible = "st,stm32f7-usart"},
 	{.compatible = "st,stm32f7-uart"},
-	{.compatible = "st,stm32h7-usart"},
 	{.compatible = "st,stm32h7-uart"},
 	{}
 };
-- 
1.9.1

[U-Boot] [PATCH v1 3/6] serial: stm32x7: prepare the ground to STM32F4 support

[patrice.chotard at st.com]

From: Patrice Chotard <patrice.chotard@st.com>

STM32F4 serial IP is similar to F7 and H7, but registers
are not located at the same offset and some feature are
only supported by F7 and H7 version.

Registers offset must be added for each version and also
some flags indicated the supported feature.

Update registers name to match with datasheet (sr to isr,
rx_dr to rdr and tx_dr to tdr) and remove unused regs
(cr2, gtpr, rtor, and rqr).

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
 drivers/serial/serial_stm32x7.c | 72 ++++++++++++++++++++++++-----------------
 drivers/serial/serial_stm32x7.h | 38 ++++++++++++++--------
 2 files changed, 66 insertions(+), 44 deletions(-)

diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c
index bafcc36..81a2308 100644
--- a/drivers/serial/serial_stm32x7.c
+++ b/drivers/serial/serial_stm32x7.c
@@ -17,67 +17,79 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
 {
-	struct stm32x7_serial_platdata *plat = dev->platdata;
-	struct stm32_usart *const usart = plat->base;
+	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+	bool stm32f4 = plat->uart_info->stm32f4;
+	fdt_addr_t base = plat->base;
 	u32 int_div, mantissa, fraction, oversampling;
 
 	int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);
 
 	if (int_div < 16) {
 		oversampling = 8;
-		setbits_le32(&usart->cr1, USART_CR1_OVER8);
+		setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
 	} else {
 		oversampling = 16;
-		clrbits_le32(&usart->cr1, USART_CR1_OVER8);
+		clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
 	}
 
 	mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
 	fraction = int_div % oversampling;
 
-	writel(mantissa | fraction, &usart->brr);
+	writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
 
 	return 0;
 }
 
 static int stm32_serial_getc(struct udevice *dev)
 {
-	struct stm32x7_serial_platdata *plat = dev->platdata;
-	struct stm32_usart *const usart = plat->base;
+	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+	bool stm32f4 = plat->uart_info->stm32f4;
+	fdt_addr_t base = plat->base;
 
-	if ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0)
+	if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_RXNE) == 0)
 		return -EAGAIN;
 
-	return readl(&usart->rd_dr);
+	return readl(base + RDR_OFFSET(stm32f4));
 }
 
 static int stm32_serial_putc(struct udevice *dev, const char c)
 {
-	struct stm32x7_serial_platdata *plat = dev->platdata;
-	struct stm32_usart *const usart = plat->base;
+	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+	bool stm32f4 = plat->uart_info->stm32f4;
+	fdt_addr_t base = plat->base;
 
-	if ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0)
+	if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_TXE) == 0)
 		return -EAGAIN;
 
-	writel(c, &usart->tx_dr);
+	writel(c, base + TDR_OFFSET(stm32f4));
 
 	return 0;
 }
 
 static int stm32_serial_pending(struct udevice *dev, bool input)
 {
-	struct stm32x7_serial_platdata *plat = dev->platdata;
-	struct stm32_usart *const usart = plat->base;
+	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+	bool stm32f4 = plat->uart_info->stm32f4;
+	fdt_addr_t base = plat->base;
 
 	if (input)
-		return readl(&usart->sr) & USART_SR_FLAG_RXNE ? 1 : 0;
+		return readl(base + ISR_OFFSET(stm32f4)) &
+			USART_SR_FLAG_RXNE ? 1 : 0;
 	else
-		return readl(&usart->sr) & USART_SR_FLAG_TXE ? 0 : 1;
+		return readl(base + ISR_OFFSET(stm32f4)) &
+			USART_SR_FLAG_TXE ? 0 : 1;
 }
 
 static int stm32_serial_probe(struct udevice *dev)
 {
-	struct stm32x7_serial_platdata *plat = dev->platdata;
-	struct stm32_usart *const usart = plat->base;
+	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+	fdt_addr_t base = plat->base;
+	bool stm32f4;
+	u8 uart_enable_bit;
+
+	plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
+	stm32f4 = plat->uart_info->stm32f4;
+	uart_enable_bit = plat->uart_info->uart_enable_bit;
 
 #ifdef CONFIG_CLK
 	int ret;
@@ -100,32 +112,32 @@ static int stm32_serial_probe(struct udevice *dev)
 		return plat->clock_rate;
 	};
 
-	/* Disable usart-> disable overrun-> enable usart */
-	clrbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);
-	setbits_le32(&usart->cr3, USART_CR3_OVRDIS);
-	setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);
+	/* Disable uart-> disable overrun-> enable uart */
+	clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
+		     BIT(uart_enable_bit));
+	if (plat->uart_info->has_overrun_disable)
+		setbits_le32(base + CR3_OFFSET(stm32f4), USART_CR3_OVRDIS);
+	setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
+		     BIT(uart_enable_bit));
 
 	return 0;
 }
 
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 static const struct udevice_id stm32_serial_id[] = {
-	{.compatible = "st,stm32f7-uart"},
-	{.compatible = "st,stm32h7-uart"},
+	{ .compatible = "st,stm32f7-uart", .data = (ulong)&stm32x7_info},
+	{ .compatible = "st,stm32h7-uart", .data = (ulong)&stm32x7_info},
 	{}
 };
 
 static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
 {
 	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
-	fdt_addr_t addr;
 
-	addr = devfdt_get_addr(dev);
-	if (addr == FDT_ADDR_T_NONE)
+	plat->base = devfdt_get_addr(dev);
+	if (plat->base == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
-	plat->base = (struct stm32_usart *)addr;
-
 	return 0;
 }
 #endif
diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h
index 6d36b74..4c6b7d4 100644
--- a/drivers/serial/serial_stm32x7.h
+++ b/drivers/serial/serial_stm32x7.h
@@ -8,30 +8,40 @@
 #ifndef _SERIAL_STM32_X7_
 #define _SERIAL_STM32_X7_
 
-struct stm32_usart {
-	u32 cr1;
-	u32 cr2;
-	u32 cr3;
-	u32 brr;
-	u32 gtpr;
-	u32 rtor;
-	u32 rqr;
-	u32 sr;
-	u32 icr;
-	u32 rd_dr;
-	u32 tx_dr;
+#define CR1_OFFSET(x)	(x ? 0x0c : 0x00)
+#define CR3_OFFSET(x)	(x ? 0x14 : 0x08)
+#define BRR_OFFSET(x)	(x ? 0x08 : 0x0c)
+#define ISR_OFFSET(x)	(x ? 0x00 : 0x1c)
+/*
+ * STM32F4 has one Data Register (DR) for received or transmitted
+ * data, so map Receive Data Register (RDR) and Transmit Data
+ * Register (TDR) at the same offset
+ */
+#define RDR_OFFSET(x)	(x ? 0x04 : 0x24)
+#define TDR_OFFSET(x)	(x ? 0x04 : 0x28)
+
+struct stm32_uart_info {
+	u8 uart_enable_bit;	/* UART_CR1_UE */
+	bool stm32f4;		/* true for STM32F4, false otherwise */
+	bool has_overrun_disable;
+};
+
+struct stm32_uart_info stm32x7_info = {
+	.uart_enable_bit = 0,
+	.stm32f4 = false,
+	.has_overrun_disable = true,
 };
 
 /* Information about a serial port */
 struct stm32x7_serial_platdata {
-	struct stm32_usart *base;  /* address of registers in physical memory */
+	fdt_addr_t base;  /* address of registers in physical memory */
+	struct stm32_uart_info *uart_info;
 	unsigned long int clock_rate;
 };
 
 #define USART_CR1_OVER8			BIT(15)
 #define USART_CR1_TE			BIT(3)
 #define USART_CR1_RE			BIT(2)
-#define USART_CR1_UE			BIT(0)
 
 #define USART_CR3_OVRDIS		BIT(12)
 
-- 
1.9.1

[U-Boot] [PATCH v1 4/6] serial: stm32x7: add fifo support for STM32H7

[patrice.chotard at st.com]

From: Patrice Chotard <patrice.chotard@st.com>

Add fifo mode support for rx and tx.
As only STM32H7 supports this feature, add has_fifo flag
to uart configuration to use fifo only when possible.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
 drivers/serial/serial_stm32x7.c |  6 ++++--
 drivers/serial/serial_stm32x7.h | 12 +++++++++++-
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c
index 81a2308..19697e3 100644
--- a/drivers/serial/serial_stm32x7.c
+++ b/drivers/serial/serial_stm32x7.c
@@ -117,6 +117,8 @@ static int stm32_serial_probe(struct udevice *dev)
 		     BIT(uart_enable_bit));
 	if (plat->uart_info->has_overrun_disable)
 		setbits_le32(base + CR3_OFFSET(stm32f4), USART_CR3_OVRDIS);
+	if (plat->uart_info->has_fifo)
+		setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
 	setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
 		     BIT(uart_enable_bit));
 
@@ -125,8 +127,8 @@ static int stm32_serial_probe(struct udevice *dev)
 
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 static const struct udevice_id stm32_serial_id[] = {
-	{ .compatible = "st,stm32f7-uart", .data = (ulong)&stm32x7_info},
-	{ .compatible = "st,stm32h7-uart", .data = (ulong)&stm32x7_info},
+	{ .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
+	{ .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
 	{}
 };
 
diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h
index 4c6b7d4..ed8a3ee 100644
--- a/drivers/serial/serial_stm32x7.h
+++ b/drivers/serial/serial_stm32x7.h
@@ -24,12 +24,21 @@ struct stm32_uart_info {
 	u8 uart_enable_bit;	/* UART_CR1_UE */
 	bool stm32f4;		/* true for STM32F4, false otherwise */
 	bool has_overrun_disable;
+	bool has_fifo;
 };
 
-struct stm32_uart_info stm32x7_info = {
+struct stm32_uart_info stm32f7_info = {
 	.uart_enable_bit = 0,
 	.stm32f4 = false,
 	.has_overrun_disable = true,
+	.has_fifo = false,
+};
+
+struct stm32_uart_info stm32h7_info = {
+	.uart_enable_bit = 0,
+	.stm32f4 = false,
+	.has_overrun_disable = true,
+	.has_fifo = true,
 };
 
 /* Information about a serial port */
@@ -39,6 +48,7 @@ struct stm32x7_serial_platdata {
 	unsigned long int clock_rate;
 };
 
+#define USART_CR1_FIFOEN		BIT(29)
 #define USART_CR1_OVER8			BIT(15)
 #define USART_CR1_TE			BIT(3)
 #define USART_CR1_RE			BIT(2)
-- 
1.9.1

[U-Boot] [PATCH v1 5/6] serial: stm32x7: add STM32F4 support

[patrice.chotard at st.com]

From: Patrice Chotard <patrice.chotard@st.com>

stm32f4 doesn't support FIFO and OVERRUN feature.
The enable bit is not at the same location in CR1
register than for STM32F7 and STM32H7.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
 drivers/serial/Kconfig          | 4 ++--
 drivers/serial/serial_stm32x7.c | 1 +
 drivers/serial/serial_stm32x7.h | 7 +++++++
 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 9bf2e26..7c54a49 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -531,9 +531,9 @@ config STI_ASC_SERIAL
 
 config STM32X7_SERIAL
 	bool "STMicroelectronics STM32 SoCs on-chip UART"
-	depends on DM_SERIAL && (STM32F7 || STM32H7)
+	depends on DM_SERIAL && (STM32F4 || STM32F7 || STM32H7)
 	help
-	  If you have a machine based on a STM32 F7 or H7 SoC you can
+	  If you have a machine based on a STM32 F4, F7 or H7 SoC you can
 	  enable its onboard serial ports, say Y to this option.
 	  If unsure, say N.
 
diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c
index 19697e3..44e8b42 100644
--- a/drivers/serial/serial_stm32x7.c
+++ b/drivers/serial/serial_stm32x7.c
@@ -127,6 +127,7 @@ static int stm32_serial_probe(struct udevice *dev)
 
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 static const struct udevice_id stm32_serial_id[] = {
+	{ .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
 	{ .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
 	{ .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
 	{}
diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h
index ed8a3ee..b914edf 100644
--- a/drivers/serial/serial_stm32x7.h
+++ b/drivers/serial/serial_stm32x7.h
@@ -27,6 +27,13 @@ struct stm32_uart_info {
 	bool has_fifo;
 };
 
+struct stm32_uart_info stm32f4_info = {
+	.stm32f4 = true,
+	.uart_enable_bit = 13,
+	.has_overrun_disable = false,
+	.has_fifo = false,
+};
+
 struct stm32_uart_info stm32f7_info = {
 	.uart_enable_bit = 0,
 	.stm32f4 = false,
-- 
1.9.1

[U-Boot] [PATCH v1 6/6] serial: stm32x7: remove useless CONFIG_CLK and OF_CONTROL flag

[patrice.chotard at st.com]

From: Patrice Chotard <patrice.chotard@st.com>

This driver is currently used by STM32F7 and STM32H7 SoCs.
As CONFIG_CLK and OF_CONTROL flags are set by default for these
2 SoCs, this flag becomes useless in this driver, so remove it.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
 drivers/serial/serial_stm32x7.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c
index 44e8b42..a5d529c 100644
--- a/drivers/serial/serial_stm32x7.c
+++ b/drivers/serial/serial_stm32x7.c
@@ -83,7 +83,9 @@ static int stm32_serial_pending(struct udevice *dev, bool input)
 static int stm32_serial_probe(struct udevice *dev)
 {
 	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+	struct clk clk;
 	fdt_addr_t base = plat->base;
+	int ret;
 	bool stm32f4;
 	u8 uart_enable_bit;
 
@@ -91,10 +93,6 @@ static int stm32_serial_probe(struct udevice *dev)
 	stm32f4 = plat->uart_info->stm32f4;
 	uart_enable_bit = plat->uart_info->uart_enable_bit;
 
-#ifdef CONFIG_CLK
-	int ret;
-	struct clk clk;
-
 	ret = clk_get_by_index(dev, 0, &clk);
 	if (ret < 0)
 		return ret;
@@ -104,7 +102,6 @@ static int stm32_serial_probe(struct udevice *dev)
 		dev_err(dev, "failed to enable clock\n");
 		return ret;
 	}
-#endif
 
 	plat->clock_rate = clk_get_rate(&clk);
 	if (plat->clock_rate < 0) {
@@ -125,7 +122,6 @@ static int stm32_serial_probe(struct udevice *dev)
 	return 0;
 }
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
 static const struct udevice_id stm32_serial_id[] = {
 	{ .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
 	{ .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
@@ -143,7 +139,6 @@ static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
 
 	return 0;
 }
-#endif
 
 static const struct dm_serial_ops stm32_serial_ops = {
 	.putc = stm32_serial_putc,
-- 
1.9.1

[U-Boot] [PATCH v1 1/6] serial: stm32x7: cleanup code

[Bo Shen]

Hi Patrice,

On 09/27/2017 06:44 AM, patrice.chotard at st.com wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
> 
> Use BIT() macro and GENMASK() macro
> 
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
> ---
>   drivers/serial/serial_stm32x7.h | 18 +++++++++---------
>   1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h
> index 9fe37af..6d36b74 100644
> --- a/drivers/serial/serial_stm32x7.h
> +++ b/drivers/serial/serial_stm32x7.h
> @@ -28,18 +28,18 @@ struct stm32x7_serial_platdata {
>   	unsigned long int clock_rate;
>   };
>   
> -#define USART_CR1_OVER8			(1 << 15)
> -#define USART_CR1_TE			(1 << 3)
> -#define USART_CR1_RE			(1 << 2)
> -#define USART_CR1_UE			(1 << 0)
> +#define USART_CR1_OVER8			BIT(15)
> +#define USART_CR1_TE			BIT(3)
> +#define USART_CR1_RE			BIT(2)
> +#define USART_CR1_UE			BIT(0)
>   
> -#define USART_CR3_OVRDIS		(1 << 12)
> +#define USART_CR3_OVRDIS		BIT(12)
>   
> -#define USART_SR_FLAG_RXNE		(1 << 5)
> -#define USART_SR_FLAG_TXE		(1 << 7)
> +#define USART_SR_FLAG_RXNE		BIT(5)
> +#define USART_SR_FLAG_TXE		BIT(7)
>   
> -#define USART_BRR_F_MASK		0xFF
> +#define USART_BRR_F_MASK		GENMASK(7, 0)
>   #define USART_BRR_M_SHIFT		4
> -#define USART_BRR_M_MASK		0xFFF0
> +#define USART_BRR_M_MASK		GENMASK(15, 4)

In stm32f7, according to the datasheet, there is no fraction and 
mantissa. Would you please confirm that?

At the same time, it makes me thinking the BRR is calculated differently 
between stm32f7 and stm32f4, would you please check it also in the 
driver code?

>   
>   #endif
> 

Best Regards,
Bo Shen

[U-Boot] [PATCH v1 3/6] serial: stm32x7: prepare the ground to STM32F4 support

[Bo Shen]

Hi Patrice,
   For this patch, overall I think you can use more generic method like 
define the parameter called ip_version in stm32_uart_info structure, and 
according to this information to covert base to different register map 
as following, then we can get rid of "stm32f4" in stm32_uart_info 
structure, and easy to extend if you have more versions.

--->8---
   struct stm32_usart_v1 { }; (version 1 register map)
   struct stm32_usart_v2 { }; (version 2 register map)

   switch (ip_version) {
   case v1:
     struct stm32_usart_v1 *ptr = (struct stm32_usart_v1 *)base;
     break;
   case v2:
     struct stm32_usart_v1 *ptr = (struct stm32_usart_v1 *)base;
     break;
   }
---8<---

Best Regards,
Bo Shen

On 09/27/2017 06:44 AM, patrice.chotard@st.com wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
> 
> STM32F4 serial IP is similar to F7 and H7, but registers
> are not located at the same offset and some feature are
> only supported by F7 and H7 version.
> 
> Registers offset must be added for each version and also
> some flags indicated the supported feature.
> 
> Update registers name to match with datasheet (sr to isr,
> rx_dr to rdr and tx_dr to tdr) and remove unused regs
> (cr2, gtpr, rtor, and rqr).
> 
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> ---
>   drivers/serial/serial_stm32x7.c | 72 ++++++++++++++++++++++++-----------------
>   drivers/serial/serial_stm32x7.h | 38 ++++++++++++++--------
>   2 files changed, 66 insertions(+), 44 deletions(-)
> 
> diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c
> index bafcc36..81a2308 100644
> --- a/drivers/serial/serial_stm32x7.c
> +++ b/drivers/serial/serial_stm32x7.c
> @@ -17,67 +17,79 @@ DECLARE_GLOBAL_DATA_PTR;
>   
>   static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
>   {
> -	struct stm32x7_serial_platdata *plat = dev->platdata;
> -	struct stm32_usart *const usart = plat->base;
> +	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
> +	bool stm32f4 = plat->uart_info->stm32f4;
> +	fdt_addr_t base = plat->base;
>   	u32 int_div, mantissa, fraction, oversampling;
>   
>   	int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);
>   
>   	if (int_div < 16) {
>   		oversampling = 8;
> -		setbits_le32(&usart->cr1, USART_CR1_OVER8);
> +		setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
>   	} else {
>   		oversampling = 16;
> -		clrbits_le32(&usart->cr1, USART_CR1_OVER8);
> +		clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
>   	}
>   
>   	mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
>   	fraction = int_div % oversampling;
>   
> -	writel(mantissa | fraction, &usart->brr);
> +	writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
>   
>   	return 0;
>   }
>   
>   static int stm32_serial_getc(struct udevice *dev)
>   {
> -	struct stm32x7_serial_platdata *plat = dev->platdata;
> -	struct stm32_usart *const usart = plat->base;
> +	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
> +	bool stm32f4 = plat->uart_info->stm32f4;
> +	fdt_addr_t base = plat->base;
>   
> -	if ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0)
> +	if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_RXNE) == 0)
>   		return -EAGAIN;
>   
> -	return readl(&usart->rd_dr);
> +	return readl(base + RDR_OFFSET(stm32f4));
>   }
>   
>   static int stm32_serial_putc(struct udevice *dev, const char c)
>   {
> -	struct stm32x7_serial_platdata *plat = dev->platdata;
> -	struct stm32_usart *const usart = plat->base;
> +	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
> +	bool stm32f4 = plat->uart_info->stm32f4;
> +	fdt_addr_t base = plat->base;
>   
> -	if ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0)
> +	if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_TXE) == 0)
>   		return -EAGAIN;
>   
> -	writel(c, &usart->tx_dr);
> +	writel(c, base + TDR_OFFSET(stm32f4));
>   
>   	return 0;
>   }
>   
>   static int stm32_serial_pending(struct udevice *dev, bool input)
>   {
> -	struct stm32x7_serial_platdata *plat = dev->platdata;
> -	struct stm32_usart *const usart = plat->base;
> +	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
> +	bool stm32f4 = plat->uart_info->stm32f4;
> +	fdt_addr_t base = plat->base;
>   
>   	if (input)
> -		return readl(&usart->sr) & USART_SR_FLAG_RXNE ? 1 : 0;
> +		return readl(base + ISR_OFFSET(stm32f4)) &
> +			USART_SR_FLAG_RXNE ? 1 : 0;
>   	else
> -		return readl(&usart->sr) & USART_SR_FLAG_TXE ? 0 : 1;
> +		return readl(base + ISR_OFFSET(stm32f4)) &
> +			USART_SR_FLAG_TXE ? 0 : 1;
>   }
>   
>   static int stm32_serial_probe(struct udevice *dev)
>   {
> -	struct stm32x7_serial_platdata *plat = dev->platdata;
> -	struct stm32_usart *const usart = plat->base;
> +	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
> +	fdt_addr_t base = plat->base;
> +	bool stm32f4;
> +	u8 uart_enable_bit;
> +
> +	plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
> +	stm32f4 = plat->uart_info->stm32f4;
> +	uart_enable_bit = plat->uart_info->uart_enable_bit;
>   
>   #ifdef CONFIG_CLK
>   	int ret;
> @@ -100,32 +112,32 @@ static int stm32_serial_probe(struct udevice *dev)
>   		return plat->clock_rate;
>   	};
>   
> -	/* Disable usart-> disable overrun-> enable usart */
> -	clrbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);
> -	setbits_le32(&usart->cr3, USART_CR3_OVRDIS);
> -	setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);
> +	/* Disable uart-> disable overrun-> enable uart */
> +	clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
> +		     BIT(uart_enable_bit));
> +	if (plat->uart_info->has_overrun_disable)
> +		setbits_le32(base + CR3_OFFSET(stm32f4), USART_CR3_OVRDIS);
> +	setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
> +		     BIT(uart_enable_bit));
>   
>   	return 0;
>   }
>   
>   #if CONFIG_IS_ENABLED(OF_CONTROL)
>   static const struct udevice_id stm32_serial_id[] = {
> -	{.compatible = "st,stm32f7-uart"},
> -	{.compatible = "st,stm32h7-uart"},
> +	{ .compatible = "st,stm32f7-uart", .data = (ulong)&stm32x7_info},
> +	{ .compatible = "st,stm32h7-uart", .data = (ulong)&stm32x7_info},
>   	{}
>   };
>   
>   static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
>   {
>   	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
> -	fdt_addr_t addr;
>   
> -	addr = devfdt_get_addr(dev);
> -	if (addr == FDT_ADDR_T_NONE)
> +	plat->base = devfdt_get_addr(dev);
> +	if (plat->base == FDT_ADDR_T_NONE)
>   		return -EINVAL;
>   
> -	plat->base = (struct stm32_usart *)addr;
> -
>   	return 0;
>   }
>   #endif
> diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h
> index 6d36b74..4c6b7d4 100644
> --- a/drivers/serial/serial_stm32x7.h
> +++ b/drivers/serial/serial_stm32x7.h
> @@ -8,30 +8,40 @@
>   #ifndef _SERIAL_STM32_X7_
>   #define _SERIAL_STM32_X7_
>   
> -struct stm32_usart {
> -	u32 cr1;
> -	u32 cr2;
> -	u32 cr3;
> -	u32 brr;
> -	u32 gtpr;
> -	u32 rtor;
> -	u32 rqr;
> -	u32 sr;
> -	u32 icr;
> -	u32 rd_dr;
> -	u32 tx_dr;
> +#define CR1_OFFSET(x)	(x ? 0x0c : 0x00)
> +#define CR3_OFFSET(x)	(x ? 0x14 : 0x08)
> +#define BRR_OFFSET(x)	(x ? 0x08 : 0x0c)
> +#define ISR_OFFSET(x)	(x ? 0x00 : 0x1c)
> +/*
> + * STM32F4 has one Data Register (DR) for received or transmitted
> + * data, so map Receive Data Register (RDR) and Transmit Data
> + * Register (TDR) at the same offset
> + */
> +#define RDR_OFFSET(x)	(x ? 0x04 : 0x24)
> +#define TDR_OFFSET(x)	(x ? 0x04 : 0x28)
> +
> +struct stm32_uart_info {
> +	u8 uart_enable_bit;	/* UART_CR1_UE */
> +	bool stm32f4;		/* true for STM32F4, false otherwise */
> +	bool has_overrun_disable;
> +};
> +
> +struct stm32_uart_info stm32x7_info = {
> +	.uart_enable_bit = 0,
> +	.stm32f4 = false,
> +	.has_overrun_disable = true,
>   };
>   
>   /* Information about a serial port */
>   struct stm32x7_serial_platdata {
> -	struct stm32_usart *base;  /* address of registers in physical memory */
> +	fdt_addr_t base;  /* address of registers in physical memory */
> +	struct stm32_uart_info *uart_info;
>   	unsigned long int clock_rate;
>   };
>   
>   #define USART_CR1_OVER8			BIT(15)
>   #define USART_CR1_TE			BIT(3)
>   #define USART_CR1_RE			BIT(2)
> -#define USART_CR1_UE			BIT(0)
>   
>   #define USART_CR3_OVRDIS		BIT(12)
>   
> 

[U-Boot] [PATCH v1 5/6] serial: stm32x7: add STM32F4 support

[Bo Shen]

Hi Patrice,

On 09/27/2017 06:44 AM, patrice.chotard at st.com wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
> 
> stm32f4 doesn't support FIFO and OVERRUN feature.
> The enable bit is not at the same location in CR1
> register than for STM32F7 and STM32H7.
> 
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> ---
>   drivers/serial/Kconfig          | 4 ++--
>   drivers/serial/serial_stm32x7.c | 1 +
>   drivers/serial/serial_stm32x7.h | 7 +++++++
>   3 files changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index 9bf2e26..7c54a49 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -531,9 +531,9 @@ config STI_ASC_SERIAL
>   
>   config STM32X7_SERIAL
>   	bool "STMicroelectronics STM32 SoCs on-chip UART"
> -	depends on DM_SERIAL && (STM32F7 || STM32H7)
> +	depends on DM_SERIAL && (STM32F4 || STM32F7 || STM32H7)
>   	help
> -	  If you have a machine based on a STM32 F7 or H7 SoC you can
> +	  If you have a machine based on a STM32 F4, F7 or H7 SoC you can
>   	  enable its onboard serial ports, say Y to this option.
>   	  If unsure, say N.
>   
> diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c
> index 19697e3..44e8b42 100644
> --- a/drivers/serial/serial_stm32x7.c
> +++ b/drivers/serial/serial_stm32x7.c
> @@ -127,6 +127,7 @@ static int stm32_serial_probe(struct udevice *dev)
>   
>   #if CONFIG_IS_ENABLED(OF_CONTROL)
>   static const struct udevice_id stm32_serial_id[] = {
> +	{ .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},

s/st,stm32-uart/st,stm32f4-uart/ (?)

>   	{ .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
>   	{ .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
>   	{}
> diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h
> index ed8a3ee..b914edf 100644
> --- a/drivers/serial/serial_stm32x7.h
> +++ b/drivers/serial/serial_stm32x7.h
> @@ -27,6 +27,13 @@ struct stm32_uart_info {
>   	bool has_fifo;
>   };
>   
> +struct stm32_uart_info stm32f4_info = {
> +	.stm32f4 = true,
> +	.uart_enable_bit = 13,
> +	.has_overrun_disable = false,
> +	.has_fifo = false,
> +};
> +
>   struct stm32_uart_info stm32f7_info = {
>   	.uart_enable_bit = 0,
>   	.stm32f4 = false,
> 

Best Regards,
Bo Shen

[U-Boot] [PATCH v1 1/6] serial: stm32x7: cleanup code

[Patrice CHOTARD]

Hi Bo

On 09/29/2017 08:12 AM, Bo Shen wrote:
> Hi Patrice,
> 
> On 09/27/2017 06:44 AM, patrice.chotard at st.com wrote:
>> From: Patrice Chotard <patrice.chotard@st.com>
>>
>> Use BIT() macro and GENMASK() macro
>>
>> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
>> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
>> ---
>>   drivers/serial/serial_stm32x7.h | 18 +++++++++---------
>>   1 file changed, 9 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/serial/serial_stm32x7.h 
>> b/drivers/serial/serial_stm32x7.h
>> index 9fe37af..6d36b74 100644
>> --- a/drivers/serial/serial_stm32x7.h
>> +++ b/drivers/serial/serial_stm32x7.h
>> @@ -28,18 +28,18 @@ struct stm32x7_serial_platdata {
>>       unsigned long int clock_rate;
>>   };
>> -#define USART_CR1_OVER8            (1 << 15)
>> -#define USART_CR1_TE            (1 << 3)
>> -#define USART_CR1_RE            (1 << 2)
>> -#define USART_CR1_UE            (1 << 0)
>> +#define USART_CR1_OVER8            BIT(15)
>> +#define USART_CR1_TE            BIT(3)
>> +#define USART_CR1_RE            BIT(2)
>> +#define USART_CR1_UE            BIT(0)
>> -#define USART_CR3_OVRDIS        (1 << 12)
>> +#define USART_CR3_OVRDIS        BIT(12)
>> -#define USART_SR_FLAG_RXNE        (1 << 5)
>> -#define USART_SR_FLAG_TXE        (1 << 7)
>> +#define USART_SR_FLAG_RXNE        BIT(5)
>> +#define USART_SR_FLAG_TXE        BIT(7)
>> -#define USART_BRR_F_MASK        0xFF
>> +#define USART_BRR_F_MASK        GENMASK(7, 0)
>>   #define USART_BRR_M_SHIFT        4
>> -#define USART_BRR_M_MASK        0xFFF0
>> +#define USART_BRR_M_MASK        GENMASK(15, 4)
> 
> In stm32f7, according to the datasheet, there is no fraction and 
> mantissa. Would you please confirm that?

Agree,
"mantissa" is a different wording for BRR[15:4] bits
and "fraction" is used for BRR[0:3] bits


> 
> At the same time, it makes me thinking the BRR is calculated differently 
> between stm32f7 and stm32f4, would you please check it also in the 
> driver code?

Previously BRR was calculated with a more complex formula, i simply 
reused the same BRR formula from the kernel serial driver common to 
F4/F7/H7 (see drivers/tty/serial/stm32-usart.c)


> 
>>   #endif
>>
> 
> Best Regards,
> Bo Shen

Regards

Patrice

[U-Boot] [PATCH v1 3/6] serial: stm32x7: prepare the ground to STM32F4 support

[Patrice CHOTARD]

Hi Bo

On 09/29/2017 08:24 AM, Bo Shen wrote:
> Hi Patrice,
>    For this patch, overall I think you can use more generic method like 
> define the parameter called ip_version in stm32_uart_info structure, and 
> according to this information to covert base to different register map 
> as following, then we can get rid of "stm32f4" in stm32_uart_info 
> structure, and easy to extend if you have more versions.
> 
> --->8---
>    struct stm32_usart_v1 { }; (version 1 register map)
>    struct stm32_usart_v2 { }; (version 2 register map)
> 
>    switch (ip_version) {
>    case v1:
>      struct stm32_usart_v1 *ptr = (struct stm32_usart_v1 *)base;
>      break;
>    case v2:
>      struct stm32_usart_v1 *ptr = (struct stm32_usart_v1 *)base;
>      break;
>    }
> ---8<---

It's another way to solve this problem, i will check if it's more 
efficient regarding code/data size

Thanks for the tips.

Patrice

> 
> Best Regards,
> Bo Shen
> 
> On 09/27/2017 06:44 AM, patrice.chotard at st.com wrote:
>> From: Patrice Chotard <patrice.chotard@st.com>
>>
>> STM32F4 serial IP is similar to F7 and H7, but registers
>> are not located at the same offset and some feature are
>> only supported by F7 and H7 version.
>>
>> Registers offset must be added for each version and also
>> some flags indicated the supported feature.
>>
>> Update registers name to match with datasheet (sr to isr,
>> rx_dr to rdr and tx_dr to tdr) and remove unused regs
>> (cr2, gtpr, rtor, and rqr).
>>
>> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
>> ---
>>   drivers/serial/serial_stm32x7.c | 72 
>> ++++++++++++++++++++++++-----------------
>>   drivers/serial/serial_stm32x7.h | 38 ++++++++++++++--------
>>   2 files changed, 66 insertions(+), 44 deletions(-)
>>
>> diff --git a/drivers/serial/serial_stm32x7.c 
>> b/drivers/serial/serial_stm32x7.c
>> index bafcc36..81a2308 100644
>> --- a/drivers/serial/serial_stm32x7.c
>> +++ b/drivers/serial/serial_stm32x7.c
>> @@ -17,67 +17,79 @@ DECLARE_GLOBAL_DATA_PTR;
>>   static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
>>   {
>> -    struct stm32x7_serial_platdata *plat = dev->platdata;
>> -    struct stm32_usart *const usart = plat->base;
>> +    struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
>> +    bool stm32f4 = plat->uart_info->stm32f4;
>> +    fdt_addr_t base = plat->base;
>>       u32 int_div, mantissa, fraction, oversampling;
>>       int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);
>>       if (int_div < 16) {
>>           oversampling = 8;
>> -        setbits_le32(&usart->cr1, USART_CR1_OVER8);
>> +        setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
>>       } else {
>>           oversampling = 16;
>> -        clrbits_le32(&usart->cr1, USART_CR1_OVER8);
>> +        clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
>>       }
>>       mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
>>       fraction = int_div % oversampling;
>> -    writel(mantissa | fraction, &usart->brr);
>> +    writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
>>       return 0;
>>   }
>>   static int stm32_serial_getc(struct udevice *dev)
>>   {
>> -    struct stm32x7_serial_platdata *plat = dev->platdata;
>> -    struct stm32_usart *const usart = plat->base;
>> +    struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
>> +    bool stm32f4 = plat->uart_info->stm32f4;
>> +    fdt_addr_t base = plat->base;
>> -    if ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0)
>> +    if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_RXNE) == 0)
>>           return -EAGAIN;
>> -    return readl(&usart->rd_dr);
>> +    return readl(base + RDR_OFFSET(stm32f4));
>>   }
>>   static int stm32_serial_putc(struct udevice *dev, const char c)
>>   {
>> -    struct stm32x7_serial_platdata *plat = dev->platdata;
>> -    struct stm32_usart *const usart = plat->base;
>> +    struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
>> +    bool stm32f4 = plat->uart_info->stm32f4;
>> +    fdt_addr_t base = plat->base;
>> -    if ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0)
>> +    if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_TXE) == 0)
>>           return -EAGAIN;
>> -    writel(c, &usart->tx_dr);
>> +    writel(c, base + TDR_OFFSET(stm32f4));
>>       return 0;
>>   }
>>   static int stm32_serial_pending(struct udevice *dev, bool input)
>>   {
>> -    struct stm32x7_serial_platdata *plat = dev->platdata;
>> -    struct stm32_usart *const usart = plat->base;
>> +    struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
>> +    bool stm32f4 = plat->uart_info->stm32f4;
>> +    fdt_addr_t base = plat->base;
>>       if (input)
>> -        return readl(&usart->sr) & USART_SR_FLAG_RXNE ? 1 : 0;
>> +        return readl(base + ISR_OFFSET(stm32f4)) &
>> +            USART_SR_FLAG_RXNE ? 1 : 0;
>>       else
>> -        return readl(&usart->sr) & USART_SR_FLAG_TXE ? 0 : 1;
>> +        return readl(base + ISR_OFFSET(stm32f4)) &
>> +            USART_SR_FLAG_TXE ? 0 : 1;
>>   }
>>   static int stm32_serial_probe(struct udevice *dev)
>>   {
>> -    struct stm32x7_serial_platdata *plat = dev->platdata;
>> -    struct stm32_usart *const usart = plat->base;
>> +    struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
>> +    fdt_addr_t base = plat->base;
>> +    bool stm32f4;
>> +    u8 uart_enable_bit;
>> +
>> +    plat->uart_info = (struct stm32_uart_info 
>> *)dev_get_driver_data(dev);
>> +    stm32f4 = plat->uart_info->stm32f4;
>> +    uart_enable_bit = plat->uart_info->uart_enable_bit;
>>   #ifdef CONFIG_CLK
>>       int ret;
>> @@ -100,32 +112,32 @@ static int stm32_serial_probe(struct udevice *dev)
>>           return plat->clock_rate;
>>       };
>> -    /* Disable usart-> disable overrun-> enable usart */
>> -    clrbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | 
>> USART_CR1_UE);
>> -    setbits_le32(&usart->cr3, USART_CR3_OVRDIS);
>> -    setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | 
>> USART_CR1_UE);
>> +    /* Disable uart-> disable overrun-> enable uart */
>> +    clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | 
>> USART_CR1_TE |
>> +             BIT(uart_enable_bit));
>> +    if (plat->uart_info->has_overrun_disable)
>> +        setbits_le32(base + CR3_OFFSET(stm32f4), USART_CR3_OVRDIS);
>> +    setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | 
>> USART_CR1_TE |
>> +             BIT(uart_enable_bit));
>>       return 0;
>>   }
>>   #if CONFIG_IS_ENABLED(OF_CONTROL)
>>   static const struct udevice_id stm32_serial_id[] = {
>> -    {.compatible = "st,stm32f7-uart"},
>> -    {.compatible = "st,stm32h7-uart"},
>> +    { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32x7_info},
>> +    { .compatible = "st,stm32h7-uart", .data = (ulong)&stm32x7_info},
>>       {}
>>   };
>>   static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
>>   {
>>       struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
>> -    fdt_addr_t addr;
>> -    addr = devfdt_get_addr(dev);
>> -    if (addr == FDT_ADDR_T_NONE)
>> +    plat->base = devfdt_get_addr(dev);
>> +    if (plat->base == FDT_ADDR_T_NONE)
>>           return -EINVAL;
>> -    plat->base = (struct stm32_usart *)addr;
>> -
>>       return 0;
>>   }
>>   #endif
>> diff --git a/drivers/serial/serial_stm32x7.h 
>> b/drivers/serial/serial_stm32x7.h
>> index 6d36b74..4c6b7d4 100644
>> --- a/drivers/serial/serial_stm32x7.h
>> +++ b/drivers/serial/serial_stm32x7.h
>> @@ -8,30 +8,40 @@
>>   #ifndef _SERIAL_STM32_X7_
>>   #define _SERIAL_STM32_X7_
>> -struct stm32_usart {
>> -    u32 cr1;
>> -    u32 cr2;
>> -    u32 cr3;
>> -    u32 brr;
>> -    u32 gtpr;
>> -    u32 rtor;
>> -    u32 rqr;
>> -    u32 sr;
>> -    u32 icr;
>> -    u32 rd_dr;
>> -    u32 tx_dr;
>> +#define CR1_OFFSET(x)    (x ? 0x0c : 0x00)
>> +#define CR3_OFFSET(x)    (x ? 0x14 : 0x08)
>> +#define BRR_OFFSET(x)    (x ? 0x08 : 0x0c)
>> +#define ISR_OFFSET(x)    (x ? 0x00 : 0x1c)
>> +/*
>> + * STM32F4 has one Data Register (DR) for received or transmitted
>> + * data, so map Receive Data Register (RDR) and Transmit Data
>> + * Register (TDR) at the same offset
>> + */
>> +#define RDR_OFFSET(x)    (x ? 0x04 : 0x24)
>> +#define TDR_OFFSET(x)    (x ? 0x04 : 0x28)
>> +
>> +struct stm32_uart_info {
>> +    u8 uart_enable_bit;    /* UART_CR1_UE */
>> +    bool stm32f4;        /* true for STM32F4, false otherwise */
>> +    bool has_overrun_disable;
>> +};
>> +
>> +struct stm32_uart_info stm32x7_info = {
>> +    .uart_enable_bit = 0,
>> +    .stm32f4 = false,
>> +    .has_overrun_disable = true,
>>   };
>>   /* Information about a serial port */
>>   struct stm32x7_serial_platdata {
>> -    struct stm32_usart *base;  /* address of registers in physical 
>> memory */
>> +    fdt_addr_t base;  /* address of registers in physical memory */
>> +    struct stm32_uart_info *uart_info;
>>       unsigned long int clock_rate;
>>   };
>>   #define USART_CR1_OVER8            BIT(15)
>>   #define USART_CR1_TE            BIT(3)
>>   #define USART_CR1_RE            BIT(2)
>> -#define USART_CR1_UE            BIT(0)
>>   #define USART_CR3_OVRDIS        BIT(12)
>>

[U-Boot] [PATCH v1 5/6] serial: stm32x7: add STM32F4 support

[Patrice CHOTARD]

Hi Bo

On 09/29/2017 08:26 AM, Bo Shen wrote:
> Hi Patrice,
> 
> On 09/27/2017 06:44 AM, patrice.chotard at st.com wrote:
>> From: Patrice Chotard <patrice.chotard@st.com>
>>
>> stm32f4 doesn't support FIFO and OVERRUN feature.
>> The enable bit is not at the same location in CR1
>> register than for STM32F7 and STM32H7.
>>
>> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
>> ---
>>   drivers/serial/Kconfig          | 4 ++--
>>   drivers/serial/serial_stm32x7.c | 1 +
>>   drivers/serial/serial_stm32x7.h | 7 +++++++
>>   3 files changed, 10 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
>> index 9bf2e26..7c54a49 100644
>> --- a/drivers/serial/Kconfig
>> +++ b/drivers/serial/Kconfig
>> @@ -531,9 +531,9 @@ config STI_ASC_SERIAL
>>   config STM32X7_SERIAL
>>       bool "STMicroelectronics STM32 SoCs on-chip UART"
>> -    depends on DM_SERIAL && (STM32F7 || STM32H7)
>> +    depends on DM_SERIAL && (STM32F4 || STM32F7 || STM32H7)
>>       help
>> -      If you have a machine based on a STM32 F7 or H7 SoC you can
>> +      If you have a machine based on a STM32 F4, F7 or H7 SoC you can
>>         enable its onboard serial ports, say Y to this option.
>>         If unsure, say N.
>> diff --git a/drivers/serial/serial_stm32x7.c 
>> b/drivers/serial/serial_stm32x7.c
>> index 19697e3..44e8b42 100644
>> --- a/drivers/serial/serial_stm32x7.c
>> +++ b/drivers/serial/serial_stm32x7.c
>> @@ -127,6 +127,7 @@ static int stm32_serial_probe(struct udevice *dev)
>>   #if CONFIG_IS_ENABLED(OF_CONTROL)
>>   static const struct udevice_id stm32_serial_id[] = {
>> +    { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
> 
> s/st,stm32-uart/st,stm32f4-uart/ (?)

We use the same DT bindings than kernel one and we want to keep aligned.

Historically stm32-uart is dedicated for F4, which was introduced first.
And then with introduction of F7 and H7, new compatible string 
(stm32f7-uart and stm32h7-uart) was added.

Patrice
> 
>>       { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
>>       { .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
>>       {}
>> diff --git a/drivers/serial/serial_stm32x7.h 
>> b/drivers/serial/serial_stm32x7.h
>> index ed8a3ee..b914edf 100644
>> --- a/drivers/serial/serial_stm32x7.h
>> +++ b/drivers/serial/serial_stm32x7.h
>> @@ -27,6 +27,13 @@ struct stm32_uart_info {
>>       bool has_fifo;
>>   };
>> +struct stm32_uart_info stm32f4_info = {
>> +    .stm32f4 = true,
>> +    .uart_enable_bit = 13,
>> +    .has_overrun_disable = false,
>> +    .has_fifo = false,
>> +};
>> +
>>   struct stm32_uart_info stm32f7_info = {
>>       .uart_enable_bit = 0,
>>       .stm32f4 = false,
>>
> 
> Best Regards,
> Bo Shen

[U-Boot] [PATCH v1 0/6] Update stm32x7 serial driver

[Vikas MANOCHA]

Hi,

> -----Original Message-----
> From: Patrice CHOTARD
> Sent: Wednesday, September 27, 2017 6:45 AM
> To: u-boot at lists.denx.de; albert.u.boot at aribaud.net; sjg at chromium.org; Vikas MANOCHA <vikas.manocha@st.com>
> Cc: Patrice CHOTARD <patrice.chotard@st.com>; Patrick DELAUNAY <patrick.delaunay@st.com>; Christophe KERELLO
> <christophe.kerello@st.com>
> Subject: [PATCH v1 0/6] Update stm32x7 serial driver
> 
> From: Patrice Chotard <patrice.chotard@st.com>
> 
> This series update the serial_stm32x7 driver used by both STM32F7 and STM32H7 SoCs :
> 	_ clean the code by using BIT and GENMASK macro
> 	_ remove useless CLK and OF_CONTROL flags
> 	_ add fifo support for H7
> 	_ introduce STM32F4 support
> 
> Currently, STM32F4 uses a dedicated serial driver drivers/serial/serial_stm32.c.
> whereas STM32F7 and STM32H7 uses drivers/serial/serial/serial_stm32x7.c .
> There is no reason to have 2 separate serial driver for STM32 SoCs family.
> 
> It's the first step to prepare STM32F4 conversion to driver model and device tree support. Hence this conversion will be done,
> serial_stm32x7.c driver will support alls SoCs (ie F4/F7 and H7) it will be then renamed with the generic name serial_stm32.c

For all series:
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>

Cheers,
Vikas

> 
> Patrice Chotard (6):
>   serial: stm32x7: cleanup code
>   serial: stm32x7: remove stm32f7-usart and stm32h7-usart compatible
>   serial: stm32x7: prepare the ground to STM32F4 support
>   serial: stm32x7: add fifo support for STM32H7
>   serial: stm32x7: add STM32F4 support
>   serial: stm32x7: remove useless CONFIG_CLK and OF_CONTROL flag
> 
>  arch/arm/dts/stm32h743.dtsi     |  4 +-
>  drivers/serial/Kconfig          |  4 +-
>  drivers/serial/serial_stm32x7.c | 84 ++++++++++++++++++++++-------------------
>  drivers/serial/serial_stm32x7.h | 71 +++++++++++++++++++++++-----------
>  4 files changed, 99 insertions(+), 64 deletions(-)
> 
> --
> 1.9.1

[U-Boot] [PATCH v1 5/6] serial: stm32x7: add STM32F4 support

[Bo Shen]

Hi Patrice,

On 09/29/2017 04:52 AM, Patrice CHOTARD wrote:
>>> diff --git a/drivers/serial/serial_stm32x7.c
>>> b/drivers/serial/serial_stm32x7.c
>>> index 19697e3..44e8b42 100644
>>> --- a/drivers/serial/serial_stm32x7.c
>>> +++ b/drivers/serial/serial_stm32x7.c
>>> @@ -127,6 +127,7 @@ static int stm32_serial_probe(struct udevice *dev)
>>>    #if CONFIG_IS_ENABLED(OF_CONTROL)
>>>    static const struct udevice_id stm32_serial_id[] = {
>>> +    { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
>> s/st,stm32-uart/st,stm32f4-uart/ (?)
> We use the same DT bindings than kernel one and we want to keep aligned.

I'd suggest to send a patch to kernel to rename it.

> Historically stm32-uart is dedicated for F4, which was introduced first.
> And then with introduction of F7 and H7, new compatible string
> (stm32f7-uart and stm32h7-uart) was added.

If we have patch in kernel to rename it, then it will be more clear.

Best Regards,
Bo Shen

[U-Boot] [U-Boot,v1,1/6] serial: stm32x7: cleanup code

[Tom Rini]

On Wed, Sep 27, 2017 at 03:44:48PM +0200, patrice.chotard at st.com wrote:

> From: Patrice Chotard <patrice.chotard@st.com>
> 
> Use BIT() macro and GENMASK() macro
> 
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, v1, 2/6] serial: stm32x7: remove stm32f7-usart and stm32h7-usart compatible

[Tom Rini]

On Wed, Sep 27, 2017 at 03:44:49PM +0200, patrice.chotard at st.com wrote:

> From: Patrice Chotard <patrice.chotard@st.com>
> 
> This patch remove the extra compatibility string "st,stm32h7-usart"
> and "st,stm32f7-usart" to avoid confusion, save some time & space.
> 
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, v1, 3/6] serial: stm32x7: prepare the ground to STM32F4 support

[Tom Rini]

On Wed, Sep 27, 2017 at 03:44:50PM +0200, patrice.chotard at st.com wrote:

> From: Patrice Chotard <patrice.chotard@st.com>
> 
> STM32F4 serial IP is similar to F7 and H7, but registers
> are not located at the same offset and some feature are
> only supported by F7 and H7 version.
> 
> Registers offset must be added for each version and also
> some flags indicated the supported feature.
> 
> Update registers name to match with datasheet (sr to isr,
> rx_dr to rdr and tx_dr to tdr) and remove unused regs
> (cr2, gtpr, rtor, and rqr).
> 
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, v1, 4/6] serial: stm32x7: add fifo support for STM32H7

[Tom Rini]

On Wed, Sep 27, 2017 at 03:44:51PM +0200, patrice.chotard at st.com wrote:

> From: Patrice Chotard <patrice.chotard@st.com>
> 
> Add fifo mode support for rx and tx.
> As only STM32H7 supports this feature, add has_fifo flag
> to uart configuration to use fifo only when possible.
> 
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot,v1,5/6] serial: stm32x7: add STM32F4 support

[Tom Rini]

On Wed, Sep 27, 2017 at 03:44:52PM +0200, patrice.chotard at st.com wrote:

> From: Patrice Chotard <patrice.chotard@st.com>
> 
> stm32f4 doesn't support FIFO and OVERRUN feature.
> The enable bit is not at the same location in CR1
> register than for STM32F7 and STM32H7.
> 
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, v1, 6/6] serial: stm32x7: remove useless CONFIG_CLK and OF_CONTROL flag

[Tom Rini]

On Wed, Sep 27, 2017 at 03:44:53PM +0200, patrice.chotard at st.com wrote:

> From: Patrice Chotard <patrice.chotard@st.com>
> 
> This driver is currently used by STM32F7 and STM32H7 SoCs.
> As CONFIG_CLK and OF_CONTROL flags are set by default for these
> 2 SoCs, this flag becomes useless in this driver, so remove it.
> 
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Applied to u-boot/master, thanks!

-- 
Tom
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