* [PATCH] hw/ide: Make IDEDMAOps handlers take a const IDEDMA pointer
@ 2020-05-12 19:49 Philippe Mathieu-Daudé
2020-05-14 20:21 ` John Snow
0 siblings, 1 reply; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-05-12 19:49 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, John Snow, qemu-block
Handlers don't need to modify the IDEDMA structure.
Make it const.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
include/hw/ide/internal.h | 12 ++++++------
hw/ide/ahci.c | 18 +++++++++---------
hw/ide/core.c | 6 +++---
hw/ide/macio.c | 6 +++---
hw/ide/pci.c | 12 ++++++------
5 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/include/hw/ide/internal.h b/include/hw/ide/internal.h
index 55da35d768..1a7869e85d 100644
--- a/include/hw/ide/internal.h
+++ b/include/hw/ide/internal.h
@@ -322,12 +322,12 @@ typedef enum { IDE_HD, IDE_CD, IDE_CFATA } IDEDriveKind;
typedef void EndTransferFunc(IDEState *);
-typedef void DMAStartFunc(IDEDMA *, IDEState *, BlockCompletionFunc *);
-typedef void DMAVoidFunc(IDEDMA *);
-typedef int DMAIntFunc(IDEDMA *, bool);
-typedef int32_t DMAInt32Func(IDEDMA *, int32_t len);
-typedef void DMAu32Func(IDEDMA *, uint32_t);
-typedef void DMAStopFunc(IDEDMA *, bool);
+typedef void DMAStartFunc(const IDEDMA *, IDEState *, BlockCompletionFunc *);
+typedef void DMAVoidFunc(const IDEDMA *);
+typedef int DMAIntFunc(const IDEDMA *, bool);
+typedef int32_t DMAInt32Func(const IDEDMA *, int32_t len);
+typedef void DMAu32Func(const IDEDMA *, uint32_t);
+typedef void DMAStopFunc(const IDEDMA *, bool);
struct unreported_events {
bool eject_request;
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 13d91e109a..168d34e9f2 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -44,7 +44,7 @@ static int handle_cmd(AHCIState *s, int port, uint8_t slot);
static void ahci_reset_port(AHCIState *s, int port);
static bool ahci_write_fis_d2h(AHCIDevice *ad);
static void ahci_init_d2h(AHCIDevice *ad);
-static int ahci_dma_prepare_buf(IDEDMA *dma, int32_t limit);
+static int ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit);
static bool ahci_map_clb_address(AHCIDevice *ad);
static bool ahci_map_fis_address(AHCIDevice *ad);
static void ahci_unmap_clb_address(AHCIDevice *ad);
@@ -1338,7 +1338,7 @@ out:
}
/* Transfer PIO data between RAM and device */
-static void ahci_pio_transfer(IDEDMA *dma)
+static void ahci_pio_transfer(const IDEDMA *dma)
{
AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
IDEState *s = &ad->port.ifs[0];
@@ -1397,7 +1397,7 @@ out:
}
}
-static void ahci_start_dma(IDEDMA *dma, IDEState *s,
+static void ahci_start_dma(const IDEDMA *dma, IDEState *s,
BlockCompletionFunc *dma_cb)
{
AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
@@ -1406,7 +1406,7 @@ static void ahci_start_dma(IDEDMA *dma, IDEState *s,
dma_cb(s, 0);
}
-static void ahci_restart_dma(IDEDMA *dma)
+static void ahci_restart_dma(const IDEDMA *dma)
{
/* Nothing to do, ahci_start_dma already resets s->io_buffer_offset. */
}
@@ -1415,7 +1415,7 @@ static void ahci_restart_dma(IDEDMA *dma)
* IDE/PIO restarts are handled by the core layer, but NCQ commands
* need an extra kick from the AHCI HBA.
*/
-static void ahci_restart(IDEDMA *dma)
+static void ahci_restart(const IDEDMA *dma)
{
AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
int i;
@@ -1432,7 +1432,7 @@ static void ahci_restart(IDEDMA *dma)
* Called in DMA and PIO R/W chains to read the PRDT.
* Not shared with NCQ pathways.
*/
-static int32_t ahci_dma_prepare_buf(IDEDMA *dma, int32_t limit)
+static int32_t ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit)
{
AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
IDEState *s = &ad->port.ifs[0];
@@ -1453,7 +1453,7 @@ static int32_t ahci_dma_prepare_buf(IDEDMA *dma, int32_t limit)
* Called via dma_buf_commit, for both DMA and PIO paths.
* sglist destruction is handled within dma_buf_commit.
*/
-static void ahci_commit_buf(IDEDMA *dma, uint32_t tx_bytes)
+static void ahci_commit_buf(const IDEDMA *dma, uint32_t tx_bytes)
{
AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
@@ -1461,7 +1461,7 @@ static void ahci_commit_buf(IDEDMA *dma, uint32_t tx_bytes)
ad->cur_cmd->status = cpu_to_le32(tx_bytes);
}
-static int ahci_dma_rw_buf(IDEDMA *dma, bool is_write)
+static int ahci_dma_rw_buf(const IDEDMA *dma, bool is_write)
{
AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
IDEState *s = &ad->port.ifs[0];
@@ -1486,7 +1486,7 @@ static int ahci_dma_rw_buf(IDEDMA *dma, bool is_write)
return 1;
}
-static void ahci_cmd_done(IDEDMA *dma)
+static void ahci_cmd_done(const IDEDMA *dma)
{
AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
diff --git a/hw/ide/core.c b/hw/ide/core.c
index 689bb36409..d997a78e47 100644
--- a/hw/ide/core.c
+++ b/hw/ide/core.c
@@ -2570,16 +2570,16 @@ static void ide_init1(IDEBus *bus, int unit)
ide_sector_write_timer_cb, s);
}
-static int ide_nop_int(IDEDMA *dma, bool is_write)
+static int ide_nop_int(const IDEDMA *dma, bool is_write)
{
return 0;
}
-static void ide_nop(IDEDMA *dma)
+static void ide_nop(const IDEDMA *dma)
{
}
-static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
+static int32_t ide_nop_int32(const IDEDMA *dma, int32_t l)
{
return 0;
}
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index a9f25e5d02..5b8098268d 100644
--- a/hw/ide/macio.c
+++ b/hw/ide/macio.c
@@ -376,17 +376,17 @@ static void macio_ide_reset(DeviceState *dev)
ide_bus_reset(&d->bus);
}
-static int ide_nop_int(IDEDMA *dma, bool is_write)
+static int ide_nop_int(const IDEDMA *dma, bool is_write)
{
return 0;
}
-static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
+static int32_t ide_nop_int32(const IDEDMA *dma, int32_t l)
{
return 0;
}
-static void ide_dbdma_start(IDEDMA *dma, IDEState *s,
+static void ide_dbdma_start(const IDEDMA *dma, IDEState *s,
BlockCompletionFunc *cb)
{
MACIOIDEState *m = container_of(dma, MACIOIDEState, dma);
diff --git a/hw/ide/pci.c b/hw/ide/pci.c
index 97347f07f1..5e85c4ad17 100644
--- a/hw/ide/pci.c
+++ b/hw/ide/pci.c
@@ -103,7 +103,7 @@ const MemoryRegionOps pci_ide_data_le_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static void bmdma_start_dma(IDEDMA *dma, IDEState *s,
+static void bmdma_start_dma(const IDEDMA *dma, IDEState *s,
BlockCompletionFunc *dma_cb)
{
BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
@@ -126,7 +126,7 @@ static void bmdma_start_dma(IDEDMA *dma, IDEState *s,
* IDEState.io_buffer_size will contain the number of bytes described
* by the PRDs, whether or not we added them to the sglist.
*/
-static int32_t bmdma_prepare_buf(IDEDMA *dma, int32_t limit)
+static int32_t bmdma_prepare_buf(const IDEDMA *dma, int32_t limit)
{
BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
IDEState *s = bmdma_active_if(bm);
@@ -181,7 +181,7 @@ static int32_t bmdma_prepare_buf(IDEDMA *dma, int32_t limit)
}
/* return 0 if buffer completed */
-static int bmdma_rw_buf(IDEDMA *dma, bool is_write)
+static int bmdma_rw_buf(const IDEDMA *dma, bool is_write)
{
BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
IDEState *s = bmdma_active_if(bm);
@@ -230,7 +230,7 @@ static int bmdma_rw_buf(IDEDMA *dma, bool is_write)
return 1;
}
-static void bmdma_set_inactive(IDEDMA *dma, bool more)
+static void bmdma_set_inactive(const IDEDMA *dma, bool more)
{
BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
@@ -242,7 +242,7 @@ static void bmdma_set_inactive(IDEDMA *dma, bool more)
}
}
-static void bmdma_restart_dma(IDEDMA *dma)
+static void bmdma_restart_dma(const IDEDMA *dma)
{
BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
@@ -257,7 +257,7 @@ static void bmdma_cancel(BMDMAState *bm)
}
}
-static void bmdma_reset(IDEDMA *dma)
+static void bmdma_reset(const IDEDMA *dma)
{
BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
--
2.21.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] hw/ide: Make IDEDMAOps handlers take a const IDEDMA pointer
2020-05-12 19:49 [PATCH] hw/ide: Make IDEDMAOps handlers take a const IDEDMA pointer Philippe Mathieu-Daudé
@ 2020-05-14 20:21 ` John Snow
2020-05-15 7:20 ` Philippe Mathieu-Daudé
2020-05-15 8:48 ` Kevin Wolf
0 siblings, 2 replies; 6+ messages in thread
From: John Snow @ 2020-05-14 20:21 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: qemu-block
On 5/12/20 3:49 PM, Philippe Mathieu-Daudé wrote:
> Handlers don't need to modify the IDEDMA structure.
> Make it const.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
I'll trust your judgment. As long as it still compiles and passes
qtests, I'm happy if you're happy.
Acked-by: John Snow <jsnow@redhat.com>
> ---
> include/hw/ide/internal.h | 12 ++++++------
> hw/ide/ahci.c | 18 +++++++++---------
> hw/ide/core.c | 6 +++---
> hw/ide/macio.c | 6 +++---
> hw/ide/pci.c | 12 ++++++------
> 5 files changed, 27 insertions(+), 27 deletions(-)
>
> diff --git a/include/hw/ide/internal.h b/include/hw/ide/internal.h
> index 55da35d768..1a7869e85d 100644
> --- a/include/hw/ide/internal.h
> +++ b/include/hw/ide/internal.h
> @@ -322,12 +322,12 @@ typedef enum { IDE_HD, IDE_CD, IDE_CFATA } IDEDriveKind;
>
> typedef void EndTransferFunc(IDEState *);
>
> -typedef void DMAStartFunc(IDEDMA *, IDEState *, BlockCompletionFunc *);
> -typedef void DMAVoidFunc(IDEDMA *);
> -typedef int DMAIntFunc(IDEDMA *, bool);
> -typedef int32_t DMAInt32Func(IDEDMA *, int32_t len);
> -typedef void DMAu32Func(IDEDMA *, uint32_t);
> -typedef void DMAStopFunc(IDEDMA *, bool);
> +typedef void DMAStartFunc(const IDEDMA *, IDEState *, BlockCompletionFunc *);
> +typedef void DMAVoidFunc(const IDEDMA *);
> +typedef int DMAIntFunc(const IDEDMA *, bool);
> +typedef int32_t DMAInt32Func(const IDEDMA *, int32_t len);
> +typedef void DMAu32Func(const IDEDMA *, uint32_t);
> +typedef void DMAStopFunc(const IDEDMA *, bool);
>
> struct unreported_events {
> bool eject_request;
> diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
> index 13d91e109a..168d34e9f2 100644
> --- a/hw/ide/ahci.c
> +++ b/hw/ide/ahci.c
> @@ -44,7 +44,7 @@ static int handle_cmd(AHCIState *s, int port, uint8_t slot);
> static void ahci_reset_port(AHCIState *s, int port);
> static bool ahci_write_fis_d2h(AHCIDevice *ad);
> static void ahci_init_d2h(AHCIDevice *ad);
> -static int ahci_dma_prepare_buf(IDEDMA *dma, int32_t limit);
> +static int ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit);
> static bool ahci_map_clb_address(AHCIDevice *ad);
> static bool ahci_map_fis_address(AHCIDevice *ad);
> static void ahci_unmap_clb_address(AHCIDevice *ad);
> @@ -1338,7 +1338,7 @@ out:
> }
>
> /* Transfer PIO data between RAM and device */
> -static void ahci_pio_transfer(IDEDMA *dma)
> +static void ahci_pio_transfer(const IDEDMA *dma)
> {
> AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
> IDEState *s = &ad->port.ifs[0];
> @@ -1397,7 +1397,7 @@ out:
> }
> }
>
> -static void ahci_start_dma(IDEDMA *dma, IDEState *s,
> +static void ahci_start_dma(const IDEDMA *dma, IDEState *s,
> BlockCompletionFunc *dma_cb)
> {
> AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
> @@ -1406,7 +1406,7 @@ static void ahci_start_dma(IDEDMA *dma, IDEState *s,
> dma_cb(s, 0);
> }
>
> -static void ahci_restart_dma(IDEDMA *dma)
> +static void ahci_restart_dma(const IDEDMA *dma)
> {
> /* Nothing to do, ahci_start_dma already resets s->io_buffer_offset. */
> }
> @@ -1415,7 +1415,7 @@ static void ahci_restart_dma(IDEDMA *dma)
> * IDE/PIO restarts are handled by the core layer, but NCQ commands
> * need an extra kick from the AHCI HBA.
> */
> -static void ahci_restart(IDEDMA *dma)
> +static void ahci_restart(const IDEDMA *dma)
> {
> AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
> int i;
> @@ -1432,7 +1432,7 @@ static void ahci_restart(IDEDMA *dma)
> * Called in DMA and PIO R/W chains to read the PRDT.
> * Not shared with NCQ pathways.
> */
> -static int32_t ahci_dma_prepare_buf(IDEDMA *dma, int32_t limit)
> +static int32_t ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit)
> {
> AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
> IDEState *s = &ad->port.ifs[0];
> @@ -1453,7 +1453,7 @@ static int32_t ahci_dma_prepare_buf(IDEDMA *dma, int32_t limit)
> * Called via dma_buf_commit, for both DMA and PIO paths.
> * sglist destruction is handled within dma_buf_commit.
> */
> -static void ahci_commit_buf(IDEDMA *dma, uint32_t tx_bytes)
> +static void ahci_commit_buf(const IDEDMA *dma, uint32_t tx_bytes)
> {
> AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
>
> @@ -1461,7 +1461,7 @@ static void ahci_commit_buf(IDEDMA *dma, uint32_t tx_bytes)
> ad->cur_cmd->status = cpu_to_le32(tx_bytes);
> }
>
> -static int ahci_dma_rw_buf(IDEDMA *dma, bool is_write)
> +static int ahci_dma_rw_buf(const IDEDMA *dma, bool is_write)
> {
> AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
> IDEState *s = &ad->port.ifs[0];
> @@ -1486,7 +1486,7 @@ static int ahci_dma_rw_buf(IDEDMA *dma, bool is_write)
> return 1;
> }
>
> -static void ahci_cmd_done(IDEDMA *dma)
> +static void ahci_cmd_done(const IDEDMA *dma)
> {
> AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
>
> diff --git a/hw/ide/core.c b/hw/ide/core.c
> index 689bb36409..d997a78e47 100644
> --- a/hw/ide/core.c
> +++ b/hw/ide/core.c
> @@ -2570,16 +2570,16 @@ static void ide_init1(IDEBus *bus, int unit)
> ide_sector_write_timer_cb, s);
> }
>
> -static int ide_nop_int(IDEDMA *dma, bool is_write)
> +static int ide_nop_int(const IDEDMA *dma, bool is_write)
> {
> return 0;
> }
>
> -static void ide_nop(IDEDMA *dma)
> +static void ide_nop(const IDEDMA *dma)
> {
> }
>
> -static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
> +static int32_t ide_nop_int32(const IDEDMA *dma, int32_t l)
> {
> return 0;
> }
> diff --git a/hw/ide/macio.c b/hw/ide/macio.c
> index a9f25e5d02..5b8098268d 100644
> --- a/hw/ide/macio.c
> +++ b/hw/ide/macio.c
> @@ -376,17 +376,17 @@ static void macio_ide_reset(DeviceState *dev)
> ide_bus_reset(&d->bus);
> }
>
> -static int ide_nop_int(IDEDMA *dma, bool is_write)
> +static int ide_nop_int(const IDEDMA *dma, bool is_write)
> {
> return 0;
> }
>
> -static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
> +static int32_t ide_nop_int32(const IDEDMA *dma, int32_t l)
> {
> return 0;
> }
>
> -static void ide_dbdma_start(IDEDMA *dma, IDEState *s,
> +static void ide_dbdma_start(const IDEDMA *dma, IDEState *s,
> BlockCompletionFunc *cb)
> {
> MACIOIDEState *m = container_of(dma, MACIOIDEState, dma);
> diff --git a/hw/ide/pci.c b/hw/ide/pci.c
> index 97347f07f1..5e85c4ad17 100644
> --- a/hw/ide/pci.c
> +++ b/hw/ide/pci.c
> @@ -103,7 +103,7 @@ const MemoryRegionOps pci_ide_data_le_ops = {
> .endianness = DEVICE_LITTLE_ENDIAN,
> };
>
> -static void bmdma_start_dma(IDEDMA *dma, IDEState *s,
> +static void bmdma_start_dma(const IDEDMA *dma, IDEState *s,
> BlockCompletionFunc *dma_cb)
> {
> BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
> @@ -126,7 +126,7 @@ static void bmdma_start_dma(IDEDMA *dma, IDEState *s,
> * IDEState.io_buffer_size will contain the number of bytes described
> * by the PRDs, whether or not we added them to the sglist.
> */
> -static int32_t bmdma_prepare_buf(IDEDMA *dma, int32_t limit)
> +static int32_t bmdma_prepare_buf(const IDEDMA *dma, int32_t limit)
> {
> BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
> IDEState *s = bmdma_active_if(bm);
> @@ -181,7 +181,7 @@ static int32_t bmdma_prepare_buf(IDEDMA *dma, int32_t limit)
> }
>
> /* return 0 if buffer completed */
> -static int bmdma_rw_buf(IDEDMA *dma, bool is_write)
> +static int bmdma_rw_buf(const IDEDMA *dma, bool is_write)
> {
> BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
> IDEState *s = bmdma_active_if(bm);
> @@ -230,7 +230,7 @@ static int bmdma_rw_buf(IDEDMA *dma, bool is_write)
> return 1;
> }
>
> -static void bmdma_set_inactive(IDEDMA *dma, bool more)
> +static void bmdma_set_inactive(const IDEDMA *dma, bool more)
> {
> BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
>
> @@ -242,7 +242,7 @@ static void bmdma_set_inactive(IDEDMA *dma, bool more)
> }
> }
>
> -static void bmdma_restart_dma(IDEDMA *dma)
> +static void bmdma_restart_dma(const IDEDMA *dma)
> {
> BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
>
> @@ -257,7 +257,7 @@ static void bmdma_cancel(BMDMAState *bm)
> }
> }
>
> -static void bmdma_reset(IDEDMA *dma)
> +static void bmdma_reset(const IDEDMA *dma)
> {
> BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] hw/ide: Make IDEDMAOps handlers take a const IDEDMA pointer
2020-05-14 20:21 ` John Snow
@ 2020-05-15 7:20 ` Philippe Mathieu-Daudé
2020-05-15 8:48 ` Kevin Wolf
1 sibling, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-05-15 7:20 UTC (permalink / raw)
To: John Snow, qemu-devel; +Cc: qemu-block
On 5/14/20 10:21 PM, John Snow wrote:
>
>
> On 5/12/20 3:49 PM, Philippe Mathieu-Daudé wrote:
>> Handlers don't need to modify the IDEDMA structure.
>> Make it const.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>
> I'll trust your judgment. As long as it still compiles and passes
> qtests, I'm happy if you're happy.
I guess "all data is modifyable until proven otherwise" is one of the
'defensive programming' rules.
https://wiki.sei.cmu.edu/confluence/display/c/DCL00-C.+Const-qualify+immutable+objects
"Immutable objects should be const-qualified. Enforcing object
immutability using const qualification helps ensure the correctness and
security of applications."
It is also a hint to static analyzer and compilers for optimization.
https://en.wikipedia.org/wiki/Const_(computer_programming)#Consequences
"A const parameter in pass-by-reference means that the referenced value
is not modified – it is part of the contract –"
>
> Acked-by: John Snow <jsnow@redhat.com>
Thanks!
>
>> ---
>> include/hw/ide/internal.h | 12 ++++++------
>> hw/ide/ahci.c | 18 +++++++++---------
>> hw/ide/core.c | 6 +++---
>> hw/ide/macio.c | 6 +++---
>> hw/ide/pci.c | 12 ++++++------
>> 5 files changed, 27 insertions(+), 27 deletions(-)
>>
>> diff --git a/include/hw/ide/internal.h b/include/hw/ide/internal.h
>> index 55da35d768..1a7869e85d 100644
>> --- a/include/hw/ide/internal.h
>> +++ b/include/hw/ide/internal.h
>> @@ -322,12 +322,12 @@ typedef enum { IDE_HD, IDE_CD, IDE_CFATA } IDEDriveKind;
>>
>> typedef void EndTransferFunc(IDEState *);
>>
>> -typedef void DMAStartFunc(IDEDMA *, IDEState *, BlockCompletionFunc *);
>> -typedef void DMAVoidFunc(IDEDMA *);
>> -typedef int DMAIntFunc(IDEDMA *, bool);
>> -typedef int32_t DMAInt32Func(IDEDMA *, int32_t len);
>> -typedef void DMAu32Func(IDEDMA *, uint32_t);
>> -typedef void DMAStopFunc(IDEDMA *, bool);
>> +typedef void DMAStartFunc(const IDEDMA *, IDEState *, BlockCompletionFunc *);
>> +typedef void DMAVoidFunc(const IDEDMA *);
>> +typedef int DMAIntFunc(const IDEDMA *, bool);
>> +typedef int32_t DMAInt32Func(const IDEDMA *, int32_t len);
>> +typedef void DMAu32Func(const IDEDMA *, uint32_t);
>> +typedef void DMAStopFunc(const IDEDMA *, bool);
>>
>> struct unreported_events {
>> bool eject_request;
>> diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
>> index 13d91e109a..168d34e9f2 100644
>> --- a/hw/ide/ahci.c
>> +++ b/hw/ide/ahci.c
>> @@ -44,7 +44,7 @@ static int handle_cmd(AHCIState *s, int port, uint8_t slot);
>> static void ahci_reset_port(AHCIState *s, int port);
>> static bool ahci_write_fis_d2h(AHCIDevice *ad);
>> static void ahci_init_d2h(AHCIDevice *ad);
>> -static int ahci_dma_prepare_buf(IDEDMA *dma, int32_t limit);
>> +static int ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit);
>> static bool ahci_map_clb_address(AHCIDevice *ad);
>> static bool ahci_map_fis_address(AHCIDevice *ad);
>> static void ahci_unmap_clb_address(AHCIDevice *ad);
>> @@ -1338,7 +1338,7 @@ out:
>> }
>>
>> /* Transfer PIO data between RAM and device */
>> -static void ahci_pio_transfer(IDEDMA *dma)
>> +static void ahci_pio_transfer(const IDEDMA *dma)
>> {
>> AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
>> IDEState *s = &ad->port.ifs[0];
>> @@ -1397,7 +1397,7 @@ out:
>> }
>> }
>>
>> -static void ahci_start_dma(IDEDMA *dma, IDEState *s,
>> +static void ahci_start_dma(const IDEDMA *dma, IDEState *s,
>> BlockCompletionFunc *dma_cb)
>> {
>> AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
>> @@ -1406,7 +1406,7 @@ static void ahci_start_dma(IDEDMA *dma, IDEState *s,
>> dma_cb(s, 0);
>> }
>>
>> -static void ahci_restart_dma(IDEDMA *dma)
>> +static void ahci_restart_dma(const IDEDMA *dma)
>> {
>> /* Nothing to do, ahci_start_dma already resets s->io_buffer_offset. */
>> }
>> @@ -1415,7 +1415,7 @@ static void ahci_restart_dma(IDEDMA *dma)
>> * IDE/PIO restarts are handled by the core layer, but NCQ commands
>> * need an extra kick from the AHCI HBA.
>> */
>> -static void ahci_restart(IDEDMA *dma)
>> +static void ahci_restart(const IDEDMA *dma)
>> {
>> AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
>> int i;
>> @@ -1432,7 +1432,7 @@ static void ahci_restart(IDEDMA *dma)
>> * Called in DMA and PIO R/W chains to read the PRDT.
>> * Not shared with NCQ pathways.
>> */
>> -static int32_t ahci_dma_prepare_buf(IDEDMA *dma, int32_t limit)
>> +static int32_t ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit)
>> {
>> AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
>> IDEState *s = &ad->port.ifs[0];
>> @@ -1453,7 +1453,7 @@ static int32_t ahci_dma_prepare_buf(IDEDMA *dma, int32_t limit)
>> * Called via dma_buf_commit, for both DMA and PIO paths.
>> * sglist destruction is handled within dma_buf_commit.
>> */
>> -static void ahci_commit_buf(IDEDMA *dma, uint32_t tx_bytes)
>> +static void ahci_commit_buf(const IDEDMA *dma, uint32_t tx_bytes)
>> {
>> AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
>>
>> @@ -1461,7 +1461,7 @@ static void ahci_commit_buf(IDEDMA *dma, uint32_t tx_bytes)
>> ad->cur_cmd->status = cpu_to_le32(tx_bytes);
>> }
>>
>> -static int ahci_dma_rw_buf(IDEDMA *dma, bool is_write)
>> +static int ahci_dma_rw_buf(const IDEDMA *dma, bool is_write)
>> {
>> AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
>> IDEState *s = &ad->port.ifs[0];
>> @@ -1486,7 +1486,7 @@ static int ahci_dma_rw_buf(IDEDMA *dma, bool is_write)
>> return 1;
>> }
>>
>> -static void ahci_cmd_done(IDEDMA *dma)
>> +static void ahci_cmd_done(const IDEDMA *dma)
>> {
>> AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
>>
>> diff --git a/hw/ide/core.c b/hw/ide/core.c
>> index 689bb36409..d997a78e47 100644
>> --- a/hw/ide/core.c
>> +++ b/hw/ide/core.c
>> @@ -2570,16 +2570,16 @@ static void ide_init1(IDEBus *bus, int unit)
>> ide_sector_write_timer_cb, s);
>> }
>>
>> -static int ide_nop_int(IDEDMA *dma, bool is_write)
>> +static int ide_nop_int(const IDEDMA *dma, bool is_write)
>> {
>> return 0;
>> }
>>
>> -static void ide_nop(IDEDMA *dma)
>> +static void ide_nop(const IDEDMA *dma)
>> {
>> }
>>
>> -static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
>> +static int32_t ide_nop_int32(const IDEDMA *dma, int32_t l)
>> {
>> return 0;
>> }
>> diff --git a/hw/ide/macio.c b/hw/ide/macio.c
>> index a9f25e5d02..5b8098268d 100644
>> --- a/hw/ide/macio.c
>> +++ b/hw/ide/macio.c
>> @@ -376,17 +376,17 @@ static void macio_ide_reset(DeviceState *dev)
>> ide_bus_reset(&d->bus);
>> }
>>
>> -static int ide_nop_int(IDEDMA *dma, bool is_write)
>> +static int ide_nop_int(const IDEDMA *dma, bool is_write)
>> {
>> return 0;
>> }
>>
>> -static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
>> +static int32_t ide_nop_int32(const IDEDMA *dma, int32_t l)
>> {
>> return 0;
>> }
>>
>> -static void ide_dbdma_start(IDEDMA *dma, IDEState *s,
>> +static void ide_dbdma_start(const IDEDMA *dma, IDEState *s,
>> BlockCompletionFunc *cb)
>> {
>> MACIOIDEState *m = container_of(dma, MACIOIDEState, dma);
>> diff --git a/hw/ide/pci.c b/hw/ide/pci.c
>> index 97347f07f1..5e85c4ad17 100644
>> --- a/hw/ide/pci.c
>> +++ b/hw/ide/pci.c
>> @@ -103,7 +103,7 @@ const MemoryRegionOps pci_ide_data_le_ops = {
>> .endianness = DEVICE_LITTLE_ENDIAN,
>> };
>>
>> -static void bmdma_start_dma(IDEDMA *dma, IDEState *s,
>> +static void bmdma_start_dma(const IDEDMA *dma, IDEState *s,
>> BlockCompletionFunc *dma_cb)
>> {
>> BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
>> @@ -126,7 +126,7 @@ static void bmdma_start_dma(IDEDMA *dma, IDEState *s,
>> * IDEState.io_buffer_size will contain the number of bytes described
>> * by the PRDs, whether or not we added them to the sglist.
>> */
>> -static int32_t bmdma_prepare_buf(IDEDMA *dma, int32_t limit)
>> +static int32_t bmdma_prepare_buf(const IDEDMA *dma, int32_t limit)
>> {
>> BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
>> IDEState *s = bmdma_active_if(bm);
>> @@ -181,7 +181,7 @@ static int32_t bmdma_prepare_buf(IDEDMA *dma, int32_t limit)
>> }
>>
>> /* return 0 if buffer completed */
>> -static int bmdma_rw_buf(IDEDMA *dma, bool is_write)
>> +static int bmdma_rw_buf(const IDEDMA *dma, bool is_write)
>> {
>> BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
>> IDEState *s = bmdma_active_if(bm);
>> @@ -230,7 +230,7 @@ static int bmdma_rw_buf(IDEDMA *dma, bool is_write)
>> return 1;
>> }
>>
>> -static void bmdma_set_inactive(IDEDMA *dma, bool more)
>> +static void bmdma_set_inactive(const IDEDMA *dma, bool more)
>> {
>> BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
>>
>> @@ -242,7 +242,7 @@ static void bmdma_set_inactive(IDEDMA *dma, bool more)
>> }
>> }
>>
>> -static void bmdma_restart_dma(IDEDMA *dma)
>> +static void bmdma_restart_dma(const IDEDMA *dma)
>> {
>> BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
>>
>> @@ -257,7 +257,7 @@ static void bmdma_cancel(BMDMAState *bm)
>> }
>> }
>>
>> -static void bmdma_reset(IDEDMA *dma)
>> +static void bmdma_reset(const IDEDMA *dma)
>> {
>> BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
>>
>>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] hw/ide: Make IDEDMAOps handlers take a const IDEDMA pointer
2020-05-14 20:21 ` John Snow
2020-05-15 7:20 ` Philippe Mathieu-Daudé
@ 2020-05-15 8:48 ` Kevin Wolf
2020-05-18 18:26 ` John Snow
1 sibling, 1 reply; 6+ messages in thread
From: Kevin Wolf @ 2020-05-15 8:48 UTC (permalink / raw)
To: John Snow; +Cc: Philippe Mathieu-Daudé, qemu-devel, qemu-block
Am 14.05.2020 um 22:21 hat John Snow geschrieben:
>
>
> On 5/12/20 3:49 PM, Philippe Mathieu-Daudé wrote:
> > Handlers don't need to modify the IDEDMA structure.
> > Make it const.
> >
> > Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>
> I'll trust your judgment. As long as it still compiles and passes
> qtests, I'm happy if you're happy.
>
> Acked-by: John Snow <jsnow@redhat.com>
Does this mean you assume someone else will merge it? If that someone is
me, please let me know.
Kevin
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] hw/ide: Make IDEDMAOps handlers take a const IDEDMA pointer
2020-05-15 8:48 ` Kevin Wolf
@ 2020-05-18 18:26 ` John Snow
2020-05-19 8:45 ` Kevin Wolf
0 siblings, 1 reply; 6+ messages in thread
From: John Snow @ 2020-05-18 18:26 UTC (permalink / raw)
To: Kevin Wolf; +Cc: Philippe Mathieu-Daudé, qemu-devel, qemu-block
On 5/15/20 4:48 AM, Kevin Wolf wrote:
> Am 14.05.2020 um 22:21 hat John Snow geschrieben:
>>
>>
>> On 5/12/20 3:49 PM, Philippe Mathieu-Daudé wrote:
>>> Handlers don't need to modify the IDEDMA structure.
>>> Make it const.
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>
>> I'll trust your judgment. As long as it still compiles and passes
>> qtests, I'm happy if you're happy.
>>
>> Acked-by: John Snow <jsnow@redhat.com>
>
> Does this mean you assume someone else will merge it? If that someone is
> me, please let me know.
>
> Kevin
>
I think I had thought this was part of a larger set, and didn't realize
it wasn't.
Yes, if you could please stage this for inclusion, that would be helpful.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] hw/ide: Make IDEDMAOps handlers take a const IDEDMA pointer
2020-05-18 18:26 ` John Snow
@ 2020-05-19 8:45 ` Kevin Wolf
0 siblings, 0 replies; 6+ messages in thread
From: Kevin Wolf @ 2020-05-19 8:45 UTC (permalink / raw)
To: John Snow; +Cc: Philippe Mathieu-Daudé, qemu-devel, qemu-block
Am 18.05.2020 um 20:26 hat John Snow geschrieben:
>
>
> On 5/15/20 4:48 AM, Kevin Wolf wrote:
> > Am 14.05.2020 um 22:21 hat John Snow geschrieben:
> >>
> >>
> >> On 5/12/20 3:49 PM, Philippe Mathieu-Daudé wrote:
> >>> Handlers don't need to modify the IDEDMA structure.
> >>> Make it const.
> >>>
> >>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> >>
> >> I'll trust your judgment. As long as it still compiles and passes
> >> qtests, I'm happy if you're happy.
> >>
> >> Acked-by: John Snow <jsnow@redhat.com>
> >
> > Does this mean you assume someone else will merge it? If that
> > someone is me, please let me know.
> >
> > Kevin
> >
>
> I think I had thought this was part of a larger set, and didn't
> realize it wasn't.
>
> Yes, if you could please stage this for inclusion, that would be
> helpful.
No problem, applied to the block branch.
Kevin
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-05-19 8:46 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-12 19:49 [PATCH] hw/ide: Make IDEDMAOps handlers take a const IDEDMA pointer Philippe Mathieu-Daudé
2020-05-14 20:21 ` John Snow
2020-05-15 7:20 ` Philippe Mathieu-Daudé
2020-05-15 8:48 ` Kevin Wolf
2020-05-18 18:26 ` John Snow
2020-05-19 8:45 ` Kevin Wolf
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