* [PATCH v2 0/6] DTS Sync from v6.5-rc1 to u-boot
@ 2023-08-25 11:16 Manorit Chawdhry
2023-08-25 11:16 ` [PATCH v2 1/6] configs: j721s2_evm_r5_defconfig: Increase malloc pool size in DRAM Manorit Chawdhry
` (5 more replies)
0 siblings, 6 replies; 20+ messages in thread
From: Manorit Chawdhry @ 2023-08-25 11:16 UTC (permalink / raw)
To: Tom Rini
Cc: u-boot, Nishanth Menon, Vignesh Raghavendra, Neha Malcom Francis,
Udit Kumar, Reid Tonking, Apurva Nandan, Andrew Davis,
Manorit Chawdhry, Nikhil M Jain
The sync tries to ensure that U-boot remains functional with the updated
Linux DTS and all the fixes from Linux move to U-boot during the sync.
The series tries to sync from Linux v6.5-rc1 along with addition of
the documentation for J721S2 that had been previously missing.
MCU Ringacc [0] and DMA fixes [1] are currently being upstreamed to Linux.
They'll be fixed in U-boot post their merge in Linux hopefully during
v6.6-rc1 timeframe.
Test Logs are included in [2]
[0]: https://lore.kernel.org/all/20230809175932.2553156-1-vigneshr@ti.com/
[1]: https://lore.kernel.org/all/20230810174356.3322583-1-vigneshr@ti.com/
[2]: https://gist.github.com/manorit2001/dbad09fd00e8b7c3872e85874c8e648c
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
---
Changes in v2:
- Add an additional patch required for booting the board after rebasing
to uboot-next
- Use v6.5-rc1 for the Sync and revert the changed done for -next
(Nishanth)
- Change <> to "" in #include and fix the order of includes(Nishanth)
- Remove duplicates among -u-boot.dtsi and -r5 dtsi files moving the
nodes to appropriate files (Nishanth)
- Remove fs_loader0 node (Nishanth)
- Remove /delete-property/ and add the dev-data and clk-data (Nishanth)
- Update documentation with better wordings (Nishanth)
- Added openocd section (Nishanth)
- Fix section numbering that was pointed out (Nishanth)
- Change to use explicit-targets for cross-referencing in documentation
(Nishanth)
- Propose myself as a Maintainer for J721S2 as a separate commit (Nishanth)
- Link to v1: https://lore.kernel.org/r/20230816-b4-upstream-j721s2-r5-pinmux-v1-0-f4548452760a@ti.com
---
Manorit Chawdhry (5):
arm: mach-k3: j721s2: Add mcu_timer0 id to the dev list
k3-j721s2: Sync from Linux tag v6.5-rc1
k3-am68: Sync from Linux tag v6.5-rc1
docs: ti: j721s2_evm: Create documentation from J7200 docs
board: ti: j721s2: MAINTAINERS: Update the MAINTAINERS File.
Udit Kumar (1):
configs: j721s2_evm_r5_defconfig: Increase malloc pool size in DRAM
arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi | 69 +--
arch/arm/dts/k3-am68-sk-base-board.dts | 389 ++++++++------
arch/arm/dts/k3-am68-sk-r5-base-board.dts | 143 +----
arch/arm/dts/k3-am68-sk-som.dtsi | 112 +---
.../dts/k3-j721s2-common-proc-board-u-boot.dtsi | 60 +--
arch/arm/dts/k3-j721s2-common-proc-board.dts | 330 ++++++------
arch/arm/dts/k3-j721s2-main.dtsi | 585 ++++++++++++++++++++-
arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi | 365 ++++++++++++-
arch/arm/dts/k3-j721s2-r5-common-proc-board.dts | 151 +-----
arch/arm/dts/k3-j721s2-som-p0.dtsi | 165 +++---
arch/arm/dts/k3-j721s2-thermal.dtsi | 101 ++++
arch/arm/dts/k3-j721s2.dtsi | 12 +-
arch/arm/mach-k3/j721s2/dev-data.c | 1 +
board/ti/j721s2/MAINTAINERS | 5 +-
configs/j721s2_evm_r5_defconfig | 1 +
doc/board/ti/j721s2_evm.rst | 263 +++++++++
doc/board/ti/k3.rst | 1 +
17 files changed, 1908 insertions(+), 845 deletions(-)
---
base-commit: 97841de680430e235f0954a188f245775cbbb962
change-id: 20230816-b4-upstream-j721s2-r5-pinmux-25c4cd61b258
Best regards,
--
Manorit Chawdhry <m-chawdhry@ti.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 1/6] configs: j721s2_evm_r5_defconfig: Increase malloc pool size in DRAM
2023-08-25 11:16 [PATCH v2 0/6] DTS Sync from v6.5-rc1 to u-boot Manorit Chawdhry
@ 2023-08-25 11:16 ` Manorit Chawdhry
2023-08-28 16:41 ` Nishanth Menon
2023-08-25 11:17 ` [PATCH v2 2/6] arm: mach-k3: j721s2: Add mcu_timer0 id to the dev list Manorit Chawdhry
` (4 subsequent siblings)
5 siblings, 1 reply; 20+ messages in thread
From: Manorit Chawdhry @ 2023-08-25 11:16 UTC (permalink / raw)
To: Tom Rini
Cc: u-boot, Nishanth Menon, Vignesh Raghavendra, Neha Malcom Francis,
Udit Kumar, Reid Tonking, Apurva Nandan, Andrew Davis,
Manorit Chawdhry, Nikhil M Jain
From: Udit Kumar <u-kumar1@ti.com>
The malloc capacity in DRAM at R5 SPL is set to 1MB which isn't
sufficient to load the new tispl.bin to
enable loading of tispl.bin the size is increased by 256KB to 1.25MB.
Cc: Nikhil M Jain <n-jain1@ti.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
---
configs/j721s2_evm_r5_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
index 1e66ac23d05b..e2b83b337809 100644
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@@ -42,6 +42,7 @@ CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x140000
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_SPL_MALLOC=y
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
--
2.41.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 2/6] arm: mach-k3: j721s2: Add mcu_timer0 id to the dev list
2023-08-25 11:16 [PATCH v2 0/6] DTS Sync from v6.5-rc1 to u-boot Manorit Chawdhry
2023-08-25 11:16 ` [PATCH v2 1/6] configs: j721s2_evm_r5_defconfig: Increase malloc pool size in DRAM Manorit Chawdhry
@ 2023-08-25 11:17 ` Manorit Chawdhry
2023-08-28 2:05 ` Neha Malcom Francis
2023-08-28 16:35 ` Nishanth Menon
2023-08-25 11:17 ` [PATCH v2 3/6] k3-j721s2: Sync from Linux tag v6.5-rc1 Manorit Chawdhry
` (3 subsequent siblings)
5 siblings, 2 replies; 20+ messages in thread
From: Manorit Chawdhry @ 2023-08-25 11:17 UTC (permalink / raw)
To: Tom Rini
Cc: u-boot, Nishanth Menon, Vignesh Raghavendra, Neha Malcom Francis,
Udit Kumar, Reid Tonking, Apurva Nandan, Andrew Davis,
Manorit Chawdhry
mcu_timer0 is used by u-boot as the tick-timer. Add it to the soc
devices lsit so it an be enabled via the k3 power controller.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
---
arch/arm/mach-k3/j721s2/dev-data.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-k3/j721s2/dev-data.c b/arch/arm/mach-k3/j721s2/dev-data.c
index 8c999a3c5a8b..df70c5e5d7c0 100644
--- a/arch/arm/mach-k3/j721s2/dev-data.c
+++ b/arch/arm/mach-k3/j721s2/dev-data.c
@@ -47,6 +47,7 @@ static struct ti_lpsc soc_lpsc_list[] = {
};
static struct ti_dev soc_dev_list[] = {
+ PSC_DEV(35, &soc_lpsc_list[0]),
PSC_DEV(108, &soc_lpsc_list[0]),
PSC_DEV(109, &soc_lpsc_list[0]),
PSC_DEV(110, &soc_lpsc_list[0]),
--
2.41.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 3/6] k3-j721s2: Sync from Linux tag v6.5-rc1
2023-08-25 11:16 [PATCH v2 0/6] DTS Sync from v6.5-rc1 to u-boot Manorit Chawdhry
2023-08-25 11:16 ` [PATCH v2 1/6] configs: j721s2_evm_r5_defconfig: Increase malloc pool size in DRAM Manorit Chawdhry
2023-08-25 11:17 ` [PATCH v2 2/6] arm: mach-k3: j721s2: Add mcu_timer0 id to the dev list Manorit Chawdhry
@ 2023-08-25 11:17 ` Manorit Chawdhry
2023-08-28 2:16 ` Neha Malcom Francis
` (2 more replies)
2023-08-25 11:17 ` [PATCH v2 4/6] k3-am68: " Manorit Chawdhry
` (2 subsequent siblings)
5 siblings, 3 replies; 20+ messages in thread
From: Manorit Chawdhry @ 2023-08-25 11:17 UTC (permalink / raw)
To: Tom Rini
Cc: u-boot, Nishanth Menon, Vignesh Raghavendra, Neha Malcom Francis,
Udit Kumar, Reid Tonking, Apurva Nandan, Andrew Davis,
Manorit Chawdhry
The following commit syncs the device tree from Linux tag
v6.5-rc1 to U-boot and fixes the following to be compatible with
the future syncs -
- Include k3-j721s2-common-proc-board.dts file
Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and
include k3-j721s2-common-proc-board.dts for Linux fixes to propagate
to U-boot.
- Fixing the mcu_timer0
Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi
The device manager is not functional at this point so we can't
configure the clocks for the mcu_timer0, delete the properties
that enable the clocks and power domains for it.
- Fixing secure proxy nodes
Linux DT now have these nodes defined so remove them and rename to
use the Linux DT ones.
- Remove cpsw node
The compatible is now fixed and the node is not required in
-u-boot specifically
- Remove aliases and chosen node
Use these from Linux and don't override when not required.
- Remove /delete-property/ from sdhci nodes
We have the necessary clock and dev data so remove these.
- Remove dummy_clocks and fs_loader0
These weren't being used anywhere so remove it.
All these have been put in a single commit to not break the
bisectability.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
---
.../dts/k3-j721s2-common-proc-board-u-boot.dtsi | 60 +--
arch/arm/dts/k3-j721s2-common-proc-board.dts | 330 ++++++------
arch/arm/dts/k3-j721s2-main.dtsi | 585 ++++++++++++++++++++-
arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi | 365 ++++++++++++-
arch/arm/dts/k3-j721s2-r5-common-proc-board.dts | 151 +-----
arch/arm/dts/k3-j721s2-som-p0.dtsi | 165 +++---
arch/arm/dts/k3-j721s2-thermal.dtsi | 101 ++++
arch/arm/dts/k3-j721s2.dtsi | 12 +-
8 files changed, 1339 insertions(+), 430 deletions(-)
diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
index f940ffee8787..faa01169ebd8 100644
--- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
@@ -1,28 +1,10 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-j721s2-binman.dtsi"
-/ {
- chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
- };
-
- aliases {
- serial0 = &wkup_uart0;
- serial1 = &mcu_uart0;
- serial2 = &main_uart8;
- i2c0 = &wkup_i2c0;
- i2c1 = &mcu_i2c0;
- i2c2 = &mcu_i2c1;
- i2c3 = &main_i2c0;
- ethernet0 = &cpsw_port1;
- };
-};
-
&wkup_i2c0 {
bootph-pre-ram;
};
@@ -38,14 +20,6 @@
&cbass_mcu_wakeup {
bootph-pre-ram;
- timer1: timer@40400000 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x40400000 0x0 0x80>;
- ti,timer-alwon;
- clock-frequency = <250000000>;
- bootph-pre-ram;
- };
-
chipid@43000014 {
bootph-pre-ram;
};
@@ -101,6 +75,10 @@
bootph-pre-ram;
};
+&main_usbss0_pins_default {
+ bootph-pre-ram;
+};
+
&wkup_pmx0 {
bootph-pre-ram;
};
@@ -129,23 +107,27 @@
bootph-pre-ram;
};
-&mcu_cpsw {
- reg = <0x0 0x46000000 0x0 0x200000>,
- <0x0 0x40f00200 0x0 0x8>;
- reg-names = "cpsw_nuss", "mac_efuse";
- /delete-property/ ranges;
+&main_sdhci0 {
+ bootph-pre-ram;
+};
- cpsw-phy-sel@40f04040 {
- compatible = "ti,am654-cpsw-phy-sel";
- reg= <0x0 0x40f04040 0x0 0x4>;
- reg-names = "gmii-sel";
- };
+&main_sdhci1 {
+ bootph-pre-ram;
};
-&main_sdhci0 {
+&ospi0 {
+ status = "disabled";
+};
+
+&ospi1 {
+ status = "disabled";
+};
+
+&usbss0 {
bootph-pre-ram;
};
-&main_sdhci1 {
+&usb0 {
+ dr_mode = "peripheral";
bootph-pre-ram;
};
diff --git a/arch/arm/dts/k3-j721s2-common-proc-board.dts b/arch/arm/dts/k3-j721s2-common-proc-board.dts
index 3bba6473a3b6..04d4739d7245 100644
--- a/arch/arm/dts/k3-j721s2-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721s2-common-proc-board.dts
@@ -2,13 +2,16 @@
/*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*
- * Link to Common Processor Board: https://www.ti.com/lit/zip/sprr439
+ * Common Processor Board: https://www.ti.com/tool/J721EXCPXEVM
*/
/dts-v1/;
#include "k3-j721s2-som-p0.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/mux/ti-serdes.h>
/ {
compatible = "ti,j721s2-evm", "ti,j721s2";
@@ -16,10 +19,10 @@
chosen {
stdout-path = "serial2:115200n8";
- bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x2880000";
};
aliases {
+ serial1 = &mcu_uart0;
serial2 = &main_uart8;
mmc0 = &main_sdhci0;
mmc1 = &main_sdhci1;
@@ -109,7 +112,7 @@
};
&main_pmx0 {
- main_uart8_pins_default: main-uart8-pins-default {
+ main_uart8_pins_default: main-uart8-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */
J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */
@@ -118,14 +121,14 @@
>;
};
- main_i2c3_pins_default: main-i2c3-pins-default {
+ main_i2c3_pins_default: main-i2c3-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x064, PIN_INPUT_PULLUP, 13) /* (W28) MCAN0_TX.I2C3_SCL */
J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */
>;
};
- main_mmc1_pins_default: main-mmc1-pins-default {
+ main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
@@ -138,62 +141,126 @@
>;
};
- vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
+ vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */
>;
};
+
+ main_usbss0_pins_default: main-usbss0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
+ >;
+ };
};
-&wkup_pmx0 {
- mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+&wkup_pmx2 {
+ wkup_uart0_pins_default: wkup-uart0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */
+ J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
+ J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
+ J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
+ >;
+ };
+
+ mcu_uart0_pins_default: mcu-uart0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */
+ J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */
+ J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
+ J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
+ >;
+ };
+
+ mcu_cpsw_pins_default: mcu-cpsw-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
+ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
+ J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
+ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
+ J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
+ J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
+ J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
+ J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
+ J721S2_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
+ J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
+ J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
+ J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
+ >;
+ };
+
+ mcu_mdio_pins_default: mcu-mdio-default-pins {
pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
- J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
- J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
- J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
- J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
- J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
- J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
- J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
- J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
- J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
- J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
- J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
+ J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
+ J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
>;
};
- mcu_mdio_pins_default: mcu-mdio-pins-default {
+ mcu_mcan0_pins_default: mcu-mcan0-default-pins {
pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
- J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
+ J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */
+ J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */
>;
};
- mcu_mcan0_pins_default: mcu-mcan0-pins-default {
+ mcu_mcan1_pins_default: mcu-mcan1-default-pins {
pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */
- J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */
+ J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
+ J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /*(C23) WKUP_GPIO0_4.MCU_MCAN1_TX */
>;
};
- mcu_mcan1_pins_default: mcu-mcan1-pins-default {
+ mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
- J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX */
+ J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */
+ J721S2_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */
>;
};
- mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default {
+ mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins {
pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x0c0, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */
- J721S2_WKUP_IOPAD(0x0a8, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */
+ J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */
>;
};
- mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default {
+ mcu_adc0_pins_default: mcu-adc0-default-pins {
pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */
+ J721S2_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (L25) MCU_ADC0_AIN0 */
+ J721S2_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN1 */
+ J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (M24) MCU_ADC0_AIN2 */
+ J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (L24) MCU_ADC0_AIN3 */
+ J721S2_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (L27) MCU_ADC0_AIN4 */
+ J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN5 */
+ J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (M27) MCU_ADC0_AIN6 */
+ J721S2_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (M26) MCU_ADC0_AIN7 */
+ >;
+ };
+
+ mcu_adc1_pins_default: mcu-adc1-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (P25) MCU_ADC1_AIN0 */
+ J721S2_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (R25) MCU_ADC1_AIN1 */
+ J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (P28) MCU_ADC1_AIN2 */
+ J721S2_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (P27) MCU_ADC1_AIN3 */
+ J721S2_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (N25) MCU_ADC1_AIN4 */
+ J721S2_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (P26) MCU_ADC1_AIN5 */
+ J721S2_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (N26) MCU_ADC1_AIN6 */
+ J721S2_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */
+ >;
+ };
+
+ mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */
+ J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */
+ J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */
+ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */
+ J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */
+ J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */
+ J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */
+ J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
+ J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
>;
};
};
@@ -216,51 +283,24 @@
&wkup_uart0 {
status = "reserved";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
};
-&main_uart0 {
- status = "disabled";
-};
-
-&main_uart1 {
- status = "disabled";
-};
-
-&main_uart2 {
- status = "disabled";
-};
-
-&main_uart3 {
- status = "disabled";
-};
-
-&main_uart4 {
- status = "disabled";
-};
-
-&main_uart5 {
- status = "disabled";
-};
-
-&main_uart6 {
- status = "disabled";
-};
-
-&main_uart7 {
- status = "disabled";
+&mcu_uart0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_uart0_pins_default>;
};
&main_uart8 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart8_pins_default>;
/* Shared with TFA on this platform */
power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
};
-&main_uart9 {
- status = "disabled";
-};
-
&main_i2c0 {
clock-frequency = <400000>;
@@ -290,30 +330,6 @@
};
};
-&main_i2c1 {
- status = "disabled";
-};
-
-&main_i2c2 {
- status = "disabled";
-};
-
-&main_i2c3 {
- status = "disabled";
-};
-
-&main_i2c4 {
- status = "disabled";
-};
-
-&main_i2c5 {
- status = "disabled";
-};
-
-&main_i2c6 {
- status = "disabled";
-};
-
&main_sdhci0 {
/* eMMC */
non-removable;
@@ -332,7 +348,7 @@
&mcu_cpsw {
pinctrl-names = "default";
- pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+ pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
};
&davinci_mdio {
@@ -349,82 +365,98 @@
phy-handle = <&phy0>;
};
-&mcu_mcan0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_mcan0_pins_default>;
- phys = <&transceiver1>;
-};
-
-&mcu_mcan1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_mcan1_pins_default>;
- phys = <&transceiver2>;
-};
-
-&main_mcan0 {
- status = "disabled";
-};
-
-&main_mcan1 {
- status = "disabled";
-};
-
-&main_mcan2 {
- status = "disabled";
-};
-
-&main_mcan3 {
- status = "disabled";
+&serdes_ln_ctrl {
+ idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>,
+ <J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>;
};
-&main_mcan4 {
- status = "disabled";
-};
-
-&main_mcan5 {
- status = "disabled";
+&serdes_refclk {
+ clock-frequency = <100000000>;
};
-&main_mcan6 {
- status = "disabled";
-};
-
-&main_mcan7 {
- status = "disabled";
+&serdes0 {
+ status = "okay";
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>;
+ };
};
-&main_mcan8 {
- status = "disabled";
+&usb_serdes_mux {
+ idle-states = <1>; /* USB0 to SERDES lane 1 */
};
-&main_mcan9 {
- status = "disabled";
+&usbss0 {
+ status = "okay";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ pinctrl-names = "default";
+ ti,vbus-divider;
+ ti,usb2-only;
};
-&main_mcan10 {
- status = "disabled";
+&usb0 {
+ dr_mode = "otg";
+ maximum-speed = "high-speed";
};
-&main_mcan11 {
- status = "disabled";
+&ospi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
+
+ flash@0{
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <40000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <2>;
+ };
};
-&main_mcan12 {
- status = "disabled";
+&pcie1_rc {
+ status = "okay";
+ reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
};
-&main_mcan13 {
- status = "disabled";
+&mcu_mcan0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan0_pins_default>;
+ phys = <&transceiver1>;
};
-&main_mcan14 {
- status = "disabled";
+&mcu_mcan1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan1_pins_default>;
+ phys = <&transceiver2>;
};
-&main_mcan15 {
- status = "disabled";
+&tscadc0 {
+ pinctrl-0 = <&mcu_adc0_pins_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5 6 7>;
+ };
};
-&main_mcan17 {
- status = "disabled";
+&tscadc1 {
+ pinctrl-0 = <&mcu_adc1_pins_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5 6 7>;
+ };
};
diff --git a/arch/arm/dts/k3-j721s2-main.dtsi b/arch/arm/dts/k3-j721s2-main.dtsi
index 976ba1e95aba..ed79ab3a3271 100644
--- a/arch/arm/dts/k3-j721s2-main.dtsi
+++ b/arch/arm/dts/k3-j721s2-main.dtsi
@@ -5,6 +5,17 @@
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy-ti.h>
+
+/ {
+ serdes_refclk: clock-cmnrefclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+};
+
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
@@ -26,6 +37,29 @@
};
};
+ scm_conf: syscon@104000 {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0x00 0x00104000 0x00 0x18000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x00104000 0x18000>;
+
+ usb_serdes_mux: mux-controller@0 {
+ compatible = "mmio-mux";
+ reg = <0x0 0x4>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
+ };
+
+ serdes_ln_ctrl: mux-controller@80 {
+ compatible = "mmio-mux";
+ reg = <0x80 0x10>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
+ <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
+ };
+ };
+
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
@@ -33,8 +67,11 @@
ranges;
#interrupt-cells = <3>;
interrupt-controller;
- reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */
- <0x00 0x01900000 0x00 0x100000>; /* GICR */
+ reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */
+ <0x00 0x01900000 0x00 0x100000>, /* GICR */
+ <0x00 0x6f000000 0x00 0x2000>, /* GICC */
+ <0x00 0x6f010000 0x00 0x1000>, /* GICH */
+ <0x00 0x6f020000 0x00 0x2000>; /* GICV */
/* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
@@ -57,7 +94,7 @@
#interrupt-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <148>;
- ti,interrupt-ranges = <8 360 56>;
+ ti,interrupt-ranges = <8 392 56>;
};
main_pmx0: pinctrl@11c000 {
@@ -69,6 +106,283 @@
pinctrl-single,function-mask = <0xffffffff>;
};
+ /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
+ main_timerio_input: pinctrl@104200 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x104200 0x00 0x50>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x00000007>;
+ };
+
+ /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
+ main_timerio_output: pinctrl@104280 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x104280 0x00 0x20>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000001f>;
+ };
+
+ main_crypto: crypto@4e00000 {
+ compatible = "ti,j721e-sa2ul";
+ reg = <0x00 0x04e00000 0x00 0x1200>;
+ power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
+
+ dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
+ <&main_udmap 0x4a41>;
+ dma-names = "tx", "rx1", "rx2";
+
+ rng: rng@4e10000 {
+ compatible = "inside-secure,safexcel-eip76";
+ reg = <0x00 0x04e10000 0x00 0x7d>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ main_timer0: timer@2400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2400000 0x00 0x400>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 63 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 63 1>;
+ assigned-clock-parents = <&k3_clks 63 2>;
+ power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer1: timer@2410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2410000 0x00 0x400>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 64 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 64 1>;
+ assigned-clock-parents = <&k3_clks 64 2>;
+ power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer2: timer@2420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2420000 0x00 0x400>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 65 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 65 1>;
+ assigned-clock-parents = <&k3_clks 65 2>;
+ power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer3: timer@2430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2430000 0x00 0x400>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 66 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 66 1>;
+ assigned-clock-parents = <&k3_clks 66 2>;
+ power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer4: timer@2440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2440000 0x00 0x400>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 67 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 67 1>;
+ assigned-clock-parents = <&k3_clks 67 2>;
+ power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer5: timer@2450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2450000 0x00 0x400>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 68 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 68 1>;
+ assigned-clock-parents = <&k3_clks 68 2>;
+ power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer6: timer@2460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2460000 0x00 0x400>;
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 69 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 69 1>;
+ assigned-clock-parents = <&k3_clks 69 2>;
+ power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer7: timer@2470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2470000 0x00 0x400>;
+ interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 70 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 70 1>;
+ assigned-clock-parents = <&k3_clks 70 2>;
+ power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer8: timer@2480000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2480000 0x00 0x400>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 71 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 71 1>;
+ assigned-clock-parents = <&k3_clks 71 2>;
+ power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer9: timer@2490000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2490000 0x00 0x400>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 72 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 72 1>;
+ assigned-clock-parents = <&k3_clks 72 2>;
+ power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer10: timer@24a0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24a0000 0x00 0x400>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 73 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 73 1>;
+ assigned-clock-parents = <&k3_clks 73 2>;
+ power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer11: timer@24b0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24b0000 0x00 0x400>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 74 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 74 1>;
+ assigned-clock-parents = <&k3_clks 74 2>;
+ power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer12: timer@24c0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24c0000 0x00 0x400>;
+ interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 75 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 75 1>;
+ assigned-clock-parents = <&k3_clks 75 2>;
+ power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer13: timer@24d0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24d0000 0x00 0x400>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 76 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 76 1>;
+ assigned-clock-parents = <&k3_clks 76 2>;
+ power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer14: timer@24e0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24e0000 0x00 0x400>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 77 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 77 1>;
+ assigned-clock-parents = <&k3_clks 77 2>;
+ power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer15: timer@24f0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24f0000 0x00 0x400>;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 78 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 78 1>;
+ assigned-clock-parents = <&k3_clks 78 2>;
+ power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer16: timer@2500000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2500000 0x00 0x400>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 79 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 79 1>;
+ assigned-clock-parents = <&k3_clks 79 2>;
+ power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer17: timer@2510000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2510000 0x00 0x400>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 80 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 80 1>;
+ assigned-clock-parents = <&k3_clks 80 2>;
+ power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer18: timer@2520000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2520000 0x00 0x400>;
+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 81 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 81 1>;
+ assigned-clock-parents = <&k3_clks 81 2>;
+ power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer19: timer@2530000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2530000 0x00 0x400>;
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 82 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 82 1>;
+ assigned-clock-parents = <&k3_clks 82 2>;
+ power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x200>;
@@ -77,6 +391,7 @@
clocks = <&k3_clks 146 3>;
clock-names = "fclk";
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart1: serial@2810000 {
@@ -87,6 +402,7 @@
clocks = <&k3_clks 350 3>;
clock-names = "fclk";
power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart2: serial@2820000 {
@@ -97,6 +413,7 @@
clocks = <&k3_clks 351 3>;
clock-names = "fclk";
power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart3: serial@2830000 {
@@ -107,6 +424,7 @@
clocks = <&k3_clks 352 3>;
clock-names = "fclk";
power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart4: serial@2840000 {
@@ -117,6 +435,7 @@
clocks = <&k3_clks 353 3>;
clock-names = "fclk";
power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart5: serial@2850000 {
@@ -127,6 +446,7 @@
clocks = <&k3_clks 354 3>;
clock-names = "fclk";
power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart6: serial@2860000 {
@@ -137,6 +457,7 @@
clocks = <&k3_clks 355 3>;
clock-names = "fclk";
power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart7: serial@2870000 {
@@ -147,6 +468,7 @@
clocks = <&k3_clks 356 3>;
clock-names = "fclk";
power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart8: serial@2880000 {
@@ -157,6 +479,7 @@
clocks = <&k3_clks 357 3>;
clock-names = "fclk";
power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart9: serial@2890000 {
@@ -167,6 +490,7 @@
clocks = <&k3_clks 358 3>;
clock-names = "fclk";
power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_gpio0: gpio@600000 {
@@ -253,6 +577,7 @@
clocks = <&k3_clks 215 1>;
clock-names = "fck";
power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c2: i2c@2020000 {
@@ -264,6 +589,7 @@
clocks = <&k3_clks 216 1>;
clock-names = "fck";
power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c3: i2c@2030000 {
@@ -275,6 +601,7 @@
clocks = <&k3_clks 217 1>;
clock-names = "fck";
power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c4: i2c@2040000 {
@@ -286,6 +613,7 @@
clocks = <&k3_clks 218 1>;
clock-names = "fck";
power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c5: i2c@2050000 {
@@ -297,6 +625,7 @@
clocks = <&k3_clks 219 1>;
clock-names = "fck";
power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c6: i2c@2060000 {
@@ -308,6 +637,7 @@
clocks = <&k3_clks 220 1>;
clock-names = "fck";
power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_sdhci0: mmc@4f80000 {
@@ -317,7 +647,7 @@
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 98 7>, <&k3_clks 98 1>;
- clock-names = "clk_ahb", "clk_xin";
+ clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&k3_clks 98 1>;
assigned-clock-parents = <&k3_clks 98 2>;
bus-width = <8>;
@@ -344,7 +674,7 @@
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 99 8>, <&k3_clks 99 1>;
- clock-names = "clk_ahb", "clk_xin";
+ clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&k3_clks 99 1>;
assigned-clock-parents = <&k3_clks 99 2>;
bus-width = <4>;
@@ -363,7 +693,7 @@
ti,trm-icp = <0x8>;
dma-coherent;
/* Masking support for SDR104 capability */
- // sdhci-caps-mask = <0x00000003 0x00000000>;
+ sdhci-caps-mask = <0x00000003 0x00000000>;
};
main_navss: bus@30000000 {
@@ -425,6 +755,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster1: mailbox@31f81000 {
@@ -434,6 +765,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster2: mailbox@31f82000 {
@@ -443,6 +775,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster3: mailbox@31f83000 {
@@ -452,6 +785,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster4: mailbox@31f84000 {
@@ -461,6 +795,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster5: mailbox@31f85000 {
@@ -470,6 +805,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster6: mailbox@31f86000 {
@@ -479,6 +815,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster7: mailbox@31f87000 {
@@ -488,6 +825,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster8: mailbox@31f88000 {
@@ -497,6 +835,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster9: mailbox@31f89000 {
@@ -506,6 +845,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster10: mailbox@31f8a000 {
@@ -515,6 +855,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster11: mailbox@31f8b000 {
@@ -524,6 +865,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster0: mailbox@31f90000 {
@@ -533,6 +875,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster1: mailbox@31f91000 {
@@ -542,6 +885,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster2: mailbox@31f92000 {
@@ -551,6 +895,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster3: mailbox@31f93000 {
@@ -560,6 +905,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster4: mailbox@31f94000 {
@@ -569,6 +915,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster5: mailbox@31f95000 {
@@ -578,6 +925,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster6: mailbox@31f96000 {
@@ -587,6 +935,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster7: mailbox@31f97000 {
@@ -596,6 +945,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster8: mailbox@31f98000 {
@@ -605,6 +955,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster9: mailbox@31f99000 {
@@ -614,6 +965,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster10: mailbox@31f9a000 {
@@ -623,6 +975,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster11: mailbox@31f9b000 {
@@ -632,6 +985,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
main_ringacc: ringacc@3c000000 {
@@ -676,6 +1030,8 @@
reg-names = "cpts";
clocks = <&k3_clks 226 5>;
clock-names = "cpts";
+ assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */
+ assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */
interrupts-extended = <&main_navss_intr 391>;
interrupt-names = "cpts";
ti,cpts-periodic-outputs = <6>;
@@ -683,6 +1039,117 @@
};
};
+ usbss0: cdns-usb@4104000 {
+ compatible = "ti,j721e-usb";
+ reg = <0x00 0x04104000 0x00 0x100>;
+ clocks = <&k3_clks 360 16>, <&k3_clks 360 15>;
+ clock-names = "ref", "lpm";
+ assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
+ assigned-clock-parents = <&k3_clks 360 17>;
+ power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-coherent;
+
+ status = "disabled"; /* Needs pinmux */
+
+ usb0: usb@6000000 {
+ compatible = "cdns,usb3";
+ reg = <0x00 0x06000000 0x00 0x10000>,
+ <0x00 0x06010000 0x00 0x10000>,
+ <0x00 0x06020000 0x00 0x10000>;
+ reg-names = "otg", "xhci", "dev";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host", "peripheral", "otg";
+ maximum-speed = "super-speed";
+ dr_mode = "otg";
+ };
+ };
+
+ serdes_wiz0: wiz@5060000 {
+ compatible = "ti,j721s2-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x5060000 0x0 0x5060000 0x10000>;
+
+ assigned-clocks = <&k3_clks 365 3>;
+ assigned-clock-parents = <&k3_clks 365 7>;
+
+ serdes0: serdes@5060000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05060000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 365 3>,
+ <&k3_clks 365 3>,
+ <&k3_clks 365 3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled"; /* Needs lane config */
+ };
+ };
+
+ pcie1_rc: pcie@2910000 {
+ compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x800000>,
+ <0x00 0x18000000 0x00 0x1000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 276 41>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x104c>;
+ device-id = <0xb013>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
+ <0 0 0 2 &pcie1_intc 0>, /* INT B */
+ <0 0 0 3 &pcie1_intc 0>, /* INT C */
+ <0 0 0 4 &pcie1_intc 0>; /* INT D */
+
+ status = "disabled"; /* Needs gpio and serdes info */
+
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
@@ -695,6 +1162,7 @@
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan1: can@2711000 {
@@ -709,6 +1177,7 @@
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan2: can@2721000 {
@@ -723,6 +1192,7 @@
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan3: can@2731000 {
@@ -737,6 +1207,7 @@
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan4: can@2741000 {
@@ -751,6 +1222,7 @@
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan5: can@2751000 {
@@ -765,6 +1237,7 @@
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan6: can@2761000 {
@@ -779,6 +1252,7 @@
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan7: can@2771000 {
@@ -793,6 +1267,7 @@
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan8: can@2781000 {
@@ -807,6 +1282,7 @@
<GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan9: can@2791000 {
@@ -821,6 +1297,7 @@
<GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan10: can@27a1000 {
@@ -835,6 +1312,7 @@
<GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan11: can@27b1000 {
@@ -849,6 +1327,7 @@
<GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan12: can@27c1000 {
@@ -863,6 +1342,7 @@
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan13: can@27d1000 {
@@ -877,6 +1357,7 @@
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan14: can@2681000 {
@@ -891,6 +1372,7 @@
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan15: can@2691000 {
@@ -905,6 +1387,7 @@
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan16: can@26a1000 {
@@ -919,6 +1402,7 @@
<GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan17: can@26b1000 {
@@ -933,5 +1417,94 @@
<GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_spi0: spi@2100000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02100000 0x00 0x400>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 339 1>;
+ status = "disabled";
+ };
+
+ main_spi1: spi@2110000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02110000 0x00 0x400>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 340 1>;
+ status = "disabled";
+ };
+
+ main_spi2: spi@2120000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02120000 0x00 0x400>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 341 1>;
+ status = "disabled";
+ };
+
+ main_spi3: spi@2130000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02130000 0x00 0x400>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 342 1>;
+ status = "disabled";
+ };
+
+ main_spi4: spi@2140000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02140000 0x00 0x400>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 343 1>;
+ status = "disabled";
+ };
+
+ main_spi5: spi@2150000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02150000 0x00 0x400>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 344 1>;
+ status = "disabled";
+ };
+
+ main_spi6: spi@2160000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02160000 0x00 0x400>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 345 1>;
+ status = "disabled";
+ };
+
+ main_spi7: spi@2170000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02170000 0x00 0x400>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 346 1>;
+ status = "disabled";
};
};
diff --git a/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
index 7521963719ff..e7dd947a1814 100644
--- a/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
@@ -12,8 +12,8 @@
mbox-names = "rx", "tx";
- mboxes= <&secure_proxy_main 11>,
- <&secure_proxy_main 13>;
+ mboxes = <&secure_proxy_main 11>,
+ <&secure_proxy_main 13>;
reg-names = "debug_messages";
reg = <0x00 0x44083000 0x00 0x1000>;
@@ -39,6 +39,21 @@
reg = <0x00 0x43000014 0x00 0x4>;
};
+ secure_proxy_sa3: mailbox@43600000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x43600000 0x00 0x10000>,
+ <0x00 0x44880000 0x00 0x20000>,
+ <0x00 0x44860000 0x00 0x20000>;
+ /*
+ * Marked Disabled:
+ * Node is incomplete as it is meant for bootloaders and
+ * firmware on non-MPU processors
+ */
+ status = "disabled";
+ };
+
mcu_ram: sram@41c00000 {
compatible = "mmio-sram";
reg = <0x00 0x41c00000 0x00 0x100000>;
@@ -50,12 +65,61 @@
wkup_pmx0: pinctrl@4301c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
- reg = <0x00 0x4301c000 0x00 0x178>;
+ reg = <0x00 0x4301c000 0x00 0x034>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
+ wkup_pmx1: pinctrl@4301c038 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x00 0x4301c038 0x00 0x02C>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ wkup_pmx2: pinctrl@4301c068 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x00 0x4301c068 0x00 0x120>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ wkup_pmx3: pinctrl@4301c190 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x00 0x4301c190 0x00 0x004>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
+ mcu_timerio_input: pinctrl@40f04200 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x40f04200 0x00 0x28>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
+ mcu_timerio_output: pinctrl@40f04280 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x40f04280 0x00 0x28>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
wkup_gpio_intr: interrupt-controller@42200000 {
compatible = "ti,sci-intr";
reg = <0x00 0x42200000 0x00 0x400>;
@@ -65,7 +129,7 @@
#interrupt-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <125>;
- ti,interrupt-ranges = <16 928 16>;
+ ti,interrupt-ranges = <16 960 16>;
};
mcu_conf: syscon@40f00000 {
@@ -83,6 +147,146 @@
};
+ mcu_timer0: timer@40400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40400000 0x00 0x400>;
+ interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 35 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 35 1>;
+ assigned-clock-parents = <&k3_clks 35 2>;
+ power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer1: timer@40410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40410000 0x00 0x400>;
+ interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 83 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 83 1>;
+ assigned-clock-parents = <&k3_clks 83 2>;
+ power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer2: timer@40420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40420000 0x00 0x400>;
+ interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 84 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 84 1>;
+ assigned-clock-parents = <&k3_clks 84 2>;
+ power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer3: timer@40430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40430000 0x00 0x400>;
+ interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 85 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 85 1>;
+ assigned-clock-parents = <&k3_clks 85 2>;
+ power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer4: timer@40440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40440000 0x00 0x400>;
+ interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 86 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 86 1>;
+ assigned-clock-parents = <&k3_clks 86 2>;
+ power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer5: timer@40450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40450000 0x00 0x400>;
+ interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 87 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 87 1>;
+ assigned-clock-parents = <&k3_clks 87 2>;
+ power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer6: timer@40460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40460000 0x00 0x400>;
+ interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 88 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 88 1>;
+ assigned-clock-parents = <&k3_clks 88 2>;
+ power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer7: timer@40470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40470000 0x00 0x400>;
+ interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 89 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 89 1>;
+ assigned-clock-parents = <&k3_clks 89 2>;
+ power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer8: timer@40480000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40480000 0x00 0x400>;
+ interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 90 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 90 1>;
+ assigned-clock-parents = <&k3_clks 90 2>;
+ power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
+ mcu_timer9: timer@40490000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40490000 0x00 0x400>;
+ interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 91 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 91 1>;
+ assigned-clock-parents = <&k3_clks 91 2>;
+ power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ /* Non-MPU Firmware usage */
+ status = "reserved";
+ };
+
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x200>;
@@ -91,6 +295,7 @@
clocks = <&k3_clks 359 3>;
clock-names = "fclk";
power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_uart0: serial@40a00000 {
@@ -101,6 +306,7 @@
clocks = <&k3_clks 149 3>;
clock-names = "fclk";
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
wkup_gpio0: gpio@42110000 {
@@ -108,7 +314,7 @@
reg = <0x00 0x42110000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
+ interrupt-parent = <&wkup_gpio_intr>;
interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -124,7 +330,7 @@
reg = <0x00 0x42100000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
+ interrupt-parent = <&wkup_gpio_intr>;
interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -144,6 +350,7 @@
clocks = <&k3_clks 223 1>;
clock-names = "fck";
power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_i2c0: i2c@40b00000 {
@@ -155,6 +362,7 @@
clocks = <&k3_clks 221 1>;
clock-names = "fck";
power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_i2c1: i2c@40b10000 {
@@ -166,6 +374,7 @@
clocks = <&k3_clks 222 1>;
clock-names = "fck";
power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_mcan0: can@40528000 {
@@ -180,6 +389,7 @@
<GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
mcu_mcan1: can@40568000 {
@@ -194,6 +404,40 @@
<GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ mcu_spi0: spi@40300000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040300000 0x00 0x400>;
+ interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 347 0>;
+ status = "disabled";
+ };
+
+ mcu_spi1: spi@40310000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040310000 0x00 0x400>;
+ interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 348 0>;
+ status = "disabled";
+ };
+
+ mcu_spi2: spi@40320000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040320000 0x00 0x400>;
+ interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 349 0>;
+ status = "disabled";
};
mcu_navss: bus@28380000{
@@ -240,6 +484,21 @@
};
};
+ secure_proxy_mcu: mailbox@2a480000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x2a480000 0x00 0x80000>,
+ <0x00 0x2a380000 0x00 0x80000>,
+ <0x00 0x2a400000 0x00 0x80000>;
+ /*
+ * Marked Disabled:
+ * Node is incomplete as it is meant for bootloaders and
+ * firmware on non-MPU processors
+ */
+ status = "disabled";
+ };
+
mcu_cpsw: ethernet@46000000 {
compatible = "ti,j721e-cpsw-nuss";
#address-cells = <2>;
@@ -293,10 +552,104 @@
reg = <0x0 0x3d000 0x0 0x400>;
clocks = <&k3_clks 29 3>;
clock-names = "cpts";
+ assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */
+ assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */
interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cpts";
ti,cpts-ext-ts-inputs = <4>;
ti,cpts-periodic-outputs = <2>;
};
};
+
+ tscadc0: tscadc@40200000 {
+ compatible = "ti,am3359-tscadc";
+ reg = <0x00 0x40200000 0x00 0x1000>;
+ interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 0 0>;
+ assigned-clocks = <&k3_clks 0 2>;
+ assigned-clock-rates = <60000000>;
+ clock-names = "fck";
+ dmas = <&main_udmap 0x7400>,
+ <&main_udmap 0x7401>;
+ dma-names = "fifo0", "fifo1";
+ status = "disabled";
+
+ adc {
+ #io-channel-cells = <1>;
+ compatible = "ti,am3359-adc";
+ };
+ };
+
+ tscadc1: tscadc@40210000 {
+ compatible = "ti,am3359-tscadc";
+ reg = <0x00 0x40210000 0x00 0x1000>;
+ interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 1 0>;
+ assigned-clocks = <&k3_clks 1 2>;
+ assigned-clock-rates = <60000000>;
+ clock-names = "fck";
+ dmas = <&main_udmap 0x7402>,
+ <&main_udmap 0x7403>;
+ dma-names = "fifo0", "fifo1";
+ status = "disabled";
+
+ adc {
+ #io-channel-cells = <1>;
+ compatible = "ti,am3359-adc";
+ };
+ };
+
+ fss: bus@47000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
+ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
+
+ ospi0: spi@47040000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x47040000 0x00 0x100>,
+ <0x05 0x00000000 0x01 0x00000000>;
+ interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 109 5>;
+ assigned-clocks = <&k3_clks 109 5>;
+ assigned-clock-parents = <&k3_clks 109 7>;
+ assigned-clock-rates = <166666666>;
+ power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled"; /* Needs pinmux */
+ };
+
+ ospi1: spi@47050000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x47050000 0x00 0x100>,
+ <0x07 0x00000000 0x01 0x00000000>;
+ interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 110 5>;
+ power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled"; /* Needs pinmux */
+ };
+ };
+
+ wkup_vtm0: temperature-sensor@42040000 {
+ compatible = "ti,j7200-vtm";
+ reg = <0x00 0x42040000 0x0 0x350>,
+ <0x00 0x42050000 0x0 0x350>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>;
+ #thermal-sensor-cells = <1>;
+ };
};
diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
index c74e8e58ae81..022618b37c74 100644
--- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
@@ -1,20 +1,19 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-#include "k3-j721s2-som-p0.dtsi"
+#include "k3-j721s2-common-proc-board.dts"
#include "k3-j721s2-ddr-evm-lp4-4266.dtsi"
#include "k3-j721s2-ddr.dtsi"
-#include "k3-j721s2-binman.dtsi"
+#include "k3-j721s2-common-proc-board-u-boot.dtsi"
/ {
chosen {
- firmware-loader = &fs_loader0;
stdout-path = &main_uart8;
- tick-timer = &timer1;
+ tick-timer = &mcu_timer0;
};
aliases {
@@ -22,11 +21,6 @@
remoteproc1 = &a72_0;
};
- fs_loader0: fs_loader@0 {
- compatible = "u-boot,fs-loader";
- bootph-all;
- };
-
a72_0: a72@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
@@ -43,46 +37,27 @@
ti,sci-host-id = <10>;
bootph-pre-ram;
};
+};
- clk_200mhz: dummy_clock_200mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- bootph-pre-ram;
- };
-
- clk_19_2mhz: dummy_clock_19_2mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <19200000>;
+&mcu_timer0 {
+ clock-frequency = <250000000>;
bootph-pre-ram;
- };
};
-&cbass_mcu_wakeup {
- sa3_secproxy: secproxy@44880000 {
- bootph-pre-ram;
- compatible = "ti,am654-secure-proxy";
- reg = <0x0 0x44880000 0x0 0x20000>,
- <0x0 0x44860000 0x0 0x20000>,
- <0x0 0x43600000 0x0 0x10000>;
- reg-names = "rt", "scfg", "target_data";
- #mbox-cells = <1>;
- };
+&secure_proxy_sa3 {
+ bootph-pre-ram;
+ status = "okay";
+};
- mcu_secproxy: secproxy@2a380000 {
- compatible = "ti,am654-secure-proxy";
- reg = <0x0 0x2a380000 0x0 0x80000>,
- <0x0 0x2a400000 0x0 0x80000>,
- <0x0 0x2a480000 0x0 0x80000>;
- reg-names = "rt", "scfg", "target_data";
- #mbox-cells = <1>;
- bootph-pre-ram;
- };
+&secure_proxy_mcu {
+ bootph-pre-ram;
+ status = "okay";
+};
+&cbass_mcu_wakeup {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
- mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>, <&sa3_secproxy 5>;
+ mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
@@ -92,101 +67,17 @@
ti,host-id = <3>;
ti,secure-host;
mbox-names = "rx", "tx";
- mboxes= <&mcu_secproxy 21>,
- <&mcu_secproxy 23>;
+ mboxes= <&secure_proxy_mcu 21>,
+ <&secure_proxy_mcu 23>;
bootph-pre-ram;
};
};
-&main_pmx0 {
- main_uart8_pins_default: main-uart8-pins-default {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */
- J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */
- J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
- J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
- >;
- };
-
- main_mmc1_pins_default: main-mmc1-pins-default {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
- J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
- J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
- J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
- J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
- J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
- J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
- J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
- >;
- };
-};
-
-&wkup_pmx0 {
- mcu_uart0_pins_default: mcu-uart0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */
- J721S2_WKUP_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */
- J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
- J721S2_WKUP_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
- >;
- };
-
- wkup_uart0_pins_default: wkup-uart0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */
- J721S2_WKUP_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
- J721S2_WKUP_IOPAD(0x0b0, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
- J721S2_WKUP_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
- >;
- };
-};
-
&sms {
- mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
+ mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
- bootph-pre-ram;
-};
-
-&wkup_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
-};
-
-&mcu_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_uart0_pins_default>;
-};
-
-&main_uart8 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart8_pins_default>;
-};
-
-&main_sdhci0 {
- /delete-property/ power-domains;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- clock-names = "clk_xin";
- clocks = <&clk_200mhz>;
- ti,driver-strength-ohm = <50>;
- non-removable;
- bus-width = <8>;
-};
-
-&main_sdhci1 {
- /delete-property/ power-domains;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- pinctrl-0 = <&main_mmc1_pins_default>;
- pinctrl-names = "default";
- clock-names = "clk_xin";
- clocks = <&clk_200mhz>;
- ti,driver-strength-ohm = <50>;
};
&mcu_ringacc {
@@ -196,5 +87,3 @@
&mcu_udmap {
ti,sci = <&dm_tifs>;
};
-
-#include "k3-j721s2-common-proc-board-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-j721s2-som-p0.dtsi b/arch/arm/dts/k3-j721s2-som-p0.dtsi
index c0687fece017..d57dd43da0ef 100644
--- a/arch/arm/dts/k3-j721s2-som-p0.dtsi
+++ b/arch/arm/dts/k3-j721s2-som-p0.dtsi
@@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
+ * SoM: https://www.ti.com/lit/zip/sprr439
+ *
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
@@ -16,6 +18,7 @@
<0x08 0x80000000 0x03 0x80000000>;
};
+ /* Reserving memory regions still pending */
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -26,7 +29,6 @@
alignment = <0x1000>;
no-map;
};
-
};
transceiver0: can-phy0 {
@@ -37,15 +39,46 @@
};
};
+&wkup_pmx0 {
+ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */
+ J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */
+ J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */
+ J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */
+ J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */
+ J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */
+ J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */
+ J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */
+ J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */
+ J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */
+ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */
+ J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */
+ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
+ J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
+ J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
+ >;
+ };
+};
+
+&wkup_pmx2 {
+ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
+ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
+ >;
+ };
+};
+
&main_pmx0 {
- main_i2c0_pins_default: main-i2c0-pins-default {
+ main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */
J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */
>;
};
- main_mcan16_pins_default: main-mcan16-pins-default {
+ main_mcan16_pins_default: main-mcan16-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */
J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */
@@ -53,7 +86,21 @@
};
};
+&wkup_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ eeprom@50 {
+ /* CAV24C256WE-GT3 */
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ };
+};
+
&main_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
@@ -71,103 +118,27 @@
};
&main_mcan16 {
+ status = "okay";
pinctrl-0 = <&main_mcan16_pins_default>;
pinctrl-names = "default";
phys = <&transceiver0>;
};
-&mailbox0_cluster0 {
- status = "disabled";
-};
-
-&mailbox0_cluster1 {
- status = "disabled";
-};
-
-&mailbox0_cluster2 {
- status = "disabled";
-};
-
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
-&mailbox0_cluster4 {
- status = "disabled";
-};
-
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
-&mailbox0_cluster6 {
- status = "disabled";
-};
-
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
-&mailbox0_cluster8 {
- status = "disabled";
-};
-
-&mailbox0_cluster9 {
- status = "disabled";
-};
-
-&mailbox0_cluster10 {
- status = "disabled";
-};
-
-&mailbox0_cluster11 {
- status = "disabled";
-};
-
-&mailbox1_cluster0 {
- status = "disabled";
-};
-
-&mailbox1_cluster1 {
- status = "disabled";
-};
-
-&mailbox1_cluster2 {
- status = "disabled";
-};
-
-&mailbox1_cluster3 {
- status = "disabled";
-};
-
-&mailbox1_cluster4 {
- status = "disabled";
-};
-
-&mailbox1_cluster5 {
- status = "disabled";
-};
-
-&mailbox1_cluster6 {
- status = "disabled";
-};
-
-&mailbox1_cluster7 {
- status = "disabled";
-};
-
-&mailbox1_cluster8 {
- status = "disabled";
-};
-
-&mailbox1_cluster9 {
- status = "disabled";
-};
-
-&mailbox1_cluster10 {
- status = "disabled";
-};
-
-&mailbox1_cluster11 {
- status = "disabled";
+&ospi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <25000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <4>;
+ };
};
diff --git a/arch/arm/dts/k3-j721s2-thermal.dtsi b/arch/arm/dts/k3-j721s2-thermal.dtsi
new file mode 100644
index 000000000000..f7b1a15b8fa0
--- /dev/null
+++ b/arch/arm/dts/k3-j721s2-thermal.dtsi
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+wkup0_thermal: wkup0-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 0>;
+
+ trips {
+ wkup0_crit: wkup0-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
+
+wkup1_thermal: wkup1-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 1>;
+
+ trips {
+ wkup1_crit: wkup1-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
+
+main0_thermal: main0-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 2>;
+
+ trips {
+ main0_crit: main0-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
+
+main1_thermal: main1-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 3>;
+
+ trips {
+ main1_crit: main1-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
+
+main2_thermal: main2-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 4>;
+
+ trips {
+ main2_crit: main2-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
+
+main3_thermal: main3-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 5>;
+
+ trips {
+ main3_crit: main3-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
+
+main4_thermal: main4-thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+ thermal-sensors = <&wkup_vtm0 6>;
+
+ trips {
+ main4_crit: main4-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-j721s2.dtsi b/arch/arm/dts/k3-j721s2.dtsi
index fe5234c40f6c..1f636acd4eee 100644
--- a/arch/arm/dts/k3-j721s2.dtsi
+++ b/arch/arm/dts/k3-j721s2.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Source for J721S2 SoC Family
*
- * TRM (SPRUJ28 – NOVEMBER 2021) : http://www.ti.com/lit/pdf/spruj28
+ * TRM (SPRUJ28 NOVEMBER 2021): https://www.ti.com/lit/pdf/spruj28
*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*
@@ -10,9 +10,10 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
+#include "k3-pinctrl.h"
+
/ {
model = "Texas Instruments K3 J721S2 SoC";
@@ -69,6 +70,7 @@
L2_0: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-level = <2>;
cache-size = <0x100000>;
cache-line-size = <64>;
@@ -79,6 +81,7 @@
msmc_l3: l3-cache0 {
compatible = "cache";
cache-level = <3>;
+ cache-unified;
};
firmware {
@@ -119,6 +122,7 @@
<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
<0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
<0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
+ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
@@ -160,6 +164,10 @@
};
};
+
+ thermal_zones: thermal-zones {
+ #include "k3-j721s2-thermal.dtsi"
+ };
};
/* Now include peripherals from each bus segment */
--
2.41.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 4/6] k3-am68: Sync from Linux tag v6.5-rc1
2023-08-25 11:16 [PATCH v2 0/6] DTS Sync from v6.5-rc1 to u-boot Manorit Chawdhry
` (2 preceding siblings ...)
2023-08-25 11:17 ` [PATCH v2 3/6] k3-j721s2: Sync from Linux tag v6.5-rc1 Manorit Chawdhry
@ 2023-08-25 11:17 ` Manorit Chawdhry
2023-08-28 2:20 ` Neha Malcom Francis
2023-08-28 16:24 ` Nishanth Menon
2023-08-25 11:17 ` [PATCH v2 5/6] docs: ti: j721s2_evm: Create documentation from J7200 docs Manorit Chawdhry
2023-08-25 11:17 ` [PATCH v2 6/6] board: ti: j721s2: MAINTAINERS: Update the MAINTAINERS File Manorit Chawdhry
5 siblings, 2 replies; 20+ messages in thread
From: Manorit Chawdhry @ 2023-08-25 11:17 UTC (permalink / raw)
To: Tom Rini
Cc: u-boot, Nishanth Menon, Vignesh Raghavendra, Neha Malcom Francis,
Udit Kumar, Reid Tonking, Apurva Nandan, Andrew Davis,
Manorit Chawdhry
The following commit syncs the device tree from Linux tag
v6.5-rc1 to U-boot and fixes the following to be compatible with
the future syncs -
- Include k3-am68-sk-base-board.dts file
Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and
include k3-am68-sk-base-board.dts for Linux fixes to propagate
to U-boot.
- Fixing the mcu_timer0
Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi
The device manager is not functional at this point so we can't
configure the clocks for the mcu_timer0, delete the properties
that enable the clocks and power domains for it.
- Fixing secure proxy nodes
Linux DT now have these nodes defined so remove them and rename to
use the Linux DT ones.
- Remove cpsw node
The compatible is now fixed and the node is not required in
-u-boot specifically
- Remove aliases and chosen node
Use these from Linux and don't override when not required.
- Remove /delete-property/ from sdhci nodes
We have the necessary clock and dev data so remove these.
- Remove dummy_clocks and fs_loader0
These weren't being used anywhere so remove it.
All these have been put in a single commit to not break the
bisectability.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
---
arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi | 69 ++---
arch/arm/dts/k3-am68-sk-base-board.dts | 389 +++++++++++++++----------
arch/arm/dts/k3-am68-sk-r5-base-board.dts | 143 ++-------
arch/arm/dts/k3-am68-sk-som.dtsi | 112 ++-----
4 files changed, 300 insertions(+), 413 deletions(-)
diff --git a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi
index 79faa1b5737d..b05a2245b6da 100644
--- a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi
@@ -1,29 +1,10 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-j721s2-binman.dtsi"
-/ {
- chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
- };
-
- aliases {
- serial0 = &wkup_uart0;
- serial1 = &mcu_uart0;
- serial2 = &main_uart8;
- i2c0 = &wkup_i2c0;
- i2c1 = &mcu_i2c0;
- i2c2 = &mcu_i2c1;
- i2c3 = &main_i2c0;
- ethernet0 = &cpsw_port1;
- mmc1 = &main_sdhci1;
- };
-};
-
&wkup_i2c0 {
bootph-pre-ram;
};
@@ -39,14 +20,6 @@
&cbass_mcu_wakeup {
bootph-pre-ram;
- timer1: timer@40400000 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x40400000 0x0 0x80>;
- ti,timer-alwon;
- clock-frequency = <250000000>;
- bootph-pre-ram;
- };
-
chipid@43000014 {
bootph-pre-ram;
};
@@ -102,10 +75,26 @@
bootph-pre-ram;
};
+&main_usbss0_pins_default {
+ bootph-pre-ram;
+};
+
&wkup_pmx0 {
bootph-pre-ram;
};
+&wkup_pmx1 {
+ bootph-pre-ram;
+};
+
+&wkup_pmx2 {
+ bootph-pre-ram;
+};
+
+&wkup_pmx3 {
+ bootph-pre-ram;
+};
+
&k3_pds {
bootph-pre-ram;
};
@@ -130,23 +119,23 @@
bootph-pre-ram;
};
-&mcu_cpsw {
- reg = <0x0 0x46000000 0x0 0x200000>,
- <0x0 0x40f00200 0x0 0x8>;
- reg-names = "cpsw_nuss", "mac_efuse";
- /delete-property/ ranges;
+&main_sdhci1 {
+ bootph-pre-ram;
+};
- cpsw-phy-sel@40f04040 {
- compatible = "ti,am654-cpsw-phy-sel";
- reg= <0x0 0x40f04040 0x0 0x4>;
- reg-names = "gmii-sel";
- };
+&ospi0 {
+ status = "disabled";
};
-&main_sdhci0 {
+&ospi1 {
status = "disabled";
};
-&main_sdhci1 {
+&usbss0 {
+ bootph-pre-ram;
+};
+
+&usb0 {
+ dr_mode = "peripheral";
bootph-pre-ram;
};
diff --git a/arch/arm/dts/k3-am68-sk-base-board.dts b/arch/arm/dts/k3-am68-sk-base-board.dts
index 8fc03324ab8a..d5889ba3fa46 100644
--- a/arch/arm/dts/k3-am68-sk-base-board.dts
+++ b/arch/arm/dts/k3-am68-sk-base-board.dts
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*
- * Base Board: **Yet to Add**
+ * Base Board: https://www.ti.com/lit/zip/SPRR463
*/
/dts-v1/;
@@ -11,6 +11,7 @@
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/mux/ti-serdes.h>
/ {
compatible = "ti,am68-sk", "ti,j721s2";
@@ -18,15 +19,20 @@
chosen {
stdout-path = "serial2:115200n8";
- bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x2880000";
};
aliases {
+ serial0 = &wkup_uart0;
+ serial1 = &mcu_uart0;
serial2 = &main_uart8;
mmc1 = &main_sdhci1;
+ can0 = &mcu_mcan0;
+ can1 = &mcu_mcan1;
+ can2 = &main_mcan6;
+ can3 = &main_mcan7;
};
- vusb_main: fixedregulator-vusb-main5v0 {
+ vusb_main: regulator-vusb-main5v0 {
/* USB MAIN INPUT 5V DC */
compatible = "regulator-fixed";
regulator-name = "vusb-main5v0";
@@ -36,7 +42,7 @@
regulator-boot-on;
};
- vsys_3v3: fixedregulator-vsys3v3 {
+ vsys_3v3: regulator-vsys3v3 {
/* Output of LM5141 */
compatible = "regulator-fixed";
regulator-name = "vsys_3v3";
@@ -47,7 +53,7 @@
regulator-boot-on;
};
- vdd_mmc1: fixedregulator-sd {
+ vdd_mmc1: regulator-sd {
/* Output of TPS22918 */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
@@ -56,10 +62,10 @@
regulator-boot-on;
enable-active-high;
vin-supply = <&vsys_3v3>;
- gpio = <&exp1 10 GPIO_ACTIVE_HIGH>;
+ gpio = <&exp1 8 GPIO_ACTIVE_HIGH>;
};
- vdd_sd_dv: gpio-regulator-TLV71033 {
+ vdd_sd_dv: regulator-tlv71033 {
/* Output of TLV71033 */
compatible = "regulator-gpio";
regulator-name = "tlv71033";
@@ -73,30 +79,69 @@
states = <1800000 0x0>,
<3300000 0x1>;
};
+
+ vsys_io_1v8: regulator-vsys-io-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_io_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_io_1v2: regulator-vsys-io-1v2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_io_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ transceiver1: can-phy0 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ };
+
+ transceiver2: can-phy1 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ };
+
+ transceiver3: can-phy2 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ };
+
+ transceiver4: can-phy3 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ };
};
&main_pmx0 {
- main_uart8_pins_default: main-uart8-pins-default {
+ main_uart8_pins_default: main-uart8-default-pins {
pinctrl-single,pins = <
- J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */
- J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */
J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
>;
};
- main_i2c0_pins_default: i2c0-pins-default {
+ main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
- J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */
- J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */
+ J721S2_IOPAD(0x0e0, PIN_INPUT, 0) /* (AH25) I2C0_SCL */
+ J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */
>;
};
- main_mmc1_pins_default: main-mmc1-pins-default {
+ main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
- J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
@@ -105,102 +150,197 @@
>;
};
- vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
+ vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x0c4, PIN_INPUT, 7) /* (AB26) ECAP0_IN_APWM_OUT.GPIO0_49 */
>;
};
-};
-&wkup_pmx0 {
- mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+ main_usbss0_pins_default: main-usbss0-default-pins {
pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
- J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
- J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
- J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
- J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
- J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
- J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
- J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
- J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
- J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
- J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
- J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
+ J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
>;
};
- mcu_mdio_pins_default: mcu-mdio-pins-default {
+ main_mcan6_pins_default: main-mcan6-default-pins {
pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
- J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
+ J721S2_IOPAD(0x098, PIN_INPUT, 0) /* (V25) MCASP0_AXR10.MCAN6_RX */
+ J721S2_IOPAD(0x094, PIN_INPUT, 0) /* (AA25) MCASP0_AXR9.MCAN6_TX */
>;
};
-};
-&main_gpio2 {
- status = "disabled";
-};
+ main_mcan7_pins_default: main-mcan7-default-pins {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */
+ J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */
+ >;
+ };
-&main_gpio4 {
- status = "disabled";
-};
+ main_i2c4_pins_default: main-i2c4-default-pins {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) MCAN13_RX.I2C4_SDA */
+ J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) MCAN14_TX.I2C4_SCL */
+ >;
+ };
-&main_gpio6 {
- status = "disabled";
+ rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0a8, PIN_INPUT, 7) /* (U24) MCASP0_AXR14.GPIO0_42 */
+ J721S2_IOPAD(0x090, PIN_INPUT, 7) /* (W24) MCASP0_AXR8.GPIO0_36 */
+ J721S2_IOPAD(0x0bc, PIN_INPUT, 7) /* (V28) MCASP1_AFSX.GPIO0_47 */
+ J721S2_IOPAD(0x06c, PIN_INPUT, 7) /* (V26) MCAN1_TX.GPIO0_27 */
+ J721S2_IOPAD(0x004, PIN_INPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */
+ J721S2_IOPAD(0x008, PIN_INPUT, 7) /* (AC24) MCAN12_RX.GPIO0_2 */
+ J721S2_IOPAD(0x0b8, PIN_INPUT, 7) /* (AA24) MCASP1_ACLKX.GPIO0_46 */
+ J721S2_IOPAD(0x00c, PIN_INPUT, 7) /* (AE28) MCAN13_TX.GPIO0_3 */
+ J721S2_IOPAD(0x034, PIN_INPUT, 7) /* (AD24) PMIC_WAKE0.GPIO0_13 */
+ J721S2_IOPAD(0x0a4, PIN_INPUT, 7) /* (T23) MCASP0_AXR13.GPIO0_41 */
+ J721S2_IOPAD(0x0c0, PIN_INPUT, 7) /* (T28) MCASP1_AXR0.GPIO0_48 */
+ J721S2_IOPAD(0x0b4, PIN_INPUT, 7) /* (U25) MCASP1_AXR4.GPIO0_45 */
+ J721S2_IOPAD(0x0cc, PIN_INPUT, 7) /* (AE27) SPI0_CS0.GPIO0_51 */
+ J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */
+ >;
+ };
};
-&wkup_gpio1 {
- status = "disabled";
+&wkup_pmx2 {
+ wkup_uart0_pins_default: wkup-uart0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */
+ J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
+ J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
+ J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
+ >;
+ };
+
+ mcu_cpsw_pins_default: mcu-cpsw-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
+ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
+ J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
+ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
+ J721S2_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
+ J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
+ J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
+ J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
+ J721S2_WKUP_IOPAD(0x00C, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
+ J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
+ J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
+ J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
+ >;
+ };
+
+ mcu_mdio_pins_default: mcu-mdio-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
+ J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
+ >;
+ };
+
+ mcu_mcan0_pins_default: mcu-mcan0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */
+ J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */
+ >;
+ };
+
+ mcu_mcan1_pins_default: mcu-mcan1-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
+ J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/
+ >;
+ };
+
+ mcu_i2c0_pins_default: mcu-i2c0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (G24) MCU_I2C0_SCL */
+ J721S2_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (J25) MCU_I2C0_SDA */
+ >;
+ };
+
+ mcu_i2c1_pins_default: mcu-i2c1-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x078, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */
+ J721S2_WKUP_IOPAD(0x07c, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */
+ >;
+ };
+
+ mcu_uart0_pins_default: mcu-uart0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
+ J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
+ >;
+ };
+
+ mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-pins0-default {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */
+ J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */
+ J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */
+ J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */
+ J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/
+ J721S2_WKUP_IOPAD(0x0B8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */
+ J721S2_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */
+ J721S2_WKUP_IOPAD(0x11C, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */
+ J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */
+ >;
+ };
};
-&wkup_uart0 {
- status = "reserved";
+&wkup_pmx3 {
+ mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-pins1-default {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */
+ >;
+ };
};
-&main_uart0 {
- status = "disabled";
+&main_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rpi_header_gpio0_pins_default>;
};
-&main_uart1 {
+&main_gpio2 {
status = "disabled";
};
-&main_uart2 {
+&main_gpio4 {
status = "disabled";
};
-&main_uart3 {
+&main_gpio6 {
status = "disabled";
};
-&main_uart4 {
- status = "disabled";
+&wkup_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_rpi_header_gpio0_pins0_default>, <&mcu_rpi_header_gpio0_pins1_default>;
};
-&main_uart5 {
+&wkup_gpio1 {
status = "disabled";
};
-&main_uart6 {
- status = "disabled";
+&wkup_uart0 {
+ status = "reserved";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
};
-&main_uart7 {
- status = "disabled";
+&mcu_uart0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_uart0_pins_default>;
};
&main_uart8 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart8_pins_default>;
/* Shared with TFA on this platform */
power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
};
-&main_uart9 {
- status = "disabled";
-};
-
&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
@@ -211,40 +351,29 @@
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
- gpio-line-names = "CSI_VIO_SEL", "CSI_SEL_FPC_EXPN", "HDMI_PDN",
- "HDMI_LS_OE", "DP0_3V3_EN", "BOARDID_EEPROM_WP",
- "CAN_STB", "","GPIO_uSD_PWR_EN", "EDP_ENABLE",
- "IO_EXP_PCIE1_M2_RSTZ", "IO_EXP_MCU_RGMII_RSTZ",
- "IO_EXP_CSI1_EXP_RSTZ", "","CSI0_B_GPIO1",
- "CSI1_B_GPIO1";
+ gpio-line-names = " ", " ", " ", " ", " ",
+ "BOARDID_EEPROM_WP", "CAN_STB", " ",
+ "GPIO_uSD_PWR_EN", " ", "IO_EXP_PCIe1_M.2_RTSz",
+ "IO_EXP_MCU_RGMII_RST#", " ", " ", " ", " ";
};
};
-&main_i2c1 {
- status = "disabled";
-};
-
-&main_i2c2 {
- status = "disabled";
-};
-
-&main_i2c3 {
- status = "disabled";
-};
-
&main_i2c4 {
- status = "disabled";
-};
-
-&main_i2c5 {
- status = "disabled";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c4_pins_default>;
+ clock-frequency = <400000>;
};
-&main_i2c6 {
- status = "disabled";
+&mcu_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_i2c0_pins_default>;
+ clock-frequency = <400000>;
};
&main_sdhci0 {
+ /* Unused */
status = "disabled";
};
@@ -259,7 +388,7 @@
&mcu_cpsw {
pinctrl-names = "default";
- pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+ pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
};
&davinci_mdio {
@@ -277,77 +406,29 @@
};
&mcu_mcan0 {
- status = "disabled";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan0_pins_default>;
+ phys = <&transceiver1>;
};
&mcu_mcan1 {
- status = "disabled";
-};
-
-&main_mcan0 {
- status = "disabled";
-};
-
-&main_mcan1 {
- status = "disabled";
-};
-
-&main_mcan2 {
- status = "disabled";
-};
-
-&main_mcan3 {
- status = "disabled";
-};
-
-&main_mcan4 {
- status = "disabled";
-};
-
-&main_mcan5 {
- status = "disabled";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan1_pins_default>;
+ phys = <&transceiver2>;
};
&main_mcan6 {
- status = "disabled";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan6_pins_default>;
+ phys = <&transceiver3>;
};
&main_mcan7 {
- status = "disabled";
-};
-
-&main_mcan8 {
- status = "disabled";
-};
-
-&main_mcan9 {
- status = "disabled";
-};
-
-&main_mcan10 {
- status = "disabled";
-};
-
-&main_mcan11 {
- status = "disabled";
-};
-
-&main_mcan12 {
- status = "disabled";
-};
-
-&main_mcan13 {
- status = "disabled";
-};
-
-&main_mcan14 {
- status = "disabled";
-};
-
-&main_mcan15 {
- status = "disabled";
-};
-
-&main_mcan17 {
- status = "disabled";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan7_pins_default>;
+ phys = <&transceiver4>;
};
diff --git a/arch/arm/dts/k3-am68-sk-r5-base-board.dts b/arch/arm/dts/k3-am68-sk-r5-base-board.dts
index a64baba14986..bb49e866aa2c 100644
--- a/arch/arm/dts/k3-am68-sk-r5-base-board.dts
+++ b/arch/arm/dts/k3-am68-sk-r5-base-board.dts
@@ -1,19 +1,19 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-#include "k3-am68-sk-som.dtsi"
+#include "k3-am68-sk-base-board.dts"
#include "k3-j721s2-ddr-evm-lp4-4266.dtsi"
#include "k3-j721s2-ddr.dtsi"
+#include "k3-am68-sk-base-board-u-boot.dtsi"
/ {
chosen {
- firmware-loader = &fs_loader0;
stdout-path = &main_uart8;
- tick-timer = &timer1;
+ tick-timer = &mcu_timer0;
};
aliases {
@@ -21,11 +21,6 @@
remoteproc1 = &a72_0;
};
- fs_loader0: fs_loader@0 {
- compatible = "u-boot,fs-loader";
- bootph-all;
- };
-
a72_0: a72@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
@@ -41,46 +36,25 @@
ti,sci-host-id = <10>;
bootph-pre-ram;
};
+};
- clk_200mhz: dummy_clock_200mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- bootph-pre-ram;
- };
-
- clk_19_2mhz: dummy_clock_19_2mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <19200000>;
+&mcu_timer0 {
+ clock-frequency = <250000000>;
bootph-pre-ram;
- };
};
-&cbass_mcu_wakeup {
- sa3_secproxy: secproxy@44880000 {
- bootph-pre-ram;
- compatible = "ti,am654-secure-proxy";
- reg = <0x0 0x44880000 0x0 0x20000>,
- <0x0 0x44860000 0x0 0x20000>,
- <0x0 0x43600000 0x0 0x10000>;
- reg-names = "rt", "scfg", "target_data";
- #mbox-cells = <1>;
- };
+&secure_proxy_mcu {
+ bootph-pre-ram;
+};
- mcu_secproxy: secproxy@2a380000 {
- compatible = "ti,am654-secure-proxy";
- reg = <0x0 0x2a380000 0x0 0x80000>,
- <0x0 0x2a400000 0x0 0x80000>,
- <0x0 0x2a480000 0x0 0x80000>;
- reg-names = "rt", "scfg", "target_data";
- #mbox-cells = <1>;
- bootph-pre-ram;
- };
+&secure_proxy_sa3 {
+ bootph-pre-ram;
+};
+&cbass_mcu_wakeup {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
- mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>, <&sa3_secproxy 5>;
+ mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
@@ -90,97 +64,17 @@
ti,host-id = <3>;
ti,secure-host;
mbox-names = "rx", "tx";
- mboxes= <&mcu_secproxy 21>,
- <&mcu_secproxy 23>;
+ mboxes= <&secure_proxy_mcu 21>,
+ <&secure_proxy_mcu 23>;
bootph-pre-ram;
};
};
-&main_pmx0 {
- main_uart8_pins_default: main-uart8-pins-default {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
- J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
- >;
- };
-
- main_mmc1_pins_default: main-mmc1-pins-default {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
- J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
- J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
- J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
- J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
- J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
- J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
- J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
- >;
- };
-
- main_usbss0_pins_default: main-usbss0-pins-default {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
- >;
- };
-};
-
-&wkup_pmx0 {
- mcu_uart0_pins_default: mcu-uart0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /*(C24) WKUP_GPIO0_13.MCU_UART0_RXD*/
- J721S2_WKUP_IOPAD(0x0f0, PIN_OUTPUT, 0) /*(C25) WKUP_GPIO0_12.MCU_UART0_TXD*/
- >;
- };
-
- wkup_uart0_pins_default: wkup-uart0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /*(E25) WKUP_GPIO0_6.WKUP_UART0_CTSn*/
- J721S2_WKUP_IOPAD(0x0dc, PIN_OUTPUT, 0) /*(F28) WKUP_GPIO0_7.WKUP_UART0_RTSn*/
- J721S2_WKUP_IOPAD(0x0b0, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
- J721S2_WKUP_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
- >;
- };
-
-};
-
&sms {
- mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
+ mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
- bootph-pre-ram;
-};
-
-&wkup_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
-};
-
-&mcu_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_uart0_pins_default>;
-};
-
-&main_uart8 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart8_pins_default>;
-};
-
-&main_sdhci0 {
- status = "disabled";
-};
-
-&main_sdhci1 {
- /delete-property/ power-domains;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- pinctrl-0 = <&main_mmc1_pins_default>;
- pinctrl-names = "default";
- clock-names = "clk_xin";
- clocks = <&clk_200mhz>;
- ti,driver-strength-ohm = <50>;
};
&mcu_ringacc {
@@ -191,4 +85,3 @@
ti,sci = <&dm_tifs>;
};
-#include "k3-am68-sk-base-board-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-am68-sk-som.dtsi b/arch/arm/dts/k3-am68-sk-som.dtsi
index cb1c58fcd154..6c9139f73201 100644
--- a/arch/arm/dts/k3-am68-sk-som.dtsi
+++ b/arch/arm/dts/k3-am68-sk-som.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
@@ -16,7 +16,6 @@
<0x08 0x80000000 0x03 0x80000000>;
};
- /* Reserving memory regions still pending */
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -24,104 +23,29 @@
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>;
- alignment = <0x1000>;
no-map;
};
};
};
-&mailbox0_cluster0 {
- status = "disabled";
-};
-
-&mailbox0_cluster1 {
- status = "disabled";
-};
-
-&mailbox0_cluster2 {
- status = "disabled";
-};
-
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
-&mailbox0_cluster4 {
- status = "disabled";
-};
-
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
-&mailbox0_cluster6 {
- status = "disabled";
-};
-
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
-&mailbox0_cluster8 {
- status = "disabled";
-};
-
-&mailbox0_cluster9 {
- status = "disabled";
-};
-
-&mailbox0_cluster10 {
- status = "disabled";
-};
-
-&mailbox0_cluster11 {
- status = "disabled";
-};
-
-&mailbox1_cluster0 {
- status = "disabled";
-};
-
-&mailbox1_cluster1 {
- status = "disabled";
-};
-
-&mailbox1_cluster2 {
- status = "disabled";
-};
-
-&mailbox1_cluster3 {
- status = "disabled";
-};
-
-&mailbox1_cluster4 {
- status = "disabled";
-};
-
-&mailbox1_cluster5 {
- status = "disabled";
-};
-
-&mailbox1_cluster6 {
- status = "disabled";
-};
-
-&mailbox1_cluster7 {
- status = "disabled";
-};
-
-&mailbox1_cluster8 {
- status = "disabled";
+&wkup_pmx2 {
+ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
+ J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
+ >;
+ };
};
-&mailbox1_cluster9 {
- status = "disabled";
-};
+&wkup_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default>;
+ clock-frequency = <400000>;
-&mailbox1_cluster10 {
- status = "disabled";
-};
-
-&mailbox1_cluster11 {
- status = "disabled";
+ eeprom@51 {
+ /* AT24C512C-MAHM-T */
+ compatible = "atmel,24c512";
+ reg = <0x51>;
+ };
};
--
2.41.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 5/6] docs: ti: j721s2_evm: Create documentation from J7200 docs
2023-08-25 11:16 [PATCH v2 0/6] DTS Sync from v6.5-rc1 to u-boot Manorit Chawdhry
` (3 preceding siblings ...)
2023-08-25 11:17 ` [PATCH v2 4/6] k3-am68: " Manorit Chawdhry
@ 2023-08-25 11:17 ` Manorit Chawdhry
2023-08-28 2:24 ` Neha Malcom Francis
2023-08-28 13:30 ` Nishanth Menon
2023-08-25 11:17 ` [PATCH v2 6/6] board: ti: j721s2: MAINTAINERS: Update the MAINTAINERS File Manorit Chawdhry
5 siblings, 2 replies; 20+ messages in thread
From: Manorit Chawdhry @ 2023-08-25 11:17 UTC (permalink / raw)
To: Tom Rini
Cc: u-boot, Nishanth Menon, Vignesh Raghavendra, Neha Malcom Francis,
Udit Kumar, Reid Tonking, Apurva Nandan, Andrew Davis,
Manorit Chawdhry
The documentation is based off J7200 documentation tailored for J721S2.
TRM for J721S2: https://www.ti.com/lit/pdf/spruj28
Product Page: https://www.ti.com/product/TDA4AL-Q1
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
---
doc/board/ti/j721s2_evm.rst | 263 ++++++++++++++++++++++++++++++++++++++++++++
doc/board/ti/k3.rst | 1 +
2 files changed, 264 insertions(+)
diff --git a/doc/board/ti/j721s2_evm.rst b/doc/board/ti/j721s2_evm.rst
new file mode 100644
index 000000000000..1b560eb4a60e
--- /dev/null
+++ b/doc/board/ti/j721s2_evm.rst
@@ -0,0 +1,263 @@
+.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+.. sectionauthor:: Manorit Chawdhry <m-chawdhry@ti.com>
+
+J721S2 Platforms
+================
+
+Introduction:
+-------------
+The J721S2 family of SoCs are part of K3 Multicore SoC architecture platform
+targeting automotive applications. They are designed as a low power, high
+performance and highly integrated device architecture, adding significant
+enhancement on processing power, graphics capability, video and imaging
+processing, virtualization and coherent memory support.
+
+The device is partitioned into three functional domains, each containing
+specific processing cores and peripherals:
+
+1. Wake-up (WKUP) domain:
+ * ARM Cortex-M4F processor, runs TI Foundational Security (TIFS)
+
+2. Microcontroller (MCU) domain:
+ * Dual core ARM Cortex-R5F processor, runs device management
+ and SoC early boot
+
+3. MAIN domain:
+ * Dual core 64-bit ARM Cortex-A72, runs HLOS
+
+More info can be found in TRM: https://www.ti.com/lit/pdf/spruj28
+
+Platform information:
+
+* https://www.ti.com/tool/J721S2XSOMXEVM
+
+Boot Flow:
+----------
+Below is the pictorial representation of boot flow:
+
+.. image:: img/boot_diagram_k3_current.svg
+
+- On this platform, "TI Foundational Security" (TIFS) functions as the
+ security enclave master while "Device Manager" (DM), also known as the
+ "TISCI server" in TI terminology, offers all the essential services.
+
+- As illustrated in the diagram above, R5 SPL manages power and clock
+ services independently before handing over control to "DM". The A72 or
+ the C7x (Aux core) software components request TIFS/DM to handle
+ security or device management services.
+
+Sources:
+--------
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_boot_sources
+ :end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure:
+----------------
+0. Setup the environment variables:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_desc
+ :end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_board_env_vars_desc
+ :end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_defn
+ :end-before: .. k3_rst_include_end_common_env_vars_defn
+.. code-block:: bash
+
+ $ export UBOOT_CFG_CORTEXR=j721s2_evm_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=j721s2_evm_a72_defconfig
+ $ export TFA_BOARD=generic
+ $ export TFA_EXTRA_ARGS="K3_USART=0x8"
+ $ # This is not a typo, j784s4 is the
+ $ # OP-TEE platform for j721s2
+ $ export OPTEE_PLATFORM=k3-j784s4
+ $ export OPTEE_EXTRA_ARGS="CFG_CONSOLE_UART=0x8"
+
+.. j721s2_evm_rst_include_start_build_steps
+
+1. Trusted Firmware-A:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_tfa
+ :end-before: .. k3_rst_include_end_build_steps_tfa
+
+
+2. OP-TEE:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_optee
+ :end-before: .. k3_rst_include_end_build_steps_optee
+
+3. U-Boot:
+
+.. _j721s2_evm_rst_u_boot_r5:
+
+* 3.1 R5:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_spl_r5
+ :end-before: .. k3_rst_include_end_build_steps_spl_r5
+
+.. _j721s2_evm_rst_u_boot_a72:
+
+* 3.2 A72:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_uboot
+ :end-before: .. k3_rst_include_end_build_steps_uboot
+.. j721s2_evm_rst_include_end_build_steps
+
+Target Images
+--------------
+In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
+variant (GP, HS-FS, HS-SE) requires a different source for these files.
+
+ - GP
+
+ * tiboot3-j721s2-gp-evm.bin from :ref:`step 3.1 <j721s2_evm_rst_u_boot_r5>`
+ * tispl.bin_unsigned, u-boot.img_unsigned from :ref:`step 3.2 <j721s2_evm_rst_u_boot_a72>`
+
+ - HS-FS
+
+ * tiboot3-j721s2-hs-fs-evm.bin from :ref:`step 3.1 <j721s2_evm_rst_u_boot_r5>`
+ * tispl.bin, u-boot.img from :ref:`step 3.2 <j721s2_evm_rst_u_boot_a72>`
+
+ - HS-SE
+
+ * tiboot3-j721s2-hs-evm.bin from :ref:`step 3.1 <j721s2_evm_rst_u_boot_r5>`
+ * tispl.bin, u-boot.img from :ref:`step 3.2 <j721s2_evm_rst_u_boot_a72>`
+
+Image formats:
+--------------
+
+- tiboot3.bin
+
+.. image:: img/multi_cert_tiboot3.bin.svg
+
+- tispl.bin
+
+.. image:: img/dm_tispl.bin.svg
+
+R5 Memory Map:
+--------------
+
+.. list-table::
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - Region
+ - Start Address
+ - End Address
+
+ * - SPL
+ - 0x41c00000
+ - 0x41c40000
+
+ * - EMPTY
+ - 0x41c40000
+ - 0x41c61f20
+
+ * - STACK
+ - 0x41c65f20
+ - 0x41c61f20
+
+ * - Global data
+ - 0x41c65f20
+ - 0x41c66000
+
+ * - Heap
+ - 0x41c66000
+ - 0x41c76000
+
+ * - BSS
+ - 0x41c76000
+ - 0x41c80000
+
+ * - DM DATA
+ - 0x41c80000
+ - 0x41c84130
+
+ * - EMPTY
+ - 0x41c84130
+ - 0x41cff9fc
+
+ * - MCU Scratchpad
+ - 0x41cff9fc
+ - 0x41cffbfc
+
+ * - ROM DATA
+ - 0x41cffbfc
+ - 0x41cfffff
+
+Switch Setting for Boot Mode
+----------------------------
+
+Boot Mode pins provide means to select the boot mode and options before the
+device is powered up. After every POR, they are the main source to populate
+the Boot Parameter Tables.
+
+The following table shows some common boot modes used on J721S2 platform.
+More details can be found in the Technical Reference Manual:
+https://www.ti.com/lit/pdf/spruj28 under the `Boot Mode Pins` section.
+
+.. list-table:: Boot Modes
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - Switch Label
+ - SW9: 12345678
+ - SW8: 12345678
+
+ * - SD
+ - 00000000
+ - 10000010
+
+ * - EMMC
+ - 01000000
+ - 10000000
+
+ * - OSPI
+ - 01000000
+ - 00000110
+
+ * - UART
+ - 01110000
+ - 00000000
+
+ * - USB DFU
+ - 00100000
+ - 10000000
+
+For SW8 and SW9, the switch state in the "ON" position = 1.
+
+Debugging U-Boot
+----------------
+
+See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
+detailed setup information.
+
+.. warning::
+
+ **OpenOCD support since**: v0.12.0
+
+ If the default package version of OpenOCD in your development
+ environment's distribution needs to be updated, it might be necessary to
+ build OpenOCD from the source.
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_openocd_connect_XDS110
+ :end-before: .. k3_rst_include_end_openocd_connect_XDS110
+
+To start OpenOCD and connect to the board
+
+.. code-block:: bash
+
+ openocd -f board/ti_j721s2evm.cfg
diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst
index 5f9bd4dfcbe9..423d55526dc5 100644
--- a/doc/board/ti/k3.rst
+++ b/doc/board/ti/k3.rst
@@ -36,6 +36,7 @@ K3 Based SoCs
am65x_evm
j7200_evm
j721e_evm
+ j721s2_evm
Boot Flow Overview
------------------
--
2.41.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 6/6] board: ti: j721s2: MAINTAINERS: Update the MAINTAINERS File.
2023-08-25 11:16 [PATCH v2 0/6] DTS Sync from v6.5-rc1 to u-boot Manorit Chawdhry
` (4 preceding siblings ...)
2023-08-25 11:17 ` [PATCH v2 5/6] docs: ti: j721s2_evm: Create documentation from J7200 docs Manorit Chawdhry
@ 2023-08-25 11:17 ` Manorit Chawdhry
2023-08-28 16:39 ` Nishanth Menon
5 siblings, 1 reply; 20+ messages in thread
From: Manorit Chawdhry @ 2023-08-25 11:17 UTC (permalink / raw)
To: Tom Rini
Cc: u-boot, Nishanth Menon, Vignesh Raghavendra, Neha Malcom Francis,
Udit Kumar, Reid Tonking, Apurva Nandan, Andrew Davis,
Manorit Chawdhry
Update the MAINTAINERS file and propose a new MAINTAINER for j721s2 due
to the previous MAINTAINER not being associated with TI.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
---
board/ti/j721s2/MAINTAINERS | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/board/ti/j721s2/MAINTAINERS b/board/ti/j721s2/MAINTAINERS
index 323bd2353a7e..97a0581d0405 100644
--- a/board/ti/j721s2/MAINTAINERS
+++ b/board/ti/j721s2/MAINTAINERS
@@ -1,7 +1,8 @@
J721S2 BOARD
-M: Aswath Govindraju <a-govindraju@ti.com>
+M: Manorit Chawdhry <m-chawdhry@ti.com>
S: Maintained
F: board/ti/j721s2
+F: doc/board/ti/j721s2_evm.rst
F: include/configs/j721s2_evm.h
F: configs/j721s2_evm_r5_defconfig
F: configs/j721s2_evm_a72_defconfig
@@ -11,6 +12,6 @@ F: arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
F: arch/arm/dts/k3-j721s2-som-p0.dtsi
F: arch/arm/dts/k3-j721s2-common-proc-board.dts
F: arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
-F: arch/arm/dts//k3-j721s2-r5-common-proc-board.dts
+F: arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
F: arch/arm/dts/k3-j721s2-ddr.dtsi
F: arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi
--
2.41.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v2 2/6] arm: mach-k3: j721s2: Add mcu_timer0 id to the dev list
2023-08-25 11:17 ` [PATCH v2 2/6] arm: mach-k3: j721s2: Add mcu_timer0 id to the dev list Manorit Chawdhry
@ 2023-08-28 2:05 ` Neha Malcom Francis
2023-08-28 16:35 ` Nishanth Menon
1 sibling, 0 replies; 20+ messages in thread
From: Neha Malcom Francis @ 2023-08-28 2:05 UTC (permalink / raw)
To: Manorit Chawdhry, Tom Rini
Cc: u-boot, Nishanth Menon, Vignesh Raghavendra, Udit Kumar,
Reid Tonking, Apurva Nandan, Andrew Davis
Hi Manorit
On 25/08/23 16:47, Manorit Chawdhry wrote:
> mcu_timer0 is used by u-boot as the tick-timer. Add it to the soc
> devices lsit so it an be enabled via the k3 power controller.
>
> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
> ---
> arch/arm/mach-k3/j721s2/dev-data.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/mach-k3/j721s2/dev-data.c b/arch/arm/mach-k3/j721s2/dev-data.c
> index 8c999a3c5a8b..df70c5e5d7c0 100644
> --- a/arch/arm/mach-k3/j721s2/dev-data.c
> +++ b/arch/arm/mach-k3/j721s2/dev-data.c
> @@ -47,6 +47,7 @@ static struct ti_lpsc soc_lpsc_list[] = {
> };
>
> static struct ti_dev soc_dev_list[] = {
> + PSC_DEV(35, &soc_lpsc_list[0]),
> PSC_DEV(108, &soc_lpsc_list[0]),
> PSC_DEV(109, &soc_lpsc_list[0]),
> PSC_DEV(110, &soc_lpsc_list[0]),
>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
--
Thanking You
Neha Malcom Francis
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/6] k3-j721s2: Sync from Linux tag v6.5-rc1
2023-08-25 11:17 ` [PATCH v2 3/6] k3-j721s2: Sync from Linux tag v6.5-rc1 Manorit Chawdhry
@ 2023-08-28 2:16 ` Neha Malcom Francis
2023-08-28 7:34 ` Neha Malcom Francis
2023-08-28 16:23 ` Nishanth Menon
2 siblings, 0 replies; 20+ messages in thread
From: Neha Malcom Francis @ 2023-08-28 2:16 UTC (permalink / raw)
To: Manorit Chawdhry, Tom Rini
Cc: u-boot, Nishanth Menon, Vignesh Raghavendra, Udit Kumar,
Reid Tonking, Apurva Nandan, Andrew Davis
Hi Manorit
On 25/08/23 16:47, Manorit Chawdhry wrote:
> The following commit syncs the device tree from Linux tag
> v6.5-rc1 to U-boot and fixes the following to be compatible with
> the future syncs -
>
> - Include k3-j721s2-common-proc-board.dts file
>
> Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and
> include k3-j721s2-common-proc-board.dts for Linux fixes to propagate
> to U-boot.
>
> - Fixing the mcu_timer0
>
> Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi
>
> The device manager is not functional at this point so we can't
> configure the clocks for the mcu_timer0, delete the properties
> that enable the clocks and power domains for it.
>
> - Fixing secure proxy nodes
>
> Linux DT now have these nodes defined so remove them and rename to
> use the Linux DT ones.
>
> - Remove cpsw node
>
> The compatible is now fixed and the node is not required in
> -u-boot specifically
>
> - Remove aliases and chosen node
>
> Use these from Linux and don't override when not required.
>
> - Remove /delete-property/ from sdhci nodes
>
> We have the necessary clock and dev data so remove these.
>
> - Remove dummy_clocks and fs_loader0
>
> These weren't being used anywhere so remove it.
>
> All these have been put in a single commit to not break the
> bisectability.
>
> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
> ---
> .../dts/k3-j721s2-common-proc-board-u-boot.dtsi | 60 +--
> arch/arm/dts/k3-j721s2-common-proc-board.dts | 330 ++++++------
> arch/arm/dts/k3-j721s2-main.dtsi | 585 ++++++++++++++++++++-
> arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi | 365 ++++++++++++-
> arch/arm/dts/k3-j721s2-r5-common-proc-board.dts | 151 +-----
> arch/arm/dts/k3-j721s2-som-p0.dtsi | 165 +++---
> arch/arm/dts/k3-j721s2-thermal.dtsi | 101 ++++
> arch/arm/dts/k3-j721s2.dtsi | 12 +-
> 8 files changed, 1339 insertions(+), 430 deletions(-)
>
This LGTM,
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
--
Thanking You
Neha Malcom Francis
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 4/6] k3-am68: Sync from Linux tag v6.5-rc1
2023-08-25 11:17 ` [PATCH v2 4/6] k3-am68: " Manorit Chawdhry
@ 2023-08-28 2:20 ` Neha Malcom Francis
2023-08-28 16:24 ` Nishanth Menon
1 sibling, 0 replies; 20+ messages in thread
From: Neha Malcom Francis @ 2023-08-28 2:20 UTC (permalink / raw)
To: Manorit Chawdhry, Tom Rini
Cc: u-boot, Nishanth Menon, Vignesh Raghavendra, Udit Kumar,
Reid Tonking, Apurva Nandan, Andrew Davis
Hi Manorit
On 25/08/23 16:47, Manorit Chawdhry wrote:
> The following commit syncs the device tree from Linux tag
> v6.5-rc1 to U-boot and fixes the following to be compatible with
> the future syncs -
>
> - Include k3-am68-sk-base-board.dts file
>
> Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and
> include k3-am68-sk-base-board.dts for Linux fixes to propagate
> to U-boot.
>
> - Fixing the mcu_timer0
>
> Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi
>
> The device manager is not functional at this point so we can't
> configure the clocks for the mcu_timer0, delete the properties
> that enable the clocks and power domains for it.
>
> - Fixing secure proxy nodes
>
> Linux DT now have these nodes defined so remove them and rename to
> use the Linux DT ones.
>
> - Remove cpsw node
>
> The compatible is now fixed and the node is not required in
> -u-boot specifically
>
> - Remove aliases and chosen node
>
> Use these from Linux and don't override when not required.
>
> - Remove /delete-property/ from sdhci nodes
>
> We have the necessary clock and dev data so remove these.
>
> - Remove dummy_clocks and fs_loader0
>
> These weren't being used anywhere so remove it.
>
> All these have been put in a single commit to not break the
> bisectability.
>
> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
> ---
> arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi | 69 ++---
> arch/arm/dts/k3-am68-sk-base-board.dts | 389 +++++++++++++++----------
> arch/arm/dts/k3-am68-sk-r5-base-board.dts | 143 ++-------
> arch/arm/dts/k3-am68-sk-som.dtsi | 112 ++-----
> 4 files changed, 300 insertions(+), 413 deletions(-)
>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
--
Thanking You
Neha Malcom Francis
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 5/6] docs: ti: j721s2_evm: Create documentation from J7200 docs
2023-08-25 11:17 ` [PATCH v2 5/6] docs: ti: j721s2_evm: Create documentation from J7200 docs Manorit Chawdhry
@ 2023-08-28 2:24 ` Neha Malcom Francis
2023-08-28 13:30 ` Nishanth Menon
1 sibling, 0 replies; 20+ messages in thread
From: Neha Malcom Francis @ 2023-08-28 2:24 UTC (permalink / raw)
To: Manorit Chawdhry, Tom Rini
Cc: u-boot, Nishanth Menon, Vignesh Raghavendra, Udit Kumar,
Reid Tonking, Apurva Nandan, Andrew Davis
Hi Manorit
On 25/08/23 16:47, Manorit Chawdhry wrote:
> The documentation is based off J7200 documentation tailored for J721S2.
>
> TRM for J721S2: https://www.ti.com/lit/pdf/spruj28
> Product Page: https://www.ti.com/product/TDA4AL-Q1
>
> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
> ---
> doc/board/ti/j721s2_evm.rst | 263 ++++++++++++++++++++++++++++++++++++++++++++
> doc/board/ti/k3.rst | 1 +
> 2 files changed, 264 insertions(+)
>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
--
Thanking You
Neha Malcom Francis
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/6] k3-j721s2: Sync from Linux tag v6.5-rc1
2023-08-25 11:17 ` [PATCH v2 3/6] k3-j721s2: Sync from Linux tag v6.5-rc1 Manorit Chawdhry
2023-08-28 2:16 ` Neha Malcom Francis
@ 2023-08-28 7:34 ` Neha Malcom Francis
2023-08-28 7:56 ` Manorit Chawdhry
2023-08-28 16:23 ` Nishanth Menon
2 siblings, 1 reply; 20+ messages in thread
From: Neha Malcom Francis @ 2023-08-28 7:34 UTC (permalink / raw)
To: Manorit Chawdhry, Tom Rini
Cc: u-boot, Nishanth Menon, Vignesh Raghavendra, Udit Kumar,
Reid Tonking, Apurva Nandan, Andrew Davis
Hi Manorit
On 25/08/23 16:47, Manorit Chawdhry wrote:
> The following commit syncs the device tree from Linux tag
> v6.5-rc1 to U-boot and fixes the following to be compatible with
> the future syncs -
>
[...]
> diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
> index c74e8e58ae81..022618b37c74 100644
> --- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
> +++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
> @@ -1,20 +1,19 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
[...]
> +&cbass_mcu_wakeup {
> sysctrler: sysctrler {
> compatible = "ti,am654-system-controller";
> - mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>, <&sa3_secproxy 5>;
> + mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>;
> mbox-names = "tx", "rx", "boot_notify";
> bootph-pre-ram;
> };
> @@ -92,101 +67,17 @@
> ti,host-id = <3>;
> ti,secure-host;
> mbox-names = "rx", "tx";
> - mboxes= <&mcu_secproxy 21>,
> - <&mcu_secproxy 23>;
> + mboxes= <&secure_proxy_mcu 21>,
> + <&secure_proxy_mcu 23>;
> bootph-pre-ram;
> };
> };
>
Sorry I didn't catch this earlier before the review tag. But dm_tifs can be
moved to the root node, see review comments in [1]
>
> /* Now include peripherals from each bus segment */
>
[1]
https://patchwork.ozlabs.org/project/uboot/patch/20230822185725.6718-1-reidt@ti.com/
--
Thanking You
Neha Malcom Francis
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/6] k3-j721s2: Sync from Linux tag v6.5-rc1
2023-08-28 7:34 ` Neha Malcom Francis
@ 2023-08-28 7:56 ` Manorit Chawdhry
0 siblings, 0 replies; 20+ messages in thread
From: Manorit Chawdhry @ 2023-08-28 7:56 UTC (permalink / raw)
To: Neha Malcom Francis
Cc: Tom Rini, u-boot, Nishanth Menon, Vignesh Raghavendra,
Udit Kumar, Reid Tonking, Apurva Nandan, Andrew Davis
Hi Neha,
On 13:04-20230828, Neha Malcom Francis wrote:
> Hi Manorit
>
> On 25/08/23 16:47, Manorit Chawdhry wrote:
> > The following commit syncs the device tree from Linux tag
> > v6.5-rc1 to U-boot and fixes the following to be compatible with
> > the future syncs -
> >
>
> [...]
>
> > diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
> > index c74e8e58ae81..022618b37c74 100644
> > --- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
> > +++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
> > @@ -1,20 +1,19 @@
> > // SPDX-License-Identifier: GPL-2.0
> > /*
> > - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
>
> [...]
>
> > +&cbass_mcu_wakeup {
> > sysctrler: sysctrler {
> > compatible = "ti,am654-system-controller";
> > - mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>, <&sa3_secproxy 5>;
> > + mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>;
> > mbox-names = "tx", "rx", "boot_notify";
> > bootph-pre-ram;
> > };
> > @@ -92,101 +67,17 @@
> > ti,host-id = <3>;
> > ti,secure-host;
> > mbox-names = "rx", "tx";
> > - mboxes= <&mcu_secproxy 21>,
> > - <&mcu_secproxy 23>;
> > + mboxes= <&secure_proxy_mcu 21>,
> > + <&secure_proxy_mcu 23>;
> > bootph-pre-ram;
> > };
> > };
>
> Sorry I didn't catch this earlier before the review tag. But dm_tifs can be
> moved to the root node, see review comments in [1]
Thanks for catching this, will be sending a v3 with the change.
Regards,
Manorit
>
> > /* Now include peripherals from each bus segment */
> >
>
> [1] https://patchwork.ozlabs.org/project/uboot/patch/20230822185725.6718-1-reidt@ti.com/
>
> --
> Thanking You
> Neha Malcom Francis
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 5/6] docs: ti: j721s2_evm: Create documentation from J7200 docs
2023-08-25 11:17 ` [PATCH v2 5/6] docs: ti: j721s2_evm: Create documentation from J7200 docs Manorit Chawdhry
2023-08-28 2:24 ` Neha Malcom Francis
@ 2023-08-28 13:30 ` Nishanth Menon
2023-08-29 10:38 ` Manorit Chawdhry
1 sibling, 1 reply; 20+ messages in thread
From: Nishanth Menon @ 2023-08-28 13:30 UTC (permalink / raw)
To: Manorit Chawdhry, g
Cc: Tom Rini, u-boot, Vignesh Raghavendra, Neha Malcom Francis,
Udit Kumar, Reid Tonking, Apurva Nandan, Andrew Davis
i$subject: doc: board: ti: Add j721s2-evm documentation
On 16:47-20230825, Manorit Chawdhry wrote:
> The documentation is based off J7200 documentation tailored for J721S2.
>
> TRM for J721S2: https://www.ti.com/lit/pdf/spruj28
> Product Page: https://www.ti.com/product/TDA4AL-Q1
>
> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
> ---
> doc/board/ti/j721s2_evm.rst | 263 ++++++++++++++++++++++++++++++++++++++++++++
> doc/board/ti/k3.rst | 1 +
> 2 files changed, 264 insertions(+)
>
> diff --git a/doc/board/ti/j721s2_evm.rst b/doc/board/ti/j721s2_evm.rst
> new file mode 100644
> index 000000000000..1b560eb4a60e
> --- /dev/null
> +++ b/doc/board/ti/j721s2_evm.rst
> @@ -0,0 +1,263 @@
> +.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
> +.. sectionauthor:: Manorit Chawdhry <m-chawdhry@ti.com>
> +
> +J721S2 Platforms
> +================
> +
> +Introduction:
> +-------------
> +The J721S2 family of SoCs are part of K3 Multicore SoC architecture platform
> +targeting automotive applications. They are designed as a low power, high
> +performance and highly integrated device architecture, adding significant
> +enhancement on processing power, graphics capability, video and imaging
> +processing, virtualization and coherent memory support.
> +
> +The device is partitioned into three functional domains, each containing
> +specific processing cores and peripherals:
> +
> +1. Wake-up (WKUP) domain:
> + * ARM Cortex-M4F processor, runs TI Foundational Security (TIFS)
> +
> +2. Microcontroller (MCU) domain:
> + * Dual core ARM Cortex-R5F processor, runs device management
> + and SoC early boot
> +
> +3. MAIN domain:
> + * Dual core 64-bit ARM Cortex-A72, runs HLOS
> +
> +More info can be found in TRM: https://www.ti.com/lit/pdf/spruj28
> +
> +Platform information:
> +
> +* https://www.ti.com/tool/J721S2XSOMXEVM
How about am68-sk documentation?
> +
> +Boot Flow:
> +----------
> +Below is the pictorial representation of boot flow:
> +
> +.. image:: img/boot_diagram_k3_current.svg
> +
> +- On this platform, "TI Foundational Security" (TIFS) functions as the
> + security enclave master while "Device Manager" (DM), also known as the
> + "TISCI server" in TI terminology, offers all the essential services.
> +
> +- As illustrated in the diagram above, R5 SPL manages power and clock
> + services independently before handing over control to "DM". The A72 or
> + the C7x (Aux core) software components request TIFS/DM to handle
> + security or device management services.
> +
> +Sources:
> +--------
> +
> +.. include:: k3.rst
> + :start-after: .. k3_rst_include_start_boot_sources
> + :end-before: .. k3_rst_include_end_boot_sources
> +
> +Build procedure:
> +----------------
> +0. Setup the environment variables:
> +
> +.. include:: k3.rst
> + :start-after: .. k3_rst_include_start_common_env_vars_desc
> + :end-before: .. k3_rst_include_end_common_env_vars_desc
> +
> +.. include:: k3.rst
> + :start-after: .. k3_rst_include_start_board_env_vars_desc
> + :end-before: .. k3_rst_include_end_board_env_vars_desc
> +
> +Set the variables corresponding to this platform:
> +
> +.. include:: k3.rst
> + :start-after: .. k3_rst_include_start_common_env_vars_defn
> + :end-before: .. k3_rst_include_end_common_env_vars_defn
> +.. code-block:: bash
> +
> + $ export UBOOT_CFG_CORTEXR=j721s2_evm_r5_defconfig
> + $ export UBOOT_CFG_CORTEXA=j721s2_evm_a72_defconfig
> + $ export TFA_BOARD=generic
> + $ export TFA_EXTRA_ARGS="K3_USART=0x8"
> + $ # This is not a typo, j784s4 is the
is the .... ?
> + $ # OP-TEE platform for j721s2
> + $ export OPTEE_PLATFORM=k3-j784s4
> + $ export OPTEE_EXTRA_ARGS="CFG_CONSOLE_UART=0x8"
> +
> +.. j721s2_evm_rst_include_start_build_steps
> +
> +1. Trusted Firmware-A:
> +
> +.. include:: k3.rst
> + :start-after: .. k3_rst_include_start_build_steps_tfa
> + :end-before: .. k3_rst_include_end_build_steps_tfa
> +
> +
> +2. OP-TEE:
> +
> +.. include:: k3.rst
> + :start-after: .. k3_rst_include_start_build_steps_optee
> + :end-before: .. k3_rst_include_end_build_steps_optee
> +
> +3. U-Boot:
> +
> +.. _j721s2_evm_rst_u_boot_r5:
> +
> +* 3.1 R5:
> +
> +.. include:: k3.rst
> + :start-after: .. k3_rst_include_start_build_steps_spl_r5
> + :end-before: .. k3_rst_include_end_build_steps_spl_r5
> +
> +.. _j721s2_evm_rst_u_boot_a72:
> +
> +* 3.2 A72:
> +
> +.. include:: k3.rst
> + :start-after: .. k3_rst_include_start_build_steps_uboot
> + :end-before: .. k3_rst_include_end_build_steps_uboot
> +.. j721s2_evm_rst_include_end_build_steps
> +
> +Target Images
> +--------------
> +In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
> +variant (GP, HS-FS, HS-SE) requires a different source for these files.
> +
> + - GP
> +
> + * tiboot3-j721s2-gp-evm.bin from :ref:`step 3.1 <j721s2_evm_rst_u_boot_r5>`
> + * tispl.bin_unsigned, u-boot.img_unsigned from :ref:`step 3.2 <j721s2_evm_rst_u_boot_a72>`
> +
> + - HS-FS
> +
> + * tiboot3-j721s2-hs-fs-evm.bin from :ref:`step 3.1 <j721s2_evm_rst_u_boot_r5>`
> + * tispl.bin, u-boot.img from :ref:`step 3.2 <j721s2_evm_rst_u_boot_a72>`
> +
> + - HS-SE
> +
> + * tiboot3-j721s2-hs-evm.bin from :ref:`step 3.1 <j721s2_evm_rst_u_boot_r5>`
> + * tispl.bin, u-boot.img from :ref:`step 3.2 <j721s2_evm_rst_u_boot_a72>`
> +
> +Image formats:
> +--------------
> +
> +- tiboot3.bin
> +
> +.. image:: img/multi_cert_tiboot3.bin.svg
> +
> +- tispl.bin
> +
> +.. image:: img/dm_tispl.bin.svg
> +
> +R5 Memory Map:
> +--------------
> +
> +.. list-table::
> + :widths: 16 16 16
> + :header-rows: 1
> +
> + * - Region
> + - Start Address
> + - End Address
> +
> + * - SPL
> + - 0x41c00000
> + - 0x41c40000
> +
> + * - EMPTY
> + - 0x41c40000
> + - 0x41c61f20
> +
> + * - STACK
> + - 0x41c65f20
> + - 0x41c61f20
> +
> + * - Global data
> + - 0x41c65f20
> + - 0x41c66000
> +
> + * - Heap
> + - 0x41c66000
> + - 0x41c76000
> +
> + * - BSS
> + - 0x41c76000
> + - 0x41c80000
> +
> + * - DM DATA
> + - 0x41c80000
> + - 0x41c84130
> +
> + * - EMPTY
> + - 0x41c84130
> + - 0x41cff9fc
> +
> + * - MCU Scratchpad
> + - 0x41cff9fc
> + - 0x41cffbfc
> +
> + * - ROM DATA
> + - 0x41cffbfc
> + - 0x41cfffff
Anything similar for A72 memory map?
> +
> +Switch Setting for Boot Mode
> +----------------------------
> +
> +Boot Mode pins provide means to select the boot mode and options before the
> +device is powered up. After every POR, they are the main source to populate
> +the Boot Parameter Tables.
> +
> +The following table shows some common boot modes used on J721S2 platform.
> +More details can be found in the Technical Reference Manual:
> +https://www.ti.com/lit/pdf/spruj28 under the `Boot Mode Pins` section.
> +
> +.. list-table:: Boot Modes
> + :widths: 16 16 16
> + :header-rows: 1
> +
> + * - Switch Label
> + - SW9: 12345678
> + - SW8: 12345678
> +
> + * - SD
> + - 00000000
> + - 10000010
> +
> + * - EMMC
> + - 01000000
> + - 10000000
> +
> + * - OSPI
> + - 01000000
> + - 00000110
> +
> + * - UART
> + - 01110000
> + - 00000000
> +
> + * - USB DFU
> + - 00100000
> + - 10000000
> +
> +For SW8 and SW9, the switch state in the "ON" position = 1.
What about AM68-SK ?
> +
> +Debugging U-Boot
> +----------------
> +
> +See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
> +detailed setup information.
> +
> +.. warning::
> +
> + **OpenOCD support since**: v0.12.0
> +
> + If the default package version of OpenOCD in your development
> + environment's distribution needs to be updated, it might be necessary to
> + build OpenOCD from the source.
> +
> +.. include:: k3.rst
> + :start-after: .. k3_rst_include_start_openocd_connect_XDS110
> + :end-before: .. k3_rst_include_end_openocd_connect_XDS110
> +
> +To start OpenOCD and connect to the board
> +
> +.. code-block:: bash
> +
> + openocd -f board/ti_j721s2evm.cfg
> diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst
> index 5f9bd4dfcbe9..423d55526dc5 100644
> --- a/doc/board/ti/k3.rst
> +++ b/doc/board/ti/k3.rst
> @@ -36,6 +36,7 @@ K3 Based SoCs
> am65x_evm
> j7200_evm
> j721e_evm
> + j721s2_evm
>
> Boot Flow Overview
> ------------------
>
> --
> 2.41.0
>
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/6] k3-j721s2: Sync from Linux tag v6.5-rc1
2023-08-25 11:17 ` [PATCH v2 3/6] k3-j721s2: Sync from Linux tag v6.5-rc1 Manorit Chawdhry
2023-08-28 2:16 ` Neha Malcom Francis
2023-08-28 7:34 ` Neha Malcom Francis
@ 2023-08-28 16:23 ` Nishanth Menon
2 siblings, 0 replies; 20+ messages in thread
From: Nishanth Menon @ 2023-08-28 16:23 UTC (permalink / raw)
To: Manorit Chawdhry
Cc: Tom Rini, u-boot, Vignesh Raghavendra, Neha Malcom Francis,
Udit Kumar, Reid Tonking, Apurva Nandan, Andrew Davis
On 16:47-20230825, Manorit Chawdhry wrote:
> The following commit syncs the device tree from Linux tag
> v6.5-rc1 to U-boot and fixes the following to be compatible with
> the future syncs -
[...]
>
> diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
> index f940ffee8787..faa01169ebd8 100644
> --- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
> +++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
> @@ -1,28 +1,10 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
>
[...]
> -&main_sdhci1 {
> +&usb0 {
> + dr_mode = "peripheral";
There is a bit of a debate going on this one
https://lore.kernel.org/u-boot/20230706-handle-otg-as-periph-v3-0-27e24fa17345@baylibre.com/
But I don't see why we need to hold off for that resolution.
> bootph-pre-ram;
> };
[...]
> diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
> index c74e8e58ae81..022618b37c74 100644
> --- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
> +++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
> @@ -1,20 +1,19 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
> + * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> /dts-v1/;
>
> -#include "k3-j721s2-som-p0.dtsi"
> +#include "k3-j721s2-common-proc-board.dts"
> #include "k3-j721s2-ddr-evm-lp4-4266.dtsi"
> #include "k3-j721s2-ddr.dtsi"
> -#include "k3-j721s2-binman.dtsi"
> +#include "k3-j721s2-common-proc-board-u-boot.dtsi"
>
> / {
> chosen {
> - firmware-loader = &fs_loader0;
> stdout-path = &main_uart8;
we don't need this either.
[...]
> - clk_19_2mhz: dummy_clock_19_2mhz {
> - compatible = "fixed-clock";
> - #clock-cells = <0>;
> - clock-frequency = <19200000>;
> +&mcu_timer0 {
> + clock-frequency = <250000000>;
> bootph-pre-ram;
Check your tabs for the clock-frequency and bootph property (you have
one extra tab tab).
> - };
> };
>
[...]
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 4/6] k3-am68: Sync from Linux tag v6.5-rc1
2023-08-25 11:17 ` [PATCH v2 4/6] k3-am68: " Manorit Chawdhry
2023-08-28 2:20 ` Neha Malcom Francis
@ 2023-08-28 16:24 ` Nishanth Menon
1 sibling, 0 replies; 20+ messages in thread
From: Nishanth Menon @ 2023-08-28 16:24 UTC (permalink / raw)
To: Manorit Chawdhry
Cc: Tom Rini, u-boot, Vignesh Raghavendra, Neha Malcom Francis,
Udit Kumar, Reid Tonking, Apurva Nandan, Andrew Davis
On 16:47-20230825, Manorit Chawdhry wrote:
> The following commit syncs the device tree from Linux tag
> v6.5-rc1 to U-boot and fixes the following to be compatible with
> the future syncs -
>
[..]
>
> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
> ---
> arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi | 69 ++---
> arch/arm/dts/k3-am68-sk-base-board.dts | 389 +++++++++++++++----------
> arch/arm/dts/k3-am68-sk-r5-base-board.dts | 143 ++-------
> arch/arm/dts/k3-am68-sk-som.dtsi | 112 ++-----
These files don't have maintainer entries?
> 4 files changed, 300 insertions(+), 413 deletions(-)
>
> diff --git a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi
> index 79faa1b5737d..b05a2245b6da 100644
> --- a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi
> +++ b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi
> +
[...]
> +&usb0 {
> + dr_mode = "peripheral";
There is a bit of a debate ongoing on this.
https://lore.kernel.org/u-boot/20230706-handle-otg-as-periph-v3-0-27e24fa17345@baylibre.com/
But I don't see why we need to hold off for that resolution.
> bootph-pre-ram;
> };
> diff --git a/arch/arm/dts/k3-am68-sk-r5-base-board.dts b/arch/arm/dts/k3-am68-sk-r5-base-board.dts
> index a64baba14986..bb49e866aa2c 100644
> --- a/arch/arm/dts/k3-am68-sk-r5-base-board.dts
> +++ b/arch/arm/dts/k3-am68-sk-r5-base-board.dts
> @@ -1,19 +1,19 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
> + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> /dts-v1/;
>
> -#include "k3-am68-sk-som.dtsi"
> +#include "k3-am68-sk-base-board.dts"
> #include "k3-j721s2-ddr-evm-lp4-4266.dtsi"
> #include "k3-j721s2-ddr.dtsi"
> +#include "k3-am68-sk-base-board-u-boot.dtsi"
>
> / {
> chosen {
> - firmware-loader = &fs_loader0;
> stdout-path = &main_uart8;
Does'nt this come from board.dts?
[...]
> &mcu_ringacc {
> @@ -191,4 +85,3 @@
> ti,sci = <&dm_tifs>;
> };
>
There is an extra EoL here.
> -#include "k3-am68-sk-base-board-u-boot.dtsi"
[...]
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 2/6] arm: mach-k3: j721s2: Add mcu_timer0 id to the dev list
2023-08-25 11:17 ` [PATCH v2 2/6] arm: mach-k3: j721s2: Add mcu_timer0 id to the dev list Manorit Chawdhry
2023-08-28 2:05 ` Neha Malcom Francis
@ 2023-08-28 16:35 ` Nishanth Menon
1 sibling, 0 replies; 20+ messages in thread
From: Nishanth Menon @ 2023-08-28 16:35 UTC (permalink / raw)
To: Manorit Chawdhry
Cc: Tom Rini, u-boot, Vignesh Raghavendra, Neha Malcom Francis,
Udit Kumar, Reid Tonking, Apurva Nandan, Andrew Davis
On 16:47-20230825, Manorit Chawdhry wrote:
> mcu_timer0 is used by u-boot as the tick-timer. Add it to the soc
> devices lsit so it an be enabled via the k3 power controller.
>
> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
> ---
> arch/arm/mach-k3/j721s2/dev-data.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/mach-k3/j721s2/dev-data.c b/arch/arm/mach-k3/j721s2/dev-data.c
> index 8c999a3c5a8b..df70c5e5d7c0 100644
> --- a/arch/arm/mach-k3/j721s2/dev-data.c
> +++ b/arch/arm/mach-k3/j721s2/dev-data.c
> @@ -47,6 +47,7 @@ static struct ti_lpsc soc_lpsc_list[] = {
> };
>
> static struct ti_dev soc_dev_list[] = {
> + PSC_DEV(35, &soc_lpsc_list[0]),
Reviewed that mcu_timer0 with device ID 35 maps to LPSC_wkup_alwayson
which maps to index 0.
Reviewed-by: Nishanth Menon <nm@ti.com>
> PSC_DEV(108, &soc_lpsc_list[0]),
> PSC_DEV(109, &soc_lpsc_list[0]),
> PSC_DEV(110, &soc_lpsc_list[0]),
>
> --
> 2.41.0
>
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 6/6] board: ti: j721s2: MAINTAINERS: Update the MAINTAINERS File.
2023-08-25 11:17 ` [PATCH v2 6/6] board: ti: j721s2: MAINTAINERS: Update the MAINTAINERS File Manorit Chawdhry
@ 2023-08-28 16:39 ` Nishanth Menon
0 siblings, 0 replies; 20+ messages in thread
From: Nishanth Menon @ 2023-08-28 16:39 UTC (permalink / raw)
To: Manorit Chawdhry
Cc: Tom Rini, u-boot, Vignesh Raghavendra, Neha Malcom Francis,
Udit Kumar, Reid Tonking, Apurva Nandan, Andrew Davis
On 16:47-20230825, Manorit Chawdhry wrote:
> Update the MAINTAINERS file and propose a new MAINTAINER for j721s2 due
> to the previous MAINTAINER not being associated with TI.
>
> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
> ---
> board/ti/j721s2/MAINTAINERS | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/board/ti/j721s2/MAINTAINERS b/board/ti/j721s2/MAINTAINERS
> index 323bd2353a7e..97a0581d0405 100644
> --- a/board/ti/j721s2/MAINTAINERS
> +++ b/board/ti/j721s2/MAINTAINERS
> @@ -1,7 +1,8 @@
> J721S2 BOARD
> -M: Aswath Govindraju <a-govindraju@ti.com>
> +M: Manorit Chawdhry <m-chawdhry@ti.com>
Thank you for stepping up.
> S: Maintained
> F: board/ti/j721s2
> +F: doc/board/ti/j721s2_evm.rst
> F: include/configs/j721s2_evm.h
> F: configs/j721s2_evm_r5_defconfig
> F: configs/j721s2_evm_a72_defconfig
> @@ -11,6 +12,6 @@ F: arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
> F: arch/arm/dts/k3-j721s2-som-p0.dtsi
> F: arch/arm/dts/k3-j721s2-common-proc-board.dts
> F: arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
> -F: arch/arm/dts//k3-j721s2-r5-common-proc-board.dts
> +F: arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
> F: arch/arm/dts/k3-j721s2-ddr.dtsi
> F: arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi
I suggest adding additional patch to include AM68 as well.
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 1/6] configs: j721s2_evm_r5_defconfig: Increase malloc pool size in DRAM
2023-08-25 11:16 ` [PATCH v2 1/6] configs: j721s2_evm_r5_defconfig: Increase malloc pool size in DRAM Manorit Chawdhry
@ 2023-08-28 16:41 ` Nishanth Menon
0 siblings, 0 replies; 20+ messages in thread
From: Nishanth Menon @ 2023-08-28 16:41 UTC (permalink / raw)
To: Manorit Chawdhry
Cc: Tom Rini, u-boot, Vignesh Raghavendra, Neha Malcom Francis,
Udit Kumar, Reid Tonking, Apurva Nandan, Andrew Davis,
Nikhil M Jain
On 16:46-20230825, Manorit Chawdhry wrote:
> From: Udit Kumar <u-kumar1@ti.com>
>
> The malloc capacity in DRAM at R5 SPL is set to 1MB which isn't
> sufficient to load the new tispl.bin to
> enable loading of tispl.bin the size is increased by 256KB to 1.25MB.
>
> Cc: Nikhil M Jain <n-jain1@ti.com>
> Signed-off-by: Udit Kumar <u-kumar1@ti.com>
> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
> ---
> configs/j721s2_evm_r5_defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
> index 1e66ac23d05b..e2b83b337809 100644
> --- a/configs/j721s2_evm_r5_defconfig
> +++ b/configs/j721s2_evm_r5_defconfig
> @@ -42,6 +42,7 @@ CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
> CONFIG_SPL_BOARD_INIT=y
> CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> CONFIG_SPL_STACK_R=y
> +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x140000
> CONFIG_SPL_SEPARATE_BSS=y
> CONFIG_SYS_SPL_MALLOC=y
> CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
Though this makes me curious who AM62x did'nt need this.. but anyways..
Reviewed-by: Nishanth Menon <nm@ti.com>
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 5/6] docs: ti: j721s2_evm: Create documentation from J7200 docs
2023-08-28 13:30 ` Nishanth Menon
@ 2023-08-29 10:38 ` Manorit Chawdhry
0 siblings, 0 replies; 20+ messages in thread
From: Manorit Chawdhry @ 2023-08-29 10:38 UTC (permalink / raw)
To: Nishanth Menon
Cc: g, Tom Rini, u-boot, Vignesh Raghavendra, Neha Malcom Francis,
Udit Kumar, Reid Tonking, Apurva Nandan, Andrew Davis
Hi Nishanth,
On 08:30-20230828, Nishanth Menon wrote:
> i$subject: doc: board: ti: Add j721s2-evm documentation
Will be updating it, thanks.
>
> On 16:47-20230825, Manorit Chawdhry wrote:
> > The documentation is based off J7200 documentation tailored for J721S2.
> >
> > TRM for J721S2: https://www.ti.com/lit/pdf/spruj28
> > Product Page: https://www.ti.com/product/TDA4AL-Q1
> >
> > Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
> > ---
> > doc/board/ti/j721s2_evm.rst | 263 ++++++++++++++++++++++++++++++++++++++++++++
> > doc/board/ti/k3.rst | 1 +
> > 2 files changed, 264 insertions(+)
> >
> > diff --git a/doc/board/ti/j721s2_evm.rst b/doc/board/ti/j721s2_evm.rst
> > new file mode 100644
> > index 000000000000..1b560eb4a60e
> > --- /dev/null
> > +++ b/doc/board/ti/j721s2_evm.rst
> > @@ -0,0 +1,263 @@
> > +.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
> > +.. sectionauthor:: Manorit Chawdhry <m-chawdhry@ti.com>
> > +
> > +J721S2 Platforms
> > +================
> > +
> > +Introduction:
> > +-------------
> > +The J721S2 family of SoCs are part of K3 Multicore SoC architecture platform
> > +targeting automotive applications. They are designed as a low power, high
> > +performance and highly integrated device architecture, adding significant
> > +enhancement on processing power, graphics capability, video and imaging
> > +processing, virtualization and coherent memory support.
> > +
> > +The device is partitioned into three functional domains, each containing
> > +specific processing cores and peripherals:
> > +
> > +1. Wake-up (WKUP) domain:
> > + * ARM Cortex-M4F processor, runs TI Foundational Security (TIFS)
> > +
> > +2. Microcontroller (MCU) domain:
> > + * Dual core ARM Cortex-R5F processor, runs device management
> > + and SoC early boot
> > +
> > +3. MAIN domain:
> > + * Dual core 64-bit ARM Cortex-A72, runs HLOS
> > +
> > +More info can be found in TRM: https://www.ti.com/lit/pdf/spruj28
> > +
> > +Platform information:
> > +
> > +* https://www.ti.com/tool/J721S2XSOMXEVM
>
> How about am68-sk documentation?
Thanks for catching this! Missed it. Will be updating it.
>
> > +
> > +Boot Flow:
> > +----------
> > +Below is the pictorial representation of boot flow:
> > +
> > +.. image:: img/boot_diagram_k3_current.svg
> > +
> > +- On this platform, "TI Foundational Security" (TIFS) functions as the
> > + security enclave master while "Device Manager" (DM), also known as the
> > + "TISCI server" in TI terminology, offers all the essential services.
> > +
> > +- As illustrated in the diagram above, R5 SPL manages power and clock
> > + services independently before handing over control to "DM". The A72 or
> > + the C7x (Aux core) software components request TIFS/DM to handle
> > + security or device management services.
> > +
> > +Sources:
> > +--------
> > +
> > +.. include:: k3.rst
> > + :start-after: .. k3_rst_include_start_boot_sources
> > + :end-before: .. k3_rst_include_end_boot_sources
> > +
> > +Build procedure:
> > +----------------
> > +0. Setup the environment variables:
> > +
> > +.. include:: k3.rst
> > + :start-after: .. k3_rst_include_start_common_env_vars_desc
> > + :end-before: .. k3_rst_include_end_common_env_vars_desc
> > +
> > +.. include:: k3.rst
> > + :start-after: .. k3_rst_include_start_board_env_vars_desc
> > + :end-before: .. k3_rst_include_end_board_env_vars_desc
> > +
> > +Set the variables corresponding to this platform:
> > +
> > +.. include:: k3.rst
> > + :start-after: .. k3_rst_include_start_common_env_vars_defn
> > + :end-before: .. k3_rst_include_end_common_env_vars_defn
> > +.. code-block:: bash
> > +
> > + $ export UBOOT_CFG_CORTEXR=j721s2_evm_r5_defconfig
> > + $ export UBOOT_CFG_CORTEXA=j721s2_evm_a72_defconfig
> > + $ export TFA_BOARD=generic
> > + $ export TFA_EXTRA_ARGS="K3_USART=0x8"
> > + $ # This is not a typo, j784s4 is the
>
> is the .... ?
>
> > + $ # OP-TEE platform for j721s2
The next line completes it, had split the line in the comments though I
don't think it would be required given the line length. Would fix it.
Thanks.
Also, just realised that "This" is misleading. Would rework it to use
"The following".
> > + $ export OPTEE_PLATFORM=k3-j784s4
> > + $ export OPTEE_EXTRA_ARGS="CFG_CONSOLE_UART=0x8"
> > +
> > +.. j721s2_evm_rst_include_start_build_steps
> > +
> > +1. Trusted Firmware-A:
> > +
> > +.. include:: k3.rst
> > + :start-after: .. k3_rst_include_start_build_steps_tfa
> > + :end-before: .. k3_rst_include_end_build_steps_tfa
> > +
> > +
> > +2. OP-TEE:
> > +
> > +.. include:: k3.rst
> > + :start-after: .. k3_rst_include_start_build_steps_optee
> > + :end-before: .. k3_rst_include_end_build_steps_optee
> > +
> > +3. U-Boot:
> > +
> > +.. _j721s2_evm_rst_u_boot_r5:
> > +
> > +* 3.1 R5:
> > +
> > +.. include:: k3.rst
> > + :start-after: .. k3_rst_include_start_build_steps_spl_r5
> > + :end-before: .. k3_rst_include_end_build_steps_spl_r5
> > +
> > +.. _j721s2_evm_rst_u_boot_a72:
> > +
> > +* 3.2 A72:
> > +
> > +.. include:: k3.rst
> > + :start-after: .. k3_rst_include_start_build_steps_uboot
> > + :end-before: .. k3_rst_include_end_build_steps_uboot
> > +.. j721s2_evm_rst_include_end_build_steps
> > +
> > +Target Images
> > +--------------
> > +In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
> > +variant (GP, HS-FS, HS-SE) requires a different source for these files.
> > +
> > + - GP
> > +
> > + * tiboot3-j721s2-gp-evm.bin from :ref:`step 3.1 <j721s2_evm_rst_u_boot_r5>`
> > + * tispl.bin_unsigned, u-boot.img_unsigned from :ref:`step 3.2 <j721s2_evm_rst_u_boot_a72>`
> > +
> > + - HS-FS
> > +
> > + * tiboot3-j721s2-hs-fs-evm.bin from :ref:`step 3.1 <j721s2_evm_rst_u_boot_r5>`
> > + * tispl.bin, u-boot.img from :ref:`step 3.2 <j721s2_evm_rst_u_boot_a72>`
> > +
> > + - HS-SE
> > +
> > + * tiboot3-j721s2-hs-evm.bin from :ref:`step 3.1 <j721s2_evm_rst_u_boot_r5>`
> > + * tispl.bin, u-boot.img from :ref:`step 3.2 <j721s2_evm_rst_u_boot_a72>`
> > +
> > +Image formats:
> > +--------------
> > +
> > +- tiboot3.bin
> > +
> > +.. image:: img/multi_cert_tiboot3.bin.svg
> > +
> > +- tispl.bin
> > +
> > +.. image:: img/dm_tispl.bin.svg
> > +
> > +R5 Memory Map:
> > +--------------
> > +
> > +.. list-table::
> > + :widths: 16 16 16
> > + :header-rows: 1
> > +
> > + * - Region
> > + - Start Address
> > + - End Address
> > +
> > + * - SPL
> > + - 0x41c00000
> > + - 0x41c40000
> > +
> > + * - EMPTY
> > + - 0x41c40000
> > + - 0x41c61f20
> > +
> > + * - STACK
> > + - 0x41c65f20
> > + - 0x41c61f20
> > +
> > + * - Global data
> > + - 0x41c65f20
> > + - 0x41c66000
> > +
> > + * - Heap
> > + - 0x41c66000
> > + - 0x41c76000
> > +
> > + * - BSS
> > + - 0x41c76000
> > + - 0x41c80000
> > +
> > + * - DM DATA
> > + - 0x41c80000
> > + - 0x41c84130
> > +
> > + * - EMPTY
> > + - 0x41c84130
> > + - 0x41cff9fc
> > +
> > + * - MCU Scratchpad
> > + - 0x41cff9fc
> > + - 0x41cffbfc
> > +
> > + * - ROM DATA
> > + - 0x41cffbfc
> > + - 0x41cfffff
>
> Anything similar for A72 memory map?
>
Am not sure if I have that information. R5 ones I had figured out
manually during some other HS debug [0].
[0]: https://lore.kernel.org/u-boot/20230505134508.xwlplwlnb7ryvrtf@passably/
Regards,
Manorit
> > +
> > +Switch Setting for Boot Mode
> > +----------------------------
> > +
> > +Boot Mode pins provide means to select the boot mode and options before the
> > +device is powered up. After every POR, they are the main source to populate
> > +the Boot Parameter Tables.
> > +
> > +The following table shows some common boot modes used on J721S2 platform.
> > +More details can be found in the Technical Reference Manual:
> > +https://www.ti.com/lit/pdf/spruj28 under the `Boot Mode Pins` section.
> > +
> > +.. list-table:: Boot Modes
> > + :widths: 16 16 16
> > + :header-rows: 1
> > +
> > + * - Switch Label
> > + - SW9: 12345678
> > + - SW8: 12345678
> > +
> > + * - SD
> > + - 00000000
> > + - 10000010
> > +
> > + * - EMMC
> > + - 01000000
> > + - 10000000
> > +
> > + * - OSPI
> > + - 01000000
> > + - 00000110
> > +
> > + * - UART
> > + - 01110000
> > + - 00000000
> > +
> > + * - USB DFU
> > + - 00100000
> > + - 10000000
> > +
> > +For SW8 and SW9, the switch state in the "ON" position = 1.
>
> What about AM68-SK ?
>
> > +
> > +Debugging U-Boot
> > +----------------
> > +
> > +See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
> > +detailed setup information.
> > +
> > +.. warning::
> > +
> > + **OpenOCD support since**: v0.12.0
> > +
> > + If the default package version of OpenOCD in your development
> > + environment's distribution needs to be updated, it might be necessary to
> > + build OpenOCD from the source.
> > +
> > +.. include:: k3.rst
> > + :start-after: .. k3_rst_include_start_openocd_connect_XDS110
> > + :end-before: .. k3_rst_include_end_openocd_connect_XDS110
> > +
> > +To start OpenOCD and connect to the board
> > +
> > +.. code-block:: bash
> > +
> > + openocd -f board/ti_j721s2evm.cfg
> > diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst
> > index 5f9bd4dfcbe9..423d55526dc5 100644
> > --- a/doc/board/ti/k3.rst
> > +++ b/doc/board/ti/k3.rst
> > @@ -36,6 +36,7 @@ K3 Based SoCs
> > am65x_evm
> > j7200_evm
> > j721e_evm
> > + j721s2_evm
> >
> > Boot Flow Overview
> > ------------------
> >
> > --
> > 2.41.0
> >
>
> --
> Regards,
> Nishanth Menon
> Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
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2023-08-25 11:16 [PATCH v2 0/6] DTS Sync from v6.5-rc1 to u-boot Manorit Chawdhry
2023-08-25 11:16 ` [PATCH v2 1/6] configs: j721s2_evm_r5_defconfig: Increase malloc pool size in DRAM Manorit Chawdhry
2023-08-28 16:41 ` Nishanth Menon
2023-08-25 11:17 ` [PATCH v2 2/6] arm: mach-k3: j721s2: Add mcu_timer0 id to the dev list Manorit Chawdhry
2023-08-28 2:05 ` Neha Malcom Francis
2023-08-28 16:35 ` Nishanth Menon
2023-08-25 11:17 ` [PATCH v2 3/6] k3-j721s2: Sync from Linux tag v6.5-rc1 Manorit Chawdhry
2023-08-28 2:16 ` Neha Malcom Francis
2023-08-28 7:34 ` Neha Malcom Francis
2023-08-28 7:56 ` Manorit Chawdhry
2023-08-28 16:23 ` Nishanth Menon
2023-08-25 11:17 ` [PATCH v2 4/6] k3-am68: " Manorit Chawdhry
2023-08-28 2:20 ` Neha Malcom Francis
2023-08-28 16:24 ` Nishanth Menon
2023-08-25 11:17 ` [PATCH v2 5/6] docs: ti: j721s2_evm: Create documentation from J7200 docs Manorit Chawdhry
2023-08-28 2:24 ` Neha Malcom Francis
2023-08-28 13:30 ` Nishanth Menon
2023-08-29 10:38 ` Manorit Chawdhry
2023-08-25 11:17 ` [PATCH v2 6/6] board: ti: j721s2: MAINTAINERS: Update the MAINTAINERS File Manorit Chawdhry
2023-08-28 16:39 ` Nishanth Menon
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