[PATCH 0/7] mma8452 fixes and cleanup

[PATCH 0/7] mma8452 fixes and cleanup

[Hartmut Knaack]

This series addresses some issues found during review.

Hartmut Knaack (7):
  iio:accel:mma8452: fix _get_hp_filter_index
  iio:accel:mma8452: drop double include
  iio:accel:mma8452: pass up real error code
  iio:accel:mma8452: check values to be written
  iio:accel:mma8452: rework register definitions
  iio:accel:mma8452: coding style cleanup
  iio:accel:mma8452: reorder Kconfig entry

 drivers/iio/accel/Kconfig   |  24 ++---
 drivers/iio/accel/mma8452.c | 216 +++++++++++++++++++++++++-------------------
 2 files changed, 134 insertions(+), 106 deletions(-)

-- 
2.4.6

[PATCH 1/7] iio:accel:mma8452: fix _get_hp_filter_index

[Hartmut Knaack]

To iterate through the available frequencies of mma8452_hp_filter_cutoff[],
the array size of a row of that table needs to be provided to
_get_int_plus_micros_index().

Fixes: 	1e79841a00e46 ("iio: mma8452: Add highpass filter configuration.")

Signed-off-by: Hartmut Knaack <knaack.h@gmx.de>
---
 drivers/iio/accel/mma8452.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/accel/mma8452.c b/drivers/iio/accel/mma8452.c
index e8e2077c7244..245b95fc22be 100644
--- a/drivers/iio/accel/mma8452.c
+++ b/drivers/iio/accel/mma8452.c
@@ -229,7 +229,7 @@ static int mma8452_get_hp_filter_index(struct mma8452_data *data,
 	int i = mma8452_get_odr_index(data);
 
 	return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[i],
-		ARRAY_SIZE(mma8452_scales[0]), val, val2);
+		ARRAY_SIZE(mma8452_hp_filter_cutoff[0]), val, val2);
 }
 
 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
-- 
2.4.6

Re: [PATCH 1/7] iio:accel:mma8452: fix _get_hp_filter_index

[Jonathan Cameron]

On 02/08/15 21:43, Hartmut Knaack wrote:
> To iterate through the available frequencies of mma8452_hp_filter_cutoff[],
> the array size of a row of that table needs to be provided to
> _get_int_plus_micros_index().
> 
> Fixes: 	1e79841a00e46 ("iio: mma8452: Add highpass filter configuration.")
> 
> Signed-off-by: Hartmut Knaack <knaack.h@gmx.de>
Applied to the togreg branch of iio.git - initially pushed out as testing
etc.
> ---
>  drivers/iio/accel/mma8452.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/iio/accel/mma8452.c b/drivers/iio/accel/mma8452.c
> index e8e2077c7244..245b95fc22be 100644
> --- a/drivers/iio/accel/mma8452.c
> +++ b/drivers/iio/accel/mma8452.c
> @@ -229,7 +229,7 @@ static int mma8452_get_hp_filter_index(struct mma8452_data *data,
>  	int i = mma8452_get_odr_index(data);
>  
>  	return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[i],
> -		ARRAY_SIZE(mma8452_scales[0]), val, val2);
> +		ARRAY_SIZE(mma8452_hp_filter_cutoff[0]), val, val2);
>  }
>  
>  static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
> 

[PATCH 2/7] iio:accel:mma8452: drop double include

[Hartmut Knaack]

One inclusion of linux/iio/trigger_consumer.h is sufficient.

Fixes: 	ae6d9ce05691b ("iio: mma8452: Add support for interrupt driven triggers.")
Signed-off-by: Hartmut Knaack <knaack.h@gmx.de>
---
 drivers/iio/accel/mma8452.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/iio/accel/mma8452.c b/drivers/iio/accel/mma8452.c
index 245b95fc22be..153f26bc88dc 100644
--- a/drivers/iio/accel/mma8452.c
+++ b/drivers/iio/accel/mma8452.c
@@ -16,7 +16,6 @@
 #include <linux/i2c.h>
 #include <linux/iio/iio.h>
 #include <linux/iio/sysfs.h>
-#include <linux/iio/trigger_consumer.h>
 #include <linux/iio/buffer.h>
 #include <linux/iio/trigger.h>
 #include <linux/iio/trigger_consumer.h>
-- 
2.4.6

Re: [PATCH 2/7] iio:accel:mma8452: drop double include

[Jonathan Cameron]

On 02/08/15 21:43, Hartmut Knaack wrote:
> One inclusion of linux/iio/trigger_consumer.h is sufficient.
> 
> Fixes: 	ae6d9ce05691b ("iio: mma8452: Add support for interrupt driven triggers.")
> Signed-off-by: Hartmut Knaack <knaack.h@gmx.de>
Applied to the togreg branch of iio.git

Thanks,
> ---
>  drivers/iio/accel/mma8452.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/drivers/iio/accel/mma8452.c b/drivers/iio/accel/mma8452.c
> index 245b95fc22be..153f26bc88dc 100644
> --- a/drivers/iio/accel/mma8452.c
> +++ b/drivers/iio/accel/mma8452.c
> @@ -16,7 +16,6 @@
>  #include <linux/i2c.h>
>  #include <linux/iio/iio.h>
>  #include <linux/iio/sysfs.h>
> -#include <linux/iio/trigger_consumer.h>
>  #include <linux/iio/buffer.h>
>  #include <linux/iio/trigger.h>
>  #include <linux/iio/trigger_consumer.h>
> 

[PATCH 3/7] iio:accel:mma8452: pass up real error code

[Hartmut Knaack]

Pass up the error code provided by functions.

Signed-off-by: Hartmut Knaack <knaack.h@gmx.de>
---
 drivers/iio/accel/mma8452.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/iio/accel/mma8452.c b/drivers/iio/accel/mma8452.c
index 153f26bc88dc..1463392f679c 100644
--- a/drivers/iio/accel/mma8452.c
+++ b/drivers/iio/accel/mma8452.c
@@ -343,7 +343,7 @@ static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
 
 	i = mma8452_get_hp_filter_index(data, val, val2);
 	if (i < 0)
-		return -EINVAL;
+		return i;
 
 	reg = i2c_smbus_read_byte_data(data->client,
 				       MMA8452_HP_FILTER_CUTOFF);
@@ -369,7 +369,7 @@ static int mma8452_write_raw(struct iio_dev *indio_dev,
 	case IIO_CHAN_INFO_SAMP_FREQ:
 		i = mma8452_get_samp_freq_index(data, val, val2);
 		if (i < 0)
-			return -EINVAL;
+			return i;
 
 		data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
 		data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
@@ -378,7 +378,7 @@ static int mma8452_write_raw(struct iio_dev *indio_dev,
 	case IIO_CHAN_INFO_SCALE:
 		i = mma8452_get_scale_index(data, val, val2);
 		if (i < 0)
-			return -EINVAL;
+			return i;
 		data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
 		data->data_cfg |= i;
 		return mma8452_change_config(data, MMA8452_DATA_CFG,
-- 
2.4.6

Re: [PATCH 3/7] iio:accel:mma8452: pass up real error code

[Jonathan Cameron]

On 02/08/15 21:43, Hartmut Knaack wrote:
> Pass up the error code provided by functions.
> 
> Signed-off-by: Hartmut Knaack <knaack.h@gmx.de>
Applied
> ---
>  drivers/iio/accel/mma8452.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/iio/accel/mma8452.c b/drivers/iio/accel/mma8452.c
> index 153f26bc88dc..1463392f679c 100644
> --- a/drivers/iio/accel/mma8452.c
> +++ b/drivers/iio/accel/mma8452.c
> @@ -343,7 +343,7 @@ static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
>  
>  	i = mma8452_get_hp_filter_index(data, val, val2);
>  	if (i < 0)
> -		return -EINVAL;
> +		return i;
>  
>  	reg = i2c_smbus_read_byte_data(data->client,
>  				       MMA8452_HP_FILTER_CUTOFF);
> @@ -369,7 +369,7 @@ static int mma8452_write_raw(struct iio_dev *indio_dev,
>  	case IIO_CHAN_INFO_SAMP_FREQ:
>  		i = mma8452_get_samp_freq_index(data, val, val2);
>  		if (i < 0)
> -			return -EINVAL;
> +			return i;
>  
>  		data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
>  		data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
> @@ -378,7 +378,7 @@ static int mma8452_write_raw(struct iio_dev *indio_dev,
>  	case IIO_CHAN_INFO_SCALE:
>  		i = mma8452_get_scale_index(data, val, val2);
>  		if (i < 0)
> -			return -EINVAL;
> +			return i;
>  		data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
>  		data->data_cfg |= i;
>  		return mma8452_change_config(data, MMA8452_DATA_CFG,
> 

[PATCH 4/7] iio:accel:mma8452: check values to be written

[Hartmut Knaack]

Check values to be written to the device for valid lower and upper bounds.

Signed-off-by: Hartmut Knaack <knaack.h@gmx.de>
---
 drivers/iio/accel/mma8452.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/iio/accel/mma8452.c b/drivers/iio/accel/mma8452.c
index 1463392f679c..516b6108d5f8 100644
--- a/drivers/iio/accel/mma8452.c
+++ b/drivers/iio/accel/mma8452.c
@@ -471,15 +471,17 @@ static int mma8452_write_thresh(struct iio_dev *indio_dev,
 
 	switch (info) {
 	case IIO_EV_INFO_VALUE:
-		return mma8452_change_config(data, MMA8452_TRANSIENT_THS,
-					     val & MMA8452_TRANSIENT_THS_MASK);
+		if (val < 0 || val > MMA8452_TRANSIENT_THS_MASK)
+			return -EINVAL;
+
+		return mma8452_change_config(data, MMA8452_TRANSIENT_THS, val);
 
 	case IIO_EV_INFO_PERIOD:
 		steps = (val * USEC_PER_SEC + val2) /
 				mma8452_transient_time_step_us[
 					mma8452_get_odr_index(data)];
 
-		if (steps > 0xff)
+		if (steps < 0 || steps > 0xff)
 			return -EINVAL;
 
 		return mma8452_change_config(data, MMA8452_TRANSIENT_COUNT,
-- 
2.4.6

Re: [PATCH 4/7] iio:accel:mma8452: check values to be written

[Jonathan Cameron]

On 02/08/15 21:43, Hartmut Knaack wrote:
> Check values to be written to the device for valid lower and upper bounds.
> 
> Signed-off-by: Hartmut Knaack <knaack.h@gmx.de>
Applied.  Thanks.  Note these will be in testing for a short while
if anyone else wants to comment.

J
> ---
>  drivers/iio/accel/mma8452.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/iio/accel/mma8452.c b/drivers/iio/accel/mma8452.c
> index 1463392f679c..516b6108d5f8 100644
> --- a/drivers/iio/accel/mma8452.c
> +++ b/drivers/iio/accel/mma8452.c
> @@ -471,15 +471,17 @@ static int mma8452_write_thresh(struct iio_dev *indio_dev,
>  
>  	switch (info) {
>  	case IIO_EV_INFO_VALUE:
> -		return mma8452_change_config(data, MMA8452_TRANSIENT_THS,
> -					     val & MMA8452_TRANSIENT_THS_MASK);
> +		if (val < 0 || val > MMA8452_TRANSIENT_THS_MASK)
> +			return -EINVAL;
> +
> +		return mma8452_change_config(data, MMA8452_TRANSIENT_THS, val);
>  
>  	case IIO_EV_INFO_PERIOD:
>  		steps = (val * USEC_PER_SEC + val2) /
>  				mma8452_transient_time_step_us[
>  					mma8452_get_odr_index(data)];
>  
> -		if (steps > 0xff)
> +		if (steps < 0 || steps > 0xff)
>  			return -EINVAL;
>  
>  		return mma8452_change_config(data, MMA8452_TRANSIENT_COUNT,
> 

[PATCH 5/7] iio:accel:mma8452: rework register definitions

[Hartmut Knaack]

Rework register definitions to be sorted by register and bit number, with
bit definitions cascaded under the appropriate register, use GENMASK for
consecutive bitmasks and realign properly.

Signed-off-by: Hartmut Knaack <knaack.h@gmx.de>
---
 drivers/iio/accel/mma8452.c | 93 ++++++++++++++++++++++-----------------------
 1 file changed, 45 insertions(+), 48 deletions(-)

diff --git a/drivers/iio/accel/mma8452.c b/drivers/iio/accel/mma8452.c
index 516b6108d5f8..10e9623431e4 100644
--- a/drivers/iio/accel/mma8452.c
+++ b/drivers/iio/accel/mma8452.c
@@ -23,54 +23,51 @@
 #include <linux/iio/events.h>
 #include <linux/delay.h>
 
-#define MMA8452_STATUS 0x00
-#define MMA8452_OUT_X 0x01 /* MSB first, 12-bit  */
-#define MMA8452_OUT_Y 0x03
-#define MMA8452_OUT_Z 0x05
-#define MMA8452_INT_SRC 0x0c
-#define MMA8452_WHO_AM_I 0x0d
-#define MMA8452_DATA_CFG 0x0e
-#define MMA8452_HP_FILTER_CUTOFF 0x0f
-#define MMA8452_HP_FILTER_CUTOFF_SEL_MASK	(BIT(0) | BIT(1))
-#define MMA8452_TRANSIENT_CFG 0x1d
-#define MMA8452_TRANSIENT_CFG_ELE		BIT(4)
-#define MMA8452_TRANSIENT_CFG_CHAN(chan)	BIT(chan + 1)
-#define MMA8452_TRANSIENT_CFG_HPF_BYP		BIT(0)
-#define MMA8452_TRANSIENT_SRC 0x1e
-#define MMA8452_TRANSIENT_SRC_XTRANSE		BIT(1)
-#define MMA8452_TRANSIENT_SRC_YTRANSE		BIT(3)
-#define MMA8452_TRANSIENT_SRC_ZTRANSE		BIT(5)
-#define MMA8452_TRANSIENT_THS 0x1f
-#define MMA8452_TRANSIENT_THS_MASK	0x7f
-#define MMA8452_TRANSIENT_COUNT 0x20
-#define MMA8452_OFF_X 0x2f
-#define MMA8452_OFF_Y 0x30
-#define MMA8452_OFF_Z 0x31
-#define MMA8452_CTRL_REG1 0x2a
-#define MMA8452_CTRL_REG2 0x2b
-#define MMA8452_CTRL_REG2_RST		BIT(6)
-#define MMA8452_CTRL_REG4 0x2d
-#define MMA8452_CTRL_REG5 0x2e
-
-#define MMA8452_MAX_REG 0x31
-
-#define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
-
-#define MMA8452_CTRL_DR_MASK (BIT(5) | BIT(4) | BIT(3))
-#define MMA8452_CTRL_DR_SHIFT 3
-#define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
-#define MMA8452_CTRL_ACTIVE BIT(0)
-
-#define MMA8452_DATA_CFG_FS_MASK (BIT(1) | BIT(0))
-#define MMA8452_DATA_CFG_FS_2G 0
-#define MMA8452_DATA_CFG_FS_4G 1
-#define MMA8452_DATA_CFG_FS_8G 2
-#define MMA8452_DATA_CFG_HPF_MASK BIT(4)
-
-#define MMA8452_INT_DRDY	BIT(0)
-#define MMA8452_INT_TRANS	BIT(5)
-
-#define MMA8452_DEVICE_ID 0x2a
+#define MMA8452_STATUS				0x00
+#define  MMA8452_STATUS_DRDY			(BIT(2) | BIT(1) | BIT(0))
+#define MMA8452_OUT_X				0x01 /* MSB first, 12-bit  */
+#define MMA8452_OUT_Y				0x03
+#define MMA8452_OUT_Z				0x05
+#define MMA8452_INT_SRC				0x0c
+#define MMA8452_WHO_AM_I			0x0d
+#define MMA8452_DATA_CFG			0x0e
+#define  MMA8452_DATA_CFG_FS_MASK		GENMASK(1, 0)
+#define  MMA8452_DATA_CFG_FS_2G			0
+#define  MMA8452_DATA_CFG_FS_4G			1
+#define  MMA8452_DATA_CFG_FS_8G			2
+#define  MMA8452_DATA_CFG_HPF_MASK		BIT(4)
+#define MMA8452_HP_FILTER_CUTOFF		0x0f
+#define  MMA8452_HP_FILTER_CUTOFF_SEL_MASK	GENMASK(1, 0)
+#define MMA8452_TRANSIENT_CFG			0x1d
+#define  MMA8452_TRANSIENT_CFG_HPF_BYP		BIT(0)
+#define  MMA8452_TRANSIENT_CFG_CHAN(chan)	BIT(chan + 1)
+#define  MMA8452_TRANSIENT_CFG_ELE		BIT(4)
+#define MMA8452_TRANSIENT_SRC			0x1e
+#define  MMA8452_TRANSIENT_SRC_XTRANSE		BIT(1)
+#define  MMA8452_TRANSIENT_SRC_YTRANSE		BIT(3)
+#define  MMA8452_TRANSIENT_SRC_ZTRANSE		BIT(5)
+#define MMA8452_TRANSIENT_THS			0x1f
+#define  MMA8452_TRANSIENT_THS_MASK		GENMASK(6, 0)
+#define MMA8452_TRANSIENT_COUNT			0x20
+#define MMA8452_CTRL_REG1			0x2a
+#define  MMA8452_CTRL_ACTIVE			BIT(0)
+#define  MMA8452_CTRL_DR_MASK			GENMASK(5, 3)
+#define  MMA8452_CTRL_DR_SHIFT			3
+#define  MMA8452_CTRL_DR_DEFAULT		0x4 /* 50 Hz sample frequency */
+#define MMA8452_CTRL_REG2			0x2b
+#define  MMA8452_CTRL_REG2_RST			BIT(6)
+#define MMA8452_CTRL_REG4			0x2d
+#define MMA8452_CTRL_REG5			0x2e
+#define MMA8452_OFF_X				0x2f
+#define MMA8452_OFF_Y				0x30
+#define MMA8452_OFF_Z				0x31
+
+#define MMA8452_MAX_REG				0x31
+
+#define  MMA8452_INT_DRDY			BIT(0)
+#define  MMA8452_INT_TRANS			BIT(5)
+
+#define  MMA8452_DEVICE_ID			0x2a
 
 struct mma8452_data {
 	struct i2c_client *client;
-- 
2.4.6

Re: [PATCH 5/7] iio:accel:mma8452: rework register definitions

[Jonathan Cameron]

On 02/08/15 21:43, Hartmut Knaack wrote:
> Rework register definitions to be sorted by register and bit number, with
> bit definitions cascaded under the appropriate register, use GENMASK for
> consecutive bitmasks and realign properly.
> 
> Signed-off-by: Hartmut Knaack <knaack.h@gmx.de>
Partly a matter of taste, but I like it and it does make things a little
easier to follow.  I wouldn't advocate bothering to do this for
all drivers though! (the reordering, the GENMASK stuff is fine everywhere!)

Applied

Jonathan
> ---
>  drivers/iio/accel/mma8452.c | 93 ++++++++++++++++++++++-----------------------
>  1 file changed, 45 insertions(+), 48 deletions(-)
> 
> diff --git a/drivers/iio/accel/mma8452.c b/drivers/iio/accel/mma8452.c
> index 516b6108d5f8..10e9623431e4 100644
> --- a/drivers/iio/accel/mma8452.c
> +++ b/drivers/iio/accel/mma8452.c
> @@ -23,54 +23,51 @@
>  #include <linux/iio/events.h>
>  #include <linux/delay.h>
>  
> -#define MMA8452_STATUS 0x00
> -#define MMA8452_OUT_X 0x01 /* MSB first, 12-bit  */
> -#define MMA8452_OUT_Y 0x03
> -#define MMA8452_OUT_Z 0x05
> -#define MMA8452_INT_SRC 0x0c
> -#define MMA8452_WHO_AM_I 0x0d
> -#define MMA8452_DATA_CFG 0x0e
> -#define MMA8452_HP_FILTER_CUTOFF 0x0f
> -#define MMA8452_HP_FILTER_CUTOFF_SEL_MASK	(BIT(0) | BIT(1))
> -#define MMA8452_TRANSIENT_CFG 0x1d
> -#define MMA8452_TRANSIENT_CFG_ELE		BIT(4)
> -#define MMA8452_TRANSIENT_CFG_CHAN(chan)	BIT(chan + 1)
> -#define MMA8452_TRANSIENT_CFG_HPF_BYP		BIT(0)
> -#define MMA8452_TRANSIENT_SRC 0x1e
> -#define MMA8452_TRANSIENT_SRC_XTRANSE		BIT(1)
> -#define MMA8452_TRANSIENT_SRC_YTRANSE		BIT(3)
> -#define MMA8452_TRANSIENT_SRC_ZTRANSE		BIT(5)
> -#define MMA8452_TRANSIENT_THS 0x1f
> -#define MMA8452_TRANSIENT_THS_MASK	0x7f
> -#define MMA8452_TRANSIENT_COUNT 0x20
> -#define MMA8452_OFF_X 0x2f
> -#define MMA8452_OFF_Y 0x30
> -#define MMA8452_OFF_Z 0x31
> -#define MMA8452_CTRL_REG1 0x2a
> -#define MMA8452_CTRL_REG2 0x2b
> -#define MMA8452_CTRL_REG2_RST		BIT(6)
> -#define MMA8452_CTRL_REG4 0x2d
> -#define MMA8452_CTRL_REG5 0x2e
> -
> -#define MMA8452_MAX_REG 0x31
> -
> -#define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
> -
> -#define MMA8452_CTRL_DR_MASK (BIT(5) | BIT(4) | BIT(3))
> -#define MMA8452_CTRL_DR_SHIFT 3
> -#define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
> -#define MMA8452_CTRL_ACTIVE BIT(0)
> -
> -#define MMA8452_DATA_CFG_FS_MASK (BIT(1) | BIT(0))
> -#define MMA8452_DATA_CFG_FS_2G 0
> -#define MMA8452_DATA_CFG_FS_4G 1
> -#define MMA8452_DATA_CFG_FS_8G 2
> -#define MMA8452_DATA_CFG_HPF_MASK BIT(4)
> -
> -#define MMA8452_INT_DRDY	BIT(0)
> -#define MMA8452_INT_TRANS	BIT(5)
> -
> -#define MMA8452_DEVICE_ID 0x2a
> +#define MMA8452_STATUS				0x00
> +#define  MMA8452_STATUS_DRDY			(BIT(2) | BIT(1) | BIT(0))
> +#define MMA8452_OUT_X				0x01 /* MSB first, 12-bit  */
> +#define MMA8452_OUT_Y				0x03
> +#define MMA8452_OUT_Z				0x05
> +#define MMA8452_INT_SRC				0x0c
> +#define MMA8452_WHO_AM_I			0x0d
> +#define MMA8452_DATA_CFG			0x0e
> +#define  MMA8452_DATA_CFG_FS_MASK		GENMASK(1, 0)
> +#define  MMA8452_DATA_CFG_FS_2G			0
> +#define  MMA8452_DATA_CFG_FS_4G			1
> +#define  MMA8452_DATA_CFG_FS_8G			2
> +#define  MMA8452_DATA_CFG_HPF_MASK		BIT(4)
> +#define MMA8452_HP_FILTER_CUTOFF		0x0f
> +#define  MMA8452_HP_FILTER_CUTOFF_SEL_MASK	GENMASK(1, 0)
> +#define MMA8452_TRANSIENT_CFG			0x1d
> +#define  MMA8452_TRANSIENT_CFG_HPF_BYP		BIT(0)
> +#define  MMA8452_TRANSIENT_CFG_CHAN(chan)	BIT(chan + 1)
> +#define  MMA8452_TRANSIENT_CFG_ELE		BIT(4)
> +#define MMA8452_TRANSIENT_SRC			0x1e
> +#define  MMA8452_TRANSIENT_SRC_XTRANSE		BIT(1)
> +#define  MMA8452_TRANSIENT_SRC_YTRANSE		BIT(3)
> +#define  MMA8452_TRANSIENT_SRC_ZTRANSE		BIT(5)
> +#define MMA8452_TRANSIENT_THS			0x1f
> +#define  MMA8452_TRANSIENT_THS_MASK		GENMASK(6, 0)
> +#define MMA8452_TRANSIENT_COUNT			0x20
> +#define MMA8452_CTRL_REG1			0x2a
> +#define  MMA8452_CTRL_ACTIVE			BIT(0)
> +#define  MMA8452_CTRL_DR_MASK			GENMASK(5, 3)
> +#define  MMA8452_CTRL_DR_SHIFT			3
> +#define  MMA8452_CTRL_DR_DEFAULT		0x4 /* 50 Hz sample frequency */
> +#define MMA8452_CTRL_REG2			0x2b
> +#define  MMA8452_CTRL_REG2_RST			BIT(6)
> +#define MMA8452_CTRL_REG4			0x2d
> +#define MMA8452_CTRL_REG5			0x2e
> +#define MMA8452_OFF_X				0x2f
> +#define MMA8452_OFF_Y				0x30
> +#define MMA8452_OFF_Z				0x31
> +
> +#define MMA8452_MAX_REG				0x31
> +
> +#define  MMA8452_INT_DRDY			BIT(0)
> +#define  MMA8452_INT_TRANS			BIT(5)
> +
> +#define  MMA8452_DEVICE_ID			0x2a
>  
>  struct mma8452_data {
>  	struct i2c_client *client;
> 

Re: [PATCH 5/7] iio:accel:mma8452: rework register definitions

[Hartmut Knaack]

Jonathan Cameron schrieb am 08.08.2015 um 18:36:
> On 02/08/15 21:43, Hartmut Knaack wrote:
>> Rework register definitions to be sorted by register and bit number, with
>> bit definitions cascaded under the appropriate register, use GENMASK for
>> consecutive bitmasks and realign properly.
>>
>> Signed-off-by: Hartmut Knaack <knaack.h@gmx.de>
> Partly a matter of taste, but I like it and it does make things a little
> easier to follow.  I wouldn't advocate bothering to do this for
> all drivers though! (the reordering, the GENMASK stuff is fine everywhere!)

No worries, this was mainly a "while I'm on it, I can get this done, too".
Thanks,
Hartmut

> 
> Applied
> 
> Jonathan
>> ---
>>  drivers/iio/accel/mma8452.c | 93 ++++++++++++++++++++++-----------------------
>>  1 file changed, 45 insertions(+), 48 deletions(-)
>>
>> diff --git a/drivers/iio/accel/mma8452.c b/drivers/iio/accel/mma8452.c
>> index 516b6108d5f8..10e9623431e4 100644
>> --- a/drivers/iio/accel/mma8452.c
>> +++ b/drivers/iio/accel/mma8452.c
>> @@ -23,54 +23,51 @@
>>  #include <linux/iio/events.h>
>>  #include <linux/delay.h>
>>  
>> -#define MMA8452_STATUS 0x00
>> -#define MMA8452_OUT_X 0x01 /* MSB first, 12-bit  */
>> -#define MMA8452_OUT_Y 0x03
>> -#define MMA8452_OUT_Z 0x05
>> -#define MMA8452_INT_SRC 0x0c
>> -#define MMA8452_WHO_AM_I 0x0d
>> -#define MMA8452_DATA_CFG 0x0e
>> -#define MMA8452_HP_FILTER_CUTOFF 0x0f
>> -#define MMA8452_HP_FILTER_CUTOFF_SEL_MASK	(BIT(0) | BIT(1))
>> -#define MMA8452_TRANSIENT_CFG 0x1d
>> -#define MMA8452_TRANSIENT_CFG_ELE		BIT(4)
>> -#define MMA8452_TRANSIENT_CFG_CHAN(chan)	BIT(chan + 1)
>> -#define MMA8452_TRANSIENT_CFG_HPF_BYP		BIT(0)
>> -#define MMA8452_TRANSIENT_SRC 0x1e
>> -#define MMA8452_TRANSIENT_SRC_XTRANSE		BIT(1)
>> -#define MMA8452_TRANSIENT_SRC_YTRANSE		BIT(3)
>> -#define MMA8452_TRANSIENT_SRC_ZTRANSE		BIT(5)
>> -#define MMA8452_TRANSIENT_THS 0x1f
>> -#define MMA8452_TRANSIENT_THS_MASK	0x7f
>> -#define MMA8452_TRANSIENT_COUNT 0x20
>> -#define MMA8452_OFF_X 0x2f
>> -#define MMA8452_OFF_Y 0x30
>> -#define MMA8452_OFF_Z 0x31
>> -#define MMA8452_CTRL_REG1 0x2a
>> -#define MMA8452_CTRL_REG2 0x2b
>> -#define MMA8452_CTRL_REG2_RST		BIT(6)
>> -#define MMA8452_CTRL_REG4 0x2d
>> -#define MMA8452_CTRL_REG5 0x2e
>> -
>> -#define MMA8452_MAX_REG 0x31
>> -
>> -#define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
>> -
>> -#define MMA8452_CTRL_DR_MASK (BIT(5) | BIT(4) | BIT(3))
>> -#define MMA8452_CTRL_DR_SHIFT 3
>> -#define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
>> -#define MMA8452_CTRL_ACTIVE BIT(0)
>> -
>> -#define MMA8452_DATA_CFG_FS_MASK (BIT(1) | BIT(0))
>> -#define MMA8452_DATA_CFG_FS_2G 0
>> -#define MMA8452_DATA_CFG_FS_4G 1
>> -#define MMA8452_DATA_CFG_FS_8G 2
>> -#define MMA8452_DATA_CFG_HPF_MASK BIT(4)
>> -
>> -#define MMA8452_INT_DRDY	BIT(0)
>> -#define MMA8452_INT_TRANS	BIT(5)
>> -
>> -#define MMA8452_DEVICE_ID 0x2a
>> +#define MMA8452_STATUS				0x00
>> +#define  MMA8452_STATUS_DRDY			(BIT(2) | BIT(1) | BIT(0))
>> +#define MMA8452_OUT_X				0x01 /* MSB first, 12-bit  */
>> +#define MMA8452_OUT_Y				0x03
>> +#define MMA8452_OUT_Z				0x05
>> +#define MMA8452_INT_SRC				0x0c
>> +#define MMA8452_WHO_AM_I			0x0d
>> +#define MMA8452_DATA_CFG			0x0e
>> +#define  MMA8452_DATA_CFG_FS_MASK		GENMASK(1, 0)
>> +#define  MMA8452_DATA_CFG_FS_2G			0
>> +#define  MMA8452_DATA_CFG_FS_4G			1
>> +#define  MMA8452_DATA_CFG_FS_8G			2
>> +#define  MMA8452_DATA_CFG_HPF_MASK		BIT(4)
>> +#define MMA8452_HP_FILTER_CUTOFF		0x0f
>> +#define  MMA8452_HP_FILTER_CUTOFF_SEL_MASK	GENMASK(1, 0)
>> +#define MMA8452_TRANSIENT_CFG			0x1d
>> +#define  MMA8452_TRANSIENT_CFG_HPF_BYP		BIT(0)
>> +#define  MMA8452_TRANSIENT_CFG_CHAN(chan)	BIT(chan + 1)
>> +#define  MMA8452_TRANSIENT_CFG_ELE		BIT(4)
>> +#define MMA8452_TRANSIENT_SRC			0x1e
>> +#define  MMA8452_TRANSIENT_SRC_XTRANSE		BIT(1)
>> +#define  MMA8452_TRANSIENT_SRC_YTRANSE		BIT(3)
>> +#define  MMA8452_TRANSIENT_SRC_ZTRANSE		BIT(5)
>> +#define MMA8452_TRANSIENT_THS			0x1f
>> +#define  MMA8452_TRANSIENT_THS_MASK		GENMASK(6, 0)
>> +#define MMA8452_TRANSIENT_COUNT			0x20
>> +#define MMA8452_CTRL_REG1			0x2a
>> +#define  MMA8452_CTRL_ACTIVE			BIT(0)
>> +#define  MMA8452_CTRL_DR_MASK			GENMASK(5, 3)
>> +#define  MMA8452_CTRL_DR_SHIFT			3
>> +#define  MMA8452_CTRL_DR_DEFAULT		0x4 /* 50 Hz sample frequency */
>> +#define MMA8452_CTRL_REG2			0x2b
>> +#define  MMA8452_CTRL_REG2_RST			BIT(6)
>> +#define MMA8452_CTRL_REG4			0x2d
>> +#define MMA8452_CTRL_REG5			0x2e
>> +#define MMA8452_OFF_X				0x2f
>> +#define MMA8452_OFF_Y				0x30
>> +#define MMA8452_OFF_Z				0x31
>> +
>> +#define MMA8452_MAX_REG				0x31
>> +
>> +#define  MMA8452_INT_DRDY			BIT(0)
>> +#define  MMA8452_INT_TRANS			BIT(5)
>> +
>> +#define  MMA8452_DEVICE_ID			0x2a
>>  
>>  struct mma8452_data {
>>  	struct i2c_client *client;
>>
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

[PATCH 6/7] iio:accel:mma8452: coding style cleanup

[Hartmut Knaack]

Some coding style cleanups, mainly indicated by checkpatch.pl, which
includes indentation changes, drop spaces after casts and befor tabs.
Also insert empty lines after logical blocks and before unconditional
returns.

Signed-off-by: Hartmut Knaack <knaack.h@gmx.de>
---
 drivers/iio/accel/mma8452.c | 106 ++++++++++++++++++++++++++++----------------
 1 file changed, 68 insertions(+), 38 deletions(-)

diff --git a/drivers/iio/accel/mma8452.c b/drivers/iio/accel/mma8452.c
index 10e9623431e4..d29f0dd64f00 100644
--- a/drivers/iio/accel/mma8452.c
+++ b/drivers/iio/accel/mma8452.c
@@ -87,30 +87,34 @@ static int mma8452_drdy(struct mma8452_data *data)
 			return ret;
 		if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
 			return 0;
+
 		msleep(20);
 	}
 
 	dev_err(&data->client->dev, "data not ready\n");
+
 	return -EIO;
 }
 
 static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
 {
 	int ret = mma8452_drdy(data);
+
 	if (ret < 0)
 		return ret;
-	return i2c_smbus_read_i2c_block_data(data->client,
-		MMA8452_OUT_X, 3 * sizeof(__be16), (u8 *) buf);
+
+	return i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
+					     3 * sizeof(__be16), (u8 *)buf);
 }
 
-static ssize_t mma8452_show_int_plus_micros(char *buf,
-	const int (*vals)[2], int n)
+static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
+					    int n)
 {
 	size_t len = 0;
 
 	while (n-- > 0)
-		len += scnprintf(buf + len, PAGE_SIZE - len,
-			"%d.%06d ", vals[n][0], vals[n][1]);
+		len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
+				 vals[n][0], vals[n][1]);
 
 	/* replace trailing space by newline */
 	buf[len - 1] = '\n';
@@ -119,7 +123,7 @@ static ssize_t mma8452_show_int_plus_micros(char *buf,
 }
 
 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
-					int val, int val2)
+					     int val, int val2)
 {
 	while (n-- > 0)
 		if (val == vals[n][0] && val2 == vals[n][1])
@@ -143,7 +147,7 @@ static const int mma8452_samp_freq[8][2] = {
  * Hardware has fullscale of -2G, -4G, -8G corresponding to raw value -2048
  * The userspace interface uses m/s^2 and we declare micro units
  * So scale factor is given by:
- * 	g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
+ *	g * N * 1000000 / 2048 for N = 2, 4, 8 and g = 9.80665
  */
 static const int mma8452_scales[3][2] = {
 	{0, 9577}, {0, 19154}, {0, 38307}
@@ -174,17 +178,19 @@ static const int mma8452_hp_filter_cutoff[8][4][2] = {
 };
 
 static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
-				struct device_attribute *attr, char *buf)
+					    struct device_attribute *attr,
+					    char *buf)
 {
 	return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
-		ARRAY_SIZE(mma8452_samp_freq));
+					    ARRAY_SIZE(mma8452_samp_freq));
 }
 
 static ssize_t mma8452_show_scale_avail(struct device *dev,
-				struct device_attribute *attr, char *buf)
+					struct device_attribute *attr,
+					char *buf)
 {
 	return mma8452_show_int_plus_micros(buf, mma8452_scales,
-		ARRAY_SIZE(mma8452_scales));
+					    ARRAY_SIZE(mma8452_scales));
 }
 
 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
@@ -201,22 +207,23 @@ static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
 
 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
 static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
-	mma8452_show_scale_avail, NULL, 0);
+		       mma8452_show_scale_avail, NULL, 0);
 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
-			S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
+		       S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
 
 static int mma8452_get_samp_freq_index(struct mma8452_data *data,
-	int val, int val2)
+				       int val, int val2)
 {
 	return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
-		ARRAY_SIZE(mma8452_samp_freq), val, val2);
+						 ARRAY_SIZE(mma8452_samp_freq),
+						 val, val2);
 }
 
-static int mma8452_get_scale_index(struct mma8452_data *data,
-	int val, int val2)
+static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
 {
 	return mma8452_get_int_plus_micros_index(mma8452_scales,
-		ARRAY_SIZE(mma8452_scales), val, val2);
+						 ARRAY_SIZE(mma8452_scales),
+						 val, val2);
 }
 
 static int mma8452_get_hp_filter_index(struct mma8452_data *data,
@@ -262,25 +269,31 @@ static int mma8452_read_raw(struct iio_dev *indio_dev,
 		mutex_unlock(&data->lock);
 		if (ret < 0)
 			return ret;
-		*val = sign_extend32(
-			be16_to_cpu(buffer[chan->scan_index]) >> 4, 11);
+
+		*val = sign_extend32(be16_to_cpu(buffer[chan->scan_index]) >> 4,
+				     11);
+
 		return IIO_VAL_INT;
 	case IIO_CHAN_INFO_SCALE:
 		i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
 		*val = mma8452_scales[i][0];
 		*val2 = mma8452_scales[i][1];
+
 		return IIO_VAL_INT_PLUS_MICRO;
 	case IIO_CHAN_INFO_SAMP_FREQ:
 		i = mma8452_get_odr_index(data);
 		*val = mma8452_samp_freq[i][0];
 		*val2 = mma8452_samp_freq[i][1];
+
 		return IIO_VAL_INT_PLUS_MICRO;
 	case IIO_CHAN_INFO_CALIBBIAS:
-		ret = i2c_smbus_read_byte_data(data->client, MMA8452_OFF_X +
-			chan->scan_index);
+		ret = i2c_smbus_read_byte_data(data->client,
+					      MMA8452_OFF_X + chan->scan_index);
 		if (ret < 0)
 			return ret;
+
 		*val = sign_extend32(ret, 7);
+
 		return IIO_VAL_INT;
 	case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
 		if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
@@ -291,21 +304,23 @@ static int mma8452_read_raw(struct iio_dev *indio_dev,
 			*val = 0;
 			*val2 = 0;
 		}
+
 		return IIO_VAL_INT_PLUS_MICRO;
 	}
+
 	return -EINVAL;
 }
 
 static int mma8452_standby(struct mma8452_data *data)
 {
 	return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
-		data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
+					data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
 }
 
 static int mma8452_active(struct mma8452_data *data)
 {
 	return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
-		data->ctrl_reg1);
+					 data->ctrl_reg1);
 }
 
 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
@@ -330,6 +345,7 @@ static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
 	ret = 0;
 fail:
 	mutex_unlock(&data->lock);
+
 	return ret;
 }
 
@@ -346,6 +362,7 @@ static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
 				       MMA8452_HP_FILTER_CUTOFF);
 	if (reg < 0)
 		return reg;
+
 	reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
 	reg |= i;
 
@@ -370,21 +387,26 @@ static int mma8452_write_raw(struct iio_dev *indio_dev,
 
 		data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
 		data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
+
 		return mma8452_change_config(data, MMA8452_CTRL_REG1,
-			data->ctrl_reg1);
+					     data->ctrl_reg1);
 	case IIO_CHAN_INFO_SCALE:
 		i = mma8452_get_scale_index(data, val, val2);
 		if (i < 0)
 			return i;
+
 		data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
 		data->data_cfg |= i;
+
 		return mma8452_change_config(data, MMA8452_DATA_CFG,
-			data->data_cfg);
+					     data->data_cfg);
 	case IIO_CHAN_INFO_CALIBBIAS:
 		if (val < -128 || val > 127)
 			return -EINVAL;
-		return mma8452_change_config(data, MMA8452_OFF_X +
-			chan->scan_index, val);
+
+		return mma8452_change_config(data,
+					     MMA8452_OFF_X + chan->scan_index,
+					     val);
 
 	case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
 		if (val == 0 && val2 == 0) {
@@ -395,8 +417,9 @@ static int mma8452_write_raw(struct iio_dev *indio_dev,
 			if (ret < 0)
 				return ret;
 		}
+
 		return mma8452_change_config(data, MMA8452_DATA_CFG,
-						data->data_cfg);
+					     data->data_cfg);
 
 	default:
 		return -EINVAL;
@@ -421,6 +444,7 @@ static int mma8452_read_thresh(struct iio_dev *indio_dev,
 			return ret;
 
 		*val = ret & MMA8452_TRANSIENT_THS_MASK;
+
 		return IIO_VAL_INT;
 
 	case IIO_EV_INFO_PERIOD:
@@ -433,6 +457,7 @@ static int mma8452_read_thresh(struct iio_dev *indio_dev,
 				mma8452_get_odr_index(data)];
 		*val = us / USEC_PER_SEC;
 		*val2 = us % USEC_PER_SEC;
+
 		return IIO_VAL_INT_PLUS_MICRO;
 
 	case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
@@ -449,6 +474,7 @@ static int mma8452_read_thresh(struct iio_dev *indio_dev,
 			if (ret < 0)
 				return ret;
 		}
+
 		return IIO_VAL_INT_PLUS_MICRO;
 
 	default:
@@ -483,6 +509,7 @@ static int mma8452_write_thresh(struct iio_dev *indio_dev,
 
 		return mma8452_change_config(data, MMA8452_TRANSIENT_COUNT,
 					     steps);
+
 	case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
 		reg = i2c_smbus_read_byte_data(data->client,
 					       MMA8452_TRANSIENT_CFG);
@@ -497,6 +524,7 @@ static int mma8452_write_thresh(struct iio_dev *indio_dev,
 			if (ret < 0)
 				return ret;
 		}
+
 		return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
 
 	default:
@@ -606,15 +634,16 @@ static irqreturn_t mma8452_trigger_handler(int irq, void *p)
 	u8 buffer[16]; /* 3 16-bit channels + padding + ts */
 	int ret;
 
-	ret = mma8452_read(data, (__be16 *) buffer);
+	ret = mma8452_read(data, (__be16 *)buffer);
 	if (ret < 0)
 		goto done;
 
 	iio_push_to_buffers_with_timestamp(indio_dev, buffer,
-		iio_get_time_ns());
+					   iio_get_time_ns());
 
 done:
 	iio_trigger_notify_done(indio_dev->trig);
+
 	return IRQ_HANDLED;
 }
 
@@ -672,10 +701,10 @@ static struct attribute_group mma8452_event_attribute_group = {
 	.modified = 1, \
 	.channel2 = IIO_MOD_##axis, \
 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
-		BIT(IIO_CHAN_INFO_CALIBBIAS), \
+			      BIT(IIO_CHAN_INFO_CALIBBIAS), \
 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
-		BIT(IIO_CHAN_INFO_SCALE) | \
-		BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
+			BIT(IIO_CHAN_INFO_SCALE) | \
+			BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
 	.scan_index = idx, \
 	.scan_type = { \
 		.sign = 's', \
@@ -778,6 +807,7 @@ static int mma8452_trigger_setup(struct iio_dev *indio_dev)
 		return ret;
 
 	indio_dev->trig = trig;
+
 	return 0;
 }
 
@@ -847,7 +877,7 @@ static int mma8452_probe(struct i2c_client *client,
 
 	data->data_cfg = MMA8452_DATA_CFG_FS_2G;
 	ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
-		data->data_cfg);
+					data->data_cfg);
 	if (ret < 0)
 		return ret;
 
@@ -889,14 +919,14 @@ static int mma8452_probe(struct i2c_client *client,
 	}
 
 	data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
-		(MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
+			  (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
 	ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
 					data->ctrl_reg1);
 	if (ret < 0)
 		goto trigger_cleanup;
 
 	ret = iio_triggered_buffer_setup(indio_dev, NULL,
-		mma8452_trigger_handler, NULL);
+					 mma8452_trigger_handler, NULL);
 	if (ret < 0)
 		goto trigger_cleanup;
 
-- 
2.4.6

Re: [PATCH 6/7] iio:accel:mma8452: coding style cleanup

[Jonathan Cameron]

On 02/08/15 21:43, Hartmut Knaack wrote:
> Some coding style cleanups, mainly indicated by checkpatch.pl, which
> includes indentation changes, drop spaces after casts and befor tabs.
> Also insert empty lines after logical blocks and before unconditional
> returns.
> 
> Signed-off-by: Hartmut Knaack <knaack.h@gmx.de>
There are some cases I couldn't care less about in here, but plenty of good stuff
so applied.

Jonathan
> ---
>  drivers/iio/accel/mma8452.c | 106 ++++++++++++++++++++++++++++----------------
>  1 file changed, 68 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/iio/accel/mma8452.c b/drivers/iio/accel/mma8452.c
> index 10e9623431e4..d29f0dd64f00 100644
> --- a/drivers/iio/accel/mma8452.c
> +++ b/drivers/iio/accel/mma8452.c
> @@ -87,30 +87,34 @@ static int mma8452_drdy(struct mma8452_data *data)
>  			return ret;
>  		if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
>  			return 0;
> +
>  		msleep(20);
>  	}
>  
>  	dev_err(&data->client->dev, "data not ready\n");
> +
>  	return -EIO;
>  }
>  
>  static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
>  {
>  	int ret = mma8452_drdy(data);
> +
>  	if (ret < 0)
>  		return ret;
> -	return i2c_smbus_read_i2c_block_data(data->client,
> -		MMA8452_OUT_X, 3 * sizeof(__be16), (u8 *) buf);
> +
> +	return i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
> +					     3 * sizeof(__be16), (u8 *)buf);
>  }
>  
> -static ssize_t mma8452_show_int_plus_micros(char *buf,
> -	const int (*vals)[2], int n)
> +static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
> +					    int n)
>  {
>  	size_t len = 0;
>  
>  	while (n-- > 0)
> -		len += scnprintf(buf + len, PAGE_SIZE - len,
> -			"%d.%06d ", vals[n][0], vals[n][1]);
> +		len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
> +				 vals[n][0], vals[n][1]);
>  
>  	/* replace trailing space by newline */
>  	buf[len - 1] = '\n';
> @@ -119,7 +123,7 @@ static ssize_t mma8452_show_int_plus_micros(char *buf,
>  }
>  
>  static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
> -					int val, int val2)
> +					     int val, int val2)
>  {
>  	while (n-- > 0)
>  		if (val == vals[n][0] && val2 == vals[n][1])
> @@ -143,7 +147,7 @@ static const int mma8452_samp_freq[8][2] = {
>   * Hardware has fullscale of -2G, -4G, -8G corresponding to raw value -2048
>   * The userspace interface uses m/s^2 and we declare micro units
>   * So scale factor is given by:
> - * 	g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
> + *	g * N * 1000000 / 2048 for N = 2, 4, 8 and g = 9.80665
>   */
>  static const int mma8452_scales[3][2] = {
>  	{0, 9577}, {0, 19154}, {0, 38307}
> @@ -174,17 +178,19 @@ static const int mma8452_hp_filter_cutoff[8][4][2] = {
>  };
>  
>  static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
> -				struct device_attribute *attr, char *buf)
> +					    struct device_attribute *attr,
> +					    char *buf)
>  {
>  	return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
> -		ARRAY_SIZE(mma8452_samp_freq));
> +					    ARRAY_SIZE(mma8452_samp_freq));
>  }
>  
>  static ssize_t mma8452_show_scale_avail(struct device *dev,
> -				struct device_attribute *attr, char *buf)
> +					struct device_attribute *attr,
> +					char *buf)
>  {
>  	return mma8452_show_int_plus_micros(buf, mma8452_scales,
> -		ARRAY_SIZE(mma8452_scales));
> +					    ARRAY_SIZE(mma8452_scales));
>  }
>  
>  static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
> @@ -201,22 +207,23 @@ static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
>  
>  static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
>  static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
> -	mma8452_show_scale_avail, NULL, 0);
> +		       mma8452_show_scale_avail, NULL, 0);
>  static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
> -			S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
> +		       S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
>  
>  static int mma8452_get_samp_freq_index(struct mma8452_data *data,
> -	int val, int val2)
> +				       int val, int val2)
>  {
>  	return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
> -		ARRAY_SIZE(mma8452_samp_freq), val, val2);
> +						 ARRAY_SIZE(mma8452_samp_freq),
> +						 val, val2);
>  }
>  
> -static int mma8452_get_scale_index(struct mma8452_data *data,
> -	int val, int val2)
> +static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
>  {
>  	return mma8452_get_int_plus_micros_index(mma8452_scales,
> -		ARRAY_SIZE(mma8452_scales), val, val2);
> +						 ARRAY_SIZE(mma8452_scales),
> +						 val, val2);
>  }
>  
>  static int mma8452_get_hp_filter_index(struct mma8452_data *data,
> @@ -262,25 +269,31 @@ static int mma8452_read_raw(struct iio_dev *indio_dev,
>  		mutex_unlock(&data->lock);
>  		if (ret < 0)
>  			return ret;
> -		*val = sign_extend32(
> -			be16_to_cpu(buffer[chan->scan_index]) >> 4, 11);
> +
> +		*val = sign_extend32(be16_to_cpu(buffer[chan->scan_index]) >> 4,
> +				     11);
> +
>  		return IIO_VAL_INT;
>  	case IIO_CHAN_INFO_SCALE:
>  		i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
>  		*val = mma8452_scales[i][0];
>  		*val2 = mma8452_scales[i][1];
> +
>  		return IIO_VAL_INT_PLUS_MICRO;
>  	case IIO_CHAN_INFO_SAMP_FREQ:
>  		i = mma8452_get_odr_index(data);
>  		*val = mma8452_samp_freq[i][0];
>  		*val2 = mma8452_samp_freq[i][1];
> +
>  		return IIO_VAL_INT_PLUS_MICRO;
>  	case IIO_CHAN_INFO_CALIBBIAS:
> -		ret = i2c_smbus_read_byte_data(data->client, MMA8452_OFF_X +
> -			chan->scan_index);
> +		ret = i2c_smbus_read_byte_data(data->client,
> +					      MMA8452_OFF_X + chan->scan_index);
>  		if (ret < 0)
>  			return ret;
> +
>  		*val = sign_extend32(ret, 7);
> +
>  		return IIO_VAL_INT;
>  	case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
>  		if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
> @@ -291,21 +304,23 @@ static int mma8452_read_raw(struct iio_dev *indio_dev,
>  			*val = 0;
>  			*val2 = 0;
>  		}
> +
>  		return IIO_VAL_INT_PLUS_MICRO;
>  	}
> +
>  	return -EINVAL;
>  }
>  
>  static int mma8452_standby(struct mma8452_data *data)
>  {
>  	return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
> -		data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
> +					data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
>  }
>  
>  static int mma8452_active(struct mma8452_data *data)
>  {
>  	return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
> -		data->ctrl_reg1);
> +					 data->ctrl_reg1);
>  }
>  
>  static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
> @@ -330,6 +345,7 @@ static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
>  	ret = 0;
>  fail:
>  	mutex_unlock(&data->lock);
> +
>  	return ret;
>  }
>  
> @@ -346,6 +362,7 @@ static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
>  				       MMA8452_HP_FILTER_CUTOFF);
>  	if (reg < 0)
>  		return reg;
> +
>  	reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
>  	reg |= i;
>  
> @@ -370,21 +387,26 @@ static int mma8452_write_raw(struct iio_dev *indio_dev,
>  
>  		data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
>  		data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
> +
>  		return mma8452_change_config(data, MMA8452_CTRL_REG1,
> -			data->ctrl_reg1);
> +					     data->ctrl_reg1);
>  	case IIO_CHAN_INFO_SCALE:
>  		i = mma8452_get_scale_index(data, val, val2);
>  		if (i < 0)
>  			return i;
> +
>  		data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
>  		data->data_cfg |= i;
> +
>  		return mma8452_change_config(data, MMA8452_DATA_CFG,
> -			data->data_cfg);
> +					     data->data_cfg);
>  	case IIO_CHAN_INFO_CALIBBIAS:
>  		if (val < -128 || val > 127)
>  			return -EINVAL;
> -		return mma8452_change_config(data, MMA8452_OFF_X +
> -			chan->scan_index, val);
> +
> +		return mma8452_change_config(data,
> +					     MMA8452_OFF_X + chan->scan_index,
> +					     val);
>  
>  	case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
>  		if (val == 0 && val2 == 0) {
> @@ -395,8 +417,9 @@ static int mma8452_write_raw(struct iio_dev *indio_dev,
>  			if (ret < 0)
>  				return ret;
>  		}
> +
>  		return mma8452_change_config(data, MMA8452_DATA_CFG,
> -						data->data_cfg);
> +					     data->data_cfg);
>  
>  	default:
>  		return -EINVAL;
> @@ -421,6 +444,7 @@ static int mma8452_read_thresh(struct iio_dev *indio_dev,
>  			return ret;
>  
>  		*val = ret & MMA8452_TRANSIENT_THS_MASK;
> +
>  		return IIO_VAL_INT;
>  
>  	case IIO_EV_INFO_PERIOD:
> @@ -433,6 +457,7 @@ static int mma8452_read_thresh(struct iio_dev *indio_dev,
>  				mma8452_get_odr_index(data)];
>  		*val = us / USEC_PER_SEC;
>  		*val2 = us % USEC_PER_SEC;
> +
>  		return IIO_VAL_INT_PLUS_MICRO;
>  
>  	case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
> @@ -449,6 +474,7 @@ static int mma8452_read_thresh(struct iio_dev *indio_dev,
>  			if (ret < 0)
>  				return ret;
>  		}
> +
>  		return IIO_VAL_INT_PLUS_MICRO;
>  
>  	default:
> @@ -483,6 +509,7 @@ static int mma8452_write_thresh(struct iio_dev *indio_dev,
>  
>  		return mma8452_change_config(data, MMA8452_TRANSIENT_COUNT,
>  					     steps);
> +
>  	case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
>  		reg = i2c_smbus_read_byte_data(data->client,
>  					       MMA8452_TRANSIENT_CFG);
> @@ -497,6 +524,7 @@ static int mma8452_write_thresh(struct iio_dev *indio_dev,
>  			if (ret < 0)
>  				return ret;
>  		}
> +
>  		return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
>  
>  	default:
> @@ -606,15 +634,16 @@ static irqreturn_t mma8452_trigger_handler(int irq, void *p)
>  	u8 buffer[16]; /* 3 16-bit channels + padding + ts */
>  	int ret;
>  
> -	ret = mma8452_read(data, (__be16 *) buffer);
> +	ret = mma8452_read(data, (__be16 *)buffer);
>  	if (ret < 0)
>  		goto done;
>  
>  	iio_push_to_buffers_with_timestamp(indio_dev, buffer,
> -		iio_get_time_ns());
> +					   iio_get_time_ns());
>  
>  done:
>  	iio_trigger_notify_done(indio_dev->trig);
> +
>  	return IRQ_HANDLED;
>  }
>  
> @@ -672,10 +701,10 @@ static struct attribute_group mma8452_event_attribute_group = {
>  	.modified = 1, \
>  	.channel2 = IIO_MOD_##axis, \
>  	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
> -		BIT(IIO_CHAN_INFO_CALIBBIAS), \
> +			      BIT(IIO_CHAN_INFO_CALIBBIAS), \
>  	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
> -		BIT(IIO_CHAN_INFO_SCALE) | \
> -		BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
> +			BIT(IIO_CHAN_INFO_SCALE) | \
> +			BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
>  	.scan_index = idx, \
>  	.scan_type = { \
>  		.sign = 's', \
> @@ -778,6 +807,7 @@ static int mma8452_trigger_setup(struct iio_dev *indio_dev)
>  		return ret;
>  
>  	indio_dev->trig = trig;
> +
>  	return 0;
>  }
>  
> @@ -847,7 +877,7 @@ static int mma8452_probe(struct i2c_client *client,
>  
>  	data->data_cfg = MMA8452_DATA_CFG_FS_2G;
>  	ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
> -		data->data_cfg);
> +					data->data_cfg);
>  	if (ret < 0)
>  		return ret;
>  
> @@ -889,14 +919,14 @@ static int mma8452_probe(struct i2c_client *client,
>  	}
>  
>  	data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
> -		(MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
> +			  (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
>  	ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
>  					data->ctrl_reg1);
>  	if (ret < 0)
>  		goto trigger_cleanup;
>  
>  	ret = iio_triggered_buffer_setup(indio_dev, NULL,
> -		mma8452_trigger_handler, NULL);
> +					 mma8452_trigger_handler, NULL);
>  	if (ret < 0)
>  		goto trigger_cleanup;
>  
> 

[PATCH 7/7] iio:accel:mma8452: reorder Kconfig entry

[Hartmut Knaack]

Move the entry in Kconfig to its alphabetically correct position.

Signed-off-by: Hartmut Knaack <knaack.h@gmx.de>
---
 drivers/iio/accel/Kconfig | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/iio/accel/Kconfig b/drivers/iio/accel/Kconfig
index 00e7bcbdbe24..b8fc12c7640b 100644
--- a/drivers/iio/accel/Kconfig
+++ b/drivers/iio/accel/Kconfig
@@ -86,18 +86,6 @@ config KXSD9
 	  To compile this driver as a module, choose M here: the module
 	  will be called kxsd9.
 
-config MMA8452
-	tristate "Freescale MMA8452Q Accelerometer Driver"
-	depends on I2C
-	select IIO_BUFFER
-	select IIO_TRIGGERED_BUFFER
-	help
-	  Say yes here to build support for the Freescale MMA8452Q 3-axis
-	  accelerometer.
-
-	  To compile this driver as a module, choose M here: the module
-	  will be called mma8452.
-
 config KXCJK1013
 	tristate "Kionix 3-Axis Accelerometer Driver"
 	depends on I2C
@@ -111,6 +99,18 @@ config KXCJK1013
 	  To compile this driver as a module, choose M here: the module will
 	  be called kxcjk-1013.
 
+config MMA8452
+	tristate "Freescale MMA8452Q Accelerometer Driver"
+	depends on I2C
+	select IIO_BUFFER
+	select IIO_TRIGGERED_BUFFER
+	help
+	  Say yes here to build support for the Freescale MMA8452Q 3-axis
+	  accelerometer.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called mma8452.
+
 config MMA9551_CORE
 	tristate
 
-- 
2.4.6

Re: [PATCH 7/7] iio:accel:mma8452: reorder Kconfig entry

[Jonathan Cameron]

On 02/08/15 21:43, Hartmut Knaack wrote:
> Move the entry in Kconfig to its alphabetically correct position.
> 
> Signed-off-by: Hartmut Knaack <knaack.h@gmx.de>
Applied
> ---
>  drivers/iio/accel/Kconfig | 24 ++++++++++++------------
>  1 file changed, 12 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/iio/accel/Kconfig b/drivers/iio/accel/Kconfig
> index 00e7bcbdbe24..b8fc12c7640b 100644
> --- a/drivers/iio/accel/Kconfig
> +++ b/drivers/iio/accel/Kconfig
> @@ -86,18 +86,6 @@ config KXSD9
>  	  To compile this driver as a module, choose M here: the module
>  	  will be called kxsd9.
>  
> -config MMA8452
> -	tristate "Freescale MMA8452Q Accelerometer Driver"
> -	depends on I2C
> -	select IIO_BUFFER
> -	select IIO_TRIGGERED_BUFFER
> -	help
> -	  Say yes here to build support for the Freescale MMA8452Q 3-axis
> -	  accelerometer.
> -
> -	  To compile this driver as a module, choose M here: the module
> -	  will be called mma8452.
> -
>  config KXCJK1013
>  	tristate "Kionix 3-Axis Accelerometer Driver"
>  	depends on I2C
> @@ -111,6 +99,18 @@ config KXCJK1013
>  	  To compile this driver as a module, choose M here: the module will
>  	  be called kxcjk-1013.
>  
> +config MMA8452
> +	tristate "Freescale MMA8452Q Accelerometer Driver"
> +	depends on I2C
> +	select IIO_BUFFER
> +	select IIO_TRIGGERED_BUFFER
> +	help
> +	  Say yes here to build support for the Freescale MMA8452Q 3-axis
> +	  accelerometer.
> +
> +	  To compile this driver as a module, choose M here: the module
> +	  will be called mma8452.
> +
>  config MMA9551_CORE
>  	tristate
>  
>